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From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
	Dan Williams <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
	<vishal.l.verma@intel.com>, <alison.schofield@intel.com>
Subject: Re: [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem
Date: Tue, 16 May 2023 14:49:46 -0700	[thread overview]
Message-ID: <6463fa7ae35c4_250e2941f@dwillia2-mobl3.amr.corp.intel.com.notmuch> (raw)
In-Reply-To: <20230512162831.00003b34@Huawei.com>

Jonathan Cameron wrote:
> Hi Dave,
> 
> > The QTG ID for a device is retrieved via sending a _DSM method to the ACPI0017 device.
> > The _DSM expects an input package of 4 DWORDS that contains the read latency, write
> > latency, read bandwidth, and write banwidth. These are the caluclated numbers for the
> > path between the CXL device and the CPU. The QTG ID is also exported as a sysfs
> > attribute under the mem device memory partition type:
> > /sys/bus/cxl/devices/memX/ram/qos_class
> > /sys/bus/cxl/devices/memX/pmem/qos_class
> > Only the first QTG ID is exported.
> 
> The QTG DSM returning a list was done to allow for a case of mutual
> incompatibility between the first QTG that is returned for a particular
> performance point and the CFMWS that it points at.
> 
> CFMWS might say 'no pmem in here' but due to some RAM device that is a bit
> slow, we might end up with a QTG DSM response that says put it in that CFMWS.
> 
> Hence the fallback list.
> 
> That is currently hidden by this approach.  It makes things more complex, but
> I'd really like to see the whole of that list rather than just the first element
> presented for each region.  I think it's fine to let userspace then figure
> out if there is a missmatch.

There is some confusion here, the "Only the first QTG ID is exported"
statement is with respect to the case of multiple DSMAS entries per
partition. For the case of multiple platform QoS classes per single
DSMAS I would be ok if this qos_class returned a comma-separated
list/tuple.

So, for example, in a case where DSMAS0 for the 'ram' partition results
in QoS class-ids 0,1,2 and DSMAS1 for the 'ram' partition results in QoS
class-ids 3,4 then /sys/bus/cxl/devices/memX/ram/qos_class would be
allowed to report "0,1,2".

  reply	other threads:[~2023-05-16 21:49 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-08 20:46 [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-08 20:46 ` [PATCH v5 01/14] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-12 14:26   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 02/14] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-12 14:33   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 03/14] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-12 14:41   ` Jonathan Cameron
2023-05-16 17:49     ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 04/14] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-12 14:50   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 05/14] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-08 20:47 ` [PATCH v5 06/14] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-05-12 14:59   ` Jonathan Cameron
2023-05-16 20:58     ` Dave Jiang
2023-05-16 21:13       ` Dan Williams
2023-05-16 21:52         ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 07/14] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-12 15:05   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 08/14] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-12 15:09   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 09/14] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-05-12 15:16   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 10/14] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-05-12 15:17   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 11/14] cxl: Move read_cdat_data() to after media is ready Dave Jiang
2023-05-12 15:18   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 12/14] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-05-12 15:30   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 13/14] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-05-12 15:33   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 14/14] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-05-12 15:36   ` Jonathan Cameron
2023-05-17 22:28     ` Dave Jiang
2023-05-12 15:28 ` [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Jonathan Cameron
2023-05-16 21:49   ` Dan Williams [this message]
2023-05-17  8:50     ` Jonathan Cameron

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