From: Dave Jiang <dave.jiang@intel.com>
To: Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: linux-cxl@vger.kernel.org, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com
Subject: Re: [PATCH v5 06/14] cxl: Store the access coordinates for the generic ports
Date: Tue, 16 May 2023 14:52:18 -0700 [thread overview]
Message-ID: <a917cba3-2549-d89d-729a-3f849e134d4b@intel.com> (raw)
In-Reply-To: <6463f1e8d963d_250e2942a@dwillia2-mobl3.amr.corp.intel.com.notmuch>
On 5/16/23 2:13 PM, Dan Williams wrote:
> Dave Jiang wrote:
>>
>>
>> On 5/12/23 7:59 AM, Jonathan Cameron wrote:
>>> On Mon, 08 May 2023 13:47:29 -0700
>>> Dave Jiang <dave.jiang@intel.com> wrote:
>>>
>>>> Each CXL host bridge is represented by an ACPI0016 device. A generic port
>>>> device handle that is an ACPI device is represented by a string of
>>>> ACPI0016 device HID and UID. Create a device handle from the ACPI device
>>>> and retrieve the access coordinates from the stored memory targets. The
>>>> access coordinates are stored under the cxl_dport that is associated with
>>>> the CXL host bridge.
>>>>
>>>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>>>> ---
>>>> drivers/cxl/acpi.c | 28 ++++++++++++++++++++++++++++
>>>> drivers/cxl/cxl.h | 2 ++
>>>> 2 files changed, 30 insertions(+)
>>>>
>>>> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
>>>> index f9b35e8fe810..675a4f423f4b 100644
>>>> --- a/drivers/cxl/acpi.c
>>>> +++ b/drivers/cxl/acpi.c
>>>> @@ -537,8 +537,26 @@ static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
>>>> return 0;
>>>> }
>>>>
>>>> +static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
>>>> +{
>>>> + struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);
>>>> + u8 handle[ACPI_SRAT_DEVICE_HANDLE_SIZE] = { 0 };
>>>> + int rc;
>>>> +
>>>> + /* ACPI spec 6.5 tABLE 5.65 */
>>>
>>> tABLE?
>>
>> ooops caps lock
>>
>>>
>>>> + memcpy(handle, acpi_device_hid(hb), 8);
>>>> + memcpy(&handle[8], acpi_device_uid(hb), 4);
>>>> +
>>>> + rc = acpi_get_genport_coordinates(handle, dport->genport_coord);
>>>> + if (rc)
>>>> + return rc;
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> static int add_host_bridge_dport(struct device *match, void *arg)
>>>> {
>>>> + int ret;
>>>> acpi_status rc;
>>>> struct device *bridge;
>>>> unsigned long long uid;
>>>> @@ -594,6 +612,16 @@ static int add_host_bridge_dport(struct device *match, void *arg)
>>>> if (IS_ERR(dport))
>>>> return PTR_ERR(dport);
>>>>
>>>> + dport->genport_coord = devm_kzalloc(dport->dport,
>
> This needs to be the same device as was used to allocate @dport, and
> that's not @dport->dport.
ok
>
>>>> + sizeof(*dport->genport_coord),
>>>> + GFP_KERNEL);
>>>
>>> It's pretty small - worth allocating separately?
>>>
>>> Maybe add something on why to the patch description if there is another reason
>>> for this dance.
>>
>> My intention was to allow detection of whether the data exists or not
>> based on if the ptr is NULL. I'll add explanation in patch description.
>
> A couple reactions, is a "zero" access coordinate not sufficient for
> that?
Probably. I can change. I was being paranoid.
>
> Also, "genport" is an ACPI-ism and I was aiming for cxl-core objects
> like cxl_dport to remain platform implementation independent. The
> concept of a dport having a host-bridge access_coordinate is generic
> though, so I would just rename this to "hb_access" or some other
> host-bridge generic naming.
Ok
next prev parent reply other threads:[~2023-05-16 21:53 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-08 20:46 [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-08 20:46 ` [PATCH v5 01/14] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-12 14:26 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 02/14] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-12 14:33 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 03/14] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-12 14:41 ` Jonathan Cameron
2023-05-16 17:49 ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 04/14] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-12 14:50 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 05/14] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-08 20:47 ` [PATCH v5 06/14] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-05-12 14:59 ` Jonathan Cameron
2023-05-16 20:58 ` Dave Jiang
2023-05-16 21:13 ` Dan Williams
2023-05-16 21:52 ` Dave Jiang [this message]
2023-05-08 20:47 ` [PATCH v5 07/14] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-12 15:05 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 08/14] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-12 15:09 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 09/14] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-05-12 15:16 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 10/14] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-05-12 15:17 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 11/14] cxl: Move read_cdat_data() to after media is ready Dave Jiang
2023-05-12 15:18 ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 12/14] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-05-12 15:30 ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 13/14] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-05-12 15:33 ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 14/14] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-05-12 15:36 ` Jonathan Cameron
2023-05-17 22:28 ` Dave Jiang
2023-05-12 15:28 ` [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Jonathan Cameron
2023-05-16 21:49 ` Dan Williams
2023-05-17 8:50 ` Jonathan Cameron
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