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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
	Dan Williams <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
	<vishal.l.verma@intel.com>, <alison.schofield@intel.com>
Subject: Re: [PATCH v5 14/14] cxl/mem: Add debugfs output for QTG related data
Date: Fri, 12 May 2023 16:36:42 +0100	[thread overview]
Message-ID: <20230512163642.00002715@Huawei.com> (raw)
In-Reply-To: <168357889673.2756219.5112791678818283230.stgit@djiang5-mobl3>

On Mon, 08 May 2023 13:48:16 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Add debugfs output to /sys/kernel/debug/cxl/memX/qtgmap
> The debugfs attribute will dump out all the DSMAS ranges and the associated
> QTG ID exported by the CXL device CDAT.
> 
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

LTGM, though seems we haven't been keeping up with ABI docs for other
stuff in debugfs. That wants fixing but is unrelated to this.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> 
> ---
> v4:
> - Use cxlds->qos_list instead of the stray cxlmd->qos_list
> ---
>  Documentation/ABI/testing/debugfs-cxl |   11 +++++++++++
>  MAINTAINERS                           |    1 +
>  drivers/cxl/mem.c                     |   17 +++++++++++++++++
>  3 files changed, 29 insertions(+)
>  create mode 100644 Documentation/ABI/testing/debugfs-cxl
> 
> diff --git a/Documentation/ABI/testing/debugfs-cxl b/Documentation/ABI/testing/debugfs-cxl
> new file mode 100644
> index 000000000000..0f36eeb7e59b
> --- /dev/null
> +++ b/Documentation/ABI/testing/debugfs-cxl
> @@ -0,0 +1,11 @@
> +What:		/sys/kernel/debug/cxl/memX/qtg_map
> +Date:		Mar, 2023
> +KernelVersion:	v6.4
> +Contact:	linux-cxl@vger.kernel.org
> +Description:
> +		(RO) Entries of all Device Physical Address (DPA) ranges
> +		provided by the device Coherent Device Attributes Table (CDAT)
> +		Device Scoped Memory Affinity Structure (DSMAS) entries with
> +		the matching QoS Throttling Group (QTG) id calculated from the
> +		latency and bandwidth of the CXL path from the memory device
> +		to the CPU.

Curious. This file should already exist as there is clearly more debugfs ABI
from the code below.  Perhaps a precursor patch to create the file and document
existing interfaces?

> diff --git a/MAINTAINERS b/MAINTAINERS
> index fd8c4c560f8d..256e4e57017c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5171,6 +5171,7 @@ M:	Ben Widawsky <bwidawsk@kernel.org>
>  M:	Dan Williams <dan.j.williams@intel.com>
>  L:	linux-cxl@vger.kernel.org
>  S:	Maintained
> +F:	Documentation/ABI/testing/debugfs-cxl
>  F:	drivers/cxl/
>  F:	include/uapi/linux/cxl_mem.h
>  
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 39c4b54f0715..587e261a7f76 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -45,6 +45,22 @@ static int cxl_mem_dpa_show(struct seq_file *file, void *data)
>  	return 0;
>  }
>  
> +static int cxl_mem_qtg_show(struct seq_file *file, void *data)
> +{
> +	struct device *dev = file->private;
> +	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> +	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> +	struct perf_prop_entry *perf;
> +
> +	list_for_each_entry(perf, &cxlds->perf_list, list) {
> +		seq_printf(file, "%08llx-%08llx : QoS Class: %u\n",
> +			   perf->dpa_range.start, perf->dpa_range.end,
> +			   perf->qos_class);
> +	}
> +
> +	return 0;
> +}
> +
>  static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
>  				 struct cxl_dport *parent_dport)
>  {
> @@ -117,6 +133,7 @@ static int cxl_mem_probe(struct device *dev)
>  
>  	dentry = cxl_debugfs_create_dir(dev_name(dev));
>  	debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
> +	debugfs_create_devm_seqfile(dev, "qtgmap", dentry, cxl_mem_qtg_show);
>  	rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
>  	if (rc)
>  		return rc;
> 
> 


  reply	other threads:[~2023-05-12 15:36 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-08 20:46 [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-08 20:46 ` [PATCH v5 01/14] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-12 14:26   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 02/14] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-12 14:33   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 03/14] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-12 14:41   ` Jonathan Cameron
2023-05-16 17:49     ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 04/14] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-12 14:50   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 05/14] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-08 20:47 ` [PATCH v5 06/14] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-05-12 14:59   ` Jonathan Cameron
2023-05-16 20:58     ` Dave Jiang
2023-05-16 21:13       ` Dan Williams
2023-05-16 21:52         ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 07/14] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-12 15:05   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 08/14] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-12 15:09   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 09/14] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-05-12 15:16   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 10/14] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-05-12 15:17   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 11/14] cxl: Move read_cdat_data() to after media is ready Dave Jiang
2023-05-12 15:18   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 12/14] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-05-12 15:30   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 13/14] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-05-12 15:33   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 14/14] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-05-12 15:36   ` Jonathan Cameron [this message]
2023-05-17 22:28     ` Dave Jiang
2023-05-12 15:28 ` [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Jonathan Cameron
2023-05-16 21:49   ` Dan Williams
2023-05-17  8:50     ` Jonathan Cameron

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