[PATCH v7 0/5] Add microchip sama7d65 SoC I3C support

[PATCH v7 0/5] Add microchip sama7d65 SoC I3C support

[Manikandan Muralidharan]

Add support for microchip sama7d65 SoC I3C master only IP which is
based on mipi-i3c-hci from synopsys implementing version 1.0
specification. The platform specific changes are integrated in the
mipi-i3c-hci driver using existing quirks.

I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
mixed bus mode (I2C and I3C target devices on same i3c bus).

Please refer to the individual patches for changelogs.

Durai Manickam KR (2):
  clk: at91: sama7d65: add peripheral clock for I3C
  ARM: dts: microchip: add I3C controller

Manikandan Muralidharan (3):
  dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible
  i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the
    required quirk
  ARM: configs: at91: sama7: add sama7d65 i3c-hci

 .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 27 ++++++++++++++++---
 arch/arm/boot/dts/microchip/sama7d65.dtsi     |  8 ++++++
 arch/arm/configs/sama7_defconfig              |  2 ++
 drivers/clk/at91/sama7d65.c                   |  1 +
 drivers/i3c/master/mipi-i3c-hci/core.c        | 10 +++++++
 5 files changed, 44 insertions(+), 4 deletions(-)

-- 
2.25.1

[PATCH v7 1/5] dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible

[Manikandan Muralidharan]

Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C
HCI binding. The Microchip SAMA7D65 I3C controller is based on the
MIPI HCI specification but requires two clocks, so add a conditional
constraint when this compatible is present.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
---
Changes in v5:
- drop min/maxItems around clock entries
- use if/then/else clause instead of separate allOf entry
- cosmetic fixes for indentation and formatting

Changes in v4:
- Define and describe the clock property in the top-level properties
  section rather than inside the if/then conditional

 .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 27 ++++++++++++++++---
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml
index 39bb1a1784c9..d488fb420945 100644
--- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml
+++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml
@@ -9,9 +9,6 @@ title: MIPI I3C HCI
 maintainers:
   - Nicolas Pitre <npitre@baylibre.com>
 
-allOf:
-  - $ref: /schemas/i3c/i3c.yaml#
-
 description: |
   MIPI I3C Host Controller Interface
 
@@ -28,9 +25,17 @@ description: |
 
 properties:
   compatible:
-    const: mipi-i3c-hci
+    enum:
+      - mipi-i3c-hci
+      - microchip,sama7d65-i3c-hci
   reg:
     maxItems: 1
+
+  clocks:
+    items:
+      - description: Peripheral bus clock
+      - description: System Generic clock
+
   interrupts:
     maxItems: 1
 
@@ -39,6 +44,20 @@ required:
   - reg
   - interrupts
 
+allOf:
+  - $ref: /schemas/i3c/i3c.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: microchip,sama7d65-i3c-hci
+    then:
+      required:
+        - clocks
+    else:
+      properties:
+        clocks: false
+
 unevaluatedProperties: false
 
 examples:
-- 
2.25.1

[PATCH v7 2/5] clk: at91: sama7d65: add peripheral clock for I3C

[Manikandan Muralidharan]

From: Durai Manickam KR <durai.manickamkr@microchip.com>

Add peripheral clock description for I3C.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
---
Changes in v3:
- Fixed indentation issues in the clock table entry

 drivers/clk/at91/sama7d65.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
index 7dee2b160ffb..ba8ff413fa2c 100644
--- a/drivers/clk/at91/sama7d65.c
+++ b/drivers/clk/at91/sama7d65.c
@@ -677,6 +677,7 @@ static struct {
 	{ .n = "uhphs_clk",	.p = PCK_PARENT_HW_MCK5, .id = 101, },
 	{ .n = "dsi_clk",	.p = PCK_PARENT_HW_MCK3, .id = 103, },
 	{ .n = "lvdsc_clk",	.p = PCK_PARENT_HW_MCK3, .id = 104, },
+	{ .n = "i3cc_clk",	.p = PCK_PARENT_HW_MCK8, .id = 105, },
 };
 
 /*
-- 
2.25.1

Re: [PATCH v7 2/5] clk: at91: sama7d65: add peripheral clock for I3C

[Claudiu Beznea]

On 5/25/26 12:24, Manikandan Muralidharan wrote:
> From: Durai Manickam KR<durai.manickamkr@microchip.com>
> 
> Add peripheral clock description for I3C.
> 
> Signed-off-by: Durai Manickam KR<durai.manickamkr@microchip.com>
> Reviewed-by: Claudiu Beznea<claudiu.beznea@tuxon.dev>
> Signed-off-by: Manikandan Muralidharan<manikandan.m@microchip.com>

Applied to clk-microchip, thanks!

[PATCH v7 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk

[Manikandan Muralidharan]

Add support for microchip sama7d65 SoC I3C HCI master only IP
with additional clock support to enable bulk clock acquisition
and apply the required quirks.

Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
---
Changes in v7:
- Use (void *)(ulong) cast instead of direct (void *) cast in
  of_device_id.data for pointer-size safety across architectures
- Update commit message body to explicitly mention quirk application

Changes in v6:
- Reorder local variable definitions in i3c_hci_probe in descending
  order of line length

Changes in v5:
- Remove HCI_QUIRK_CLK_SUPPORT quirk and call
  devm_clk_bulk_get_all_enabled unconditionally, eliminating the
  need for a clock-specific quirk flag

Changes in v4:
- Remove the clock index variable MCHP_I3C_CLK_IDX as it is no
  longer needed after switching to bulk clock handling

Changes in v3:
- Make use of existing HCI_QUIRK_* code base instead of introducing
  separate MCHP_HCI_QUIRK_* flags
- Introduce HCI_QUIRK_CLK_SUPPORT to handle peripheral and system
  generic clk in bulk

Changes in v2:
- Platform specific changes integrated in the existing mipi-i3c-hci
  driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor
  specific quirk files rather than a standalone driver

 drivers/i3c/master/mipi-i3c-hci/core.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index b781dbed2165..4cdf2abd4219 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -8,6 +8,7 @@
  */
 
 #include <linux/bitfield.h>
+#include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/i3c/master.h>
@@ -969,6 +970,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
 static int i3c_hci_probe(struct platform_device *pdev)
 {
 	const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data;
+	struct clk_bulk_data *clks;
 	struct i3c_hci *hci;
 	int irq, ret;
 
@@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pdev)
 	if (!hci->quirks && platform_get_device_id(pdev))
 		hci->quirks = platform_get_device_id(pdev)->driver_data;
 
+	ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks);
+	if (ret < 0)
+		return dev_err_probe(&pdev->dev, ret,
+				     "Failed to get clocks\n");
+
 	ret = i3c_hci_init(hci);
 	if (ret)
 		return ret;
@@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pdev)
 
 static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
 	{ .compatible = "mipi-i3c-hci", },
+	{ .compatible = "microchip,sama7d65-i3c-hci",
+	  .data = (void *)(ulong)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING |
+				  HCI_QUIRK_RESP_BUF_THLD) },
 	{},
 };
 MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
-- 
2.25.1

Re: [PATCH v7 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Reusing AMD-specific hardcoded timing quirks for a Microchip SoC will result in incorrect I3C bus frequencies.
--

commit 8dab9b9edc49c0214800ec48372900ae0b5bbae4
Author: Manikandan Muralidharan <manikandan.m@microchip.com>

i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk

This commit adds support for the Microchip sama7d65 SoC I3C HCI master IP.
It introduces clock acquisition during probe and applies specific quirks
to the new compatible string.

> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index b781dbed21650..4cdf2abd42197 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
[ ... ]
> @@ -969,6 +970,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  static int i3c_hci_probe(struct platform_device *pdev)
>  {
>  	const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data;
> +	struct clk_bulk_data *clks;
>  	struct i3c_hci *hci;
>  	int irq, ret;
[ ... ]
> @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pdev)
>  	if (!hci->quirks && platform_get_device_id(pdev))
>  		hci->quirks = platform_get_device_id(pdev)->driver_data;
>  
> +	ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks);
> +	if (ret < 0)
> +		return dev_err_probe(&pdev->dev, ret,
> +				     "Failed to get clocks\n");
> +
>  	ret = i3c_hci_init(hci);
[ ... ]
> @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pdev)
>  
>  static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
>  	{ .compatible = "mipi-i3c-hci", },
> +	{ .compatible = "microchip,sama7d65-i3c-hci",
> +	  .data = (void *)(ulong)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING |
> +				  HCI_QUIRK_RESP_BUF_THLD) },

[Severity: High]
Will applying HCI_QUIRK_OD_PP_TIMING to this Microchip SoC result in
incorrect I3C bus frequencies?

This quirk typically invokes amd_set_od_pp_timing(), which writes hardcoded
timing divisors (0x00cf00cf for Open Drain and 0x00160016 for Push-Pull) to
the controller's vendor-specific registers. These fixed values were
calculated for a 9MHz I3C bus frequency assuming an AMD platform's specific
fixed input clock of roughly 400 MHz.

Since the Microchip SoC acquires its clocks dynamically via
devm_clk_bulk_get_all_enabled() as seen above, its input clock rate could
differ and vary based on the system's clock tree configuration.

Should these timing divisors be calculated dynamically against the actual
input clock rate obtained from the clock framework rather than blindly
reusing the fixed AMD divisors?

>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, i3c_hci_of_match);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260525092405.1514213-1-manikandan.m@microchip.com?part=3

Re: [PATCH v7 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk

[Frank Li]

On Mon, May 25, 2026 at 10:23:31AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] Reusing AMD-specific hardcoded timing quirks for a Microchip SoC will result in incorrect I3C bus frequencies.
> --
>
> commit 8dab9b9edc49c0214800ec48372900ae0b5bbae4
> Author: Manikandan Muralidharan <manikandan.m@microchip.com>
>
> i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk
>
> This commit adds support for the Microchip sama7d65 SoC I3C HCI master IP.
> It introduces clock acquisition during probe and applies specific quirks
> to the new compatible string.
>
> > diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> > index b781dbed21650..4cdf2abd42197 100644
> > --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> > +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> [ ... ]
> > @@ -969,6 +970,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
> >  static int i3c_hci_probe(struct platform_device *pdev)
> >  {
> >  	const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data;
> > +	struct clk_bulk_data *clks;
> >  	struct i3c_hci *hci;
> >  	int irq, ret;
> [ ... ]
> > @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pdev)
> >  	if (!hci->quirks && platform_get_device_id(pdev))
> >  		hci->quirks = platform_get_device_id(pdev)->driver_data;
> >
> > +	ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks);
> > +	if (ret < 0)
> > +		return dev_err_probe(&pdev->dev, ret,
> > +				     "Failed to get clocks\n");
> > +
> >  	ret = i3c_hci_init(hci);
> [ ... ]
> > @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pdev)
> >
> >  static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
> >  	{ .compatible = "mipi-i3c-hci", },
> > +	{ .compatible = "microchip,sama7d65-i3c-hci",
> > +	  .data = (void *)(ulong)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING |
> > +				  HCI_QUIRK_RESP_BUF_THLD) },
>
> [Severity: High]
> Will applying HCI_QUIRK_OD_PP_TIMING to this Microchip SoC result in
> incorrect I3C bus frequencies?
>
> This quirk typically invokes amd_set_od_pp_timing(), which writes hardcoded
> timing divisors (0x00cf00cf for Open Drain and 0x00160016 for Push-Pull) to
> the controller's vendor-specific registers. These fixed values were
> calculated for a 9MHz I3C bus frequency assuming an AMD platform's specific
> fixed input clock of roughly 400 MHz.

Look like make sense. Is it true?

Frank
>
> Since the Microchip SoC acquires its clocks dynamically via
> devm_clk_bulk_get_all_enabled() as seen above, its input clock rate could
> differ and vary based on the system's clock tree configuration.
>
> Should these timing divisors be calculated dynamically against the actual
> input clock rate obtained from the clock framework rather than blindly
> reusing the fixed AMD divisors?
>
> >  	{},
> >  };
> >  MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260525092405.1514213-1-manikandan.m@microchip.com?part=3

Re: [PATCH v7 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk

[Manikandan.M]

Hi Frank,

On 02/06/26 10:27 pm, Frank Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, May 25, 2026 at 10:23:31AM +0000, sashiko-bot@kernel.org wrote:
>> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>> - [High] Reusing AMD-specific hardcoded timing quirks for a Microchip SoC will result in incorrect I3C bus frequencies.
>> --
>>
>> commit 8dab9b9edc49c0214800ec48372900ae0b5bbae4
>> Author: Manikandan Muralidharan <manikandan.m@microchip.com>
>>
>> i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk
>>
>> This commit adds support for the Microchip sama7d65 SoC I3C HCI master IP.
>> It introduces clock acquisition during probe and applies specific quirks
>> to the new compatible string.
>>
>>> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
>>> index b781dbed21650..4cdf2abd42197 100644
>>> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
>>> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
>> [ ... ]
>>> @@ -969,6 +970,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
>>>   static int i3c_hci_probe(struct platform_device *pdev)
>>>   {
>>>      const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data;
>>> +   struct clk_bulk_data *clks;
>>>      struct i3c_hci *hci;
>>>      int irq, ret;
>> [ ... ]
>>> @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pdev)
>>>      if (!hci->quirks && platform_get_device_id(pdev))
>>>              hci->quirks = platform_get_device_id(pdev)->driver_data;
>>>
>>> +   ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks);
>>> +   if (ret < 0)
>>> +           return dev_err_probe(&pdev->dev, ret,
>>> +                                "Failed to get clocks\n");
>>> +
>>>      ret = i3c_hci_init(hci);
>> [ ... ]
>>> @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pdev)
>>>
>>>   static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
>>>      { .compatible = "mipi-i3c-hci", },
>>> +   { .compatible = "microchip,sama7d65-i3c-hci",
>>> +     .data = (void *)(ulong)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING |
>>> +                             HCI_QUIRK_RESP_BUF_THLD) },
>>
>> [Severity: High]
>> Will applying HCI_QUIRK_OD_PP_TIMING to this Microchip SoC result in
>> incorrect I3C bus frequencies?
>>
>> This quirk typically invokes amd_set_od_pp_timing(), which writes hardcoded
>> timing divisors (0x00cf00cf for Open Drain and 0x00160016 for Push-Pull) to
>> the controller's vendor-specific registers. These fixed values were
>> calculated for a 9MHz I3C bus frequency assuming an AMD platform's specific
>> fixed input clock of roughly 400 MHz.
> 
> Look like make sense. Is it true?
> 

During the I3C sensor slave integration, a similar OD and PP timing 
configuration was required, so the values had to be chosen with previous 
implementation as reference at the time. Going forward, a dynamic timing 
configuration approach would be the most reliable and robust solution.

I am currently working on integrating dynamic timing register updates 
based on the core clock and I3C/I2C bus clock frequencies with CLK 
quirks, and will share the patch series shortly.

Thank you for your cooperation.

> Frank
>>
>> Since the Microchip SoC acquires its clocks dynamically via
>> devm_clk_bulk_get_all_enabled() as seen above, its input clock rate could
>> differ and vary based on the system's clock tree configuration.
>>
>> Should these timing divisors be calculated dynamically against the actual
>> input clock rate obtained from the clock framework rather than blindly
>> reusing the fixed AMD divisors?
>>
>>>      {},
>>>   };
>>>   MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
>>
>> --
>> Sashiko AI review · https://sashiko.dev/#/patchset/20260525092405.1514213-1-manikandan.m@microchip.com?part=3

-- 
Thanks and Regards,
Manikandan M.

Re: [PATCH v7 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk

[Frank Li]

On Mon, May 25, 2026 at 02:54:03PM +0530, Manikandan Muralidharan wrote:
> Add support for microchip sama7d65 SoC I3C HCI master only IP
> with additional clock support to enable bulk clock acquisition
> and apply the required quirks.
>
> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
> Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
> Changes in v7:
> - Use (void *)(ulong) cast instead of direct (void *) cast in
>   of_device_id.data for pointer-size safety across architectures
> - Update commit message body to explicitly mention quirk application
>
> Changes in v6:
> - Reorder local variable definitions in i3c_hci_probe in descending
>   order of line length
>
> Changes in v5:
> - Remove HCI_QUIRK_CLK_SUPPORT quirk and call
>   devm_clk_bulk_get_all_enabled unconditionally, eliminating the
>   need for a clock-specific quirk flag
>
> Changes in v4:
> - Remove the clock index variable MCHP_I3C_CLK_IDX as it is no
>   longer needed after switching to bulk clock handling
>
> Changes in v3:
> - Make use of existing HCI_QUIRK_* code base instead of introducing
>   separate MCHP_HCI_QUIRK_* flags
> - Introduce HCI_QUIRK_CLK_SUPPORT to handle peripheral and system
>   generic clk in bulk
>
> Changes in v2:
> - Platform specific changes integrated in the existing mipi-i3c-hci
>   driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor
>   specific quirk files rather than a standalone driver
>
>  drivers/i3c/master/mipi-i3c-hci/core.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index b781dbed2165..4cdf2abd4219 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -8,6 +8,7 @@
>   */
>
>  #include <linux/bitfield.h>
> +#include <linux/clk.h>
>  #include <linux/device.h>
>  #include <linux/errno.h>
>  #include <linux/i3c/master.h>
> @@ -969,6 +970,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  static int i3c_hci_probe(struct platform_device *pdev)
>  {
>  	const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data;
> +	struct clk_bulk_data *clks;
>  	struct i3c_hci *hci;
>  	int irq, ret;
>
> @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pdev)
>  	if (!hci->quirks && platform_get_device_id(pdev))
>  		hci->quirks = platform_get_device_id(pdev)->driver_data;
>
> +	ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks);
> +	if (ret < 0)
> +		return dev_err_probe(&pdev->dev, ret,
> +				     "Failed to get clocks\n");
> +
>  	ret = i3c_hci_init(hci);
>  	if (ret)
>  		return ret;
> @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pdev)
>
>  static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
>  	{ .compatible = "mipi-i3c-hci", },
> +	{ .compatible = "microchip,sama7d65-i3c-hci",
> +	  .data = (void *)(ulong)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING |
> +				  HCI_QUIRK_RESP_BUF_THLD) },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
> --
> 2.25.1
>

[PATCH v7 4/5] ARM: dts: microchip: add I3C controller

[Manikandan Muralidharan]

From: Durai Manickam KR <durai.manickamkr@microchip.com>

Add I3C controller for sama7d65 SoC.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
---
Changes in v3:
- Remove clock-names property as the driver acquires and enables
  clocks in bulk using devm_clk_bulk_get_all_enabled

 arch/arm/boot/dts/microchip/sama7d65.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 67253bbc08df..ec200848c153 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -1055,5 +1055,13 @@ gic: interrupt-controller@e8c11000 {
 			#address-cells = <0>;
 			interrupt-controller;
 		};
+
+		i3c: i3c@e9000000 {
+			compatible = "microchip,sama7d65-i3c-hci";
+			reg = <0xe9000000 0x300>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.25.1

Re: [PATCH v7 4/5] ARM: dts: microchip: add I3C controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Missing '#address-cells' and '#size-cells' in I3C controller DT node
--

commit 6a4a77f4bd5c6126a185a06e30b920a5e43d4eb6
Author: Durai Manickam KR <durai.manickamkr@microchip.com>

ARM: dts: microchip: add I3C controller

This commit adds the I3C controller device tree node for the sama7d65 SoC.

> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -1055,5 +1055,13 @@ gic: interrupt-controller@e8c11000 {
[ ... ]
> +		i3c: i3c@e9000000 {
> +			compatible = "microchip,sama7d65-i3c-hci";
> +			reg = <0xe9000000 0x300>;
> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>;

[Severity: Low]
Are the #address-cells and #size-cells properties missing for this node?
The MIPI I3C HCI schema inherits from the core I3C schema, which typically
requires #address-cells to be 3 and #size-cells to be 0.

Without these properties, dtbs_check validation might fail, and the OF core
could have trouble parsing addresses for any child devices added when this
controller is enabled in a board file.

> +			status = "disabled";
> +		};
>  	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260525092405.1514213-1-manikandan.m@microchip.com?part=4

[PATCH v7 5/5] ARM: configs: at91: sama7: add sama7d65 i3c-hci

[Manikandan Muralidharan]

Enable the configs needed for I3C framework and microchip
sama7d65 i3c-hci driver.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
---
 arch/arm/configs/sama7_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig
index e52f671ccec4..6470c7d3fe8a 100644
--- a/arch/arm/configs/sama7_defconfig
+++ b/arch/arm/configs/sama7_defconfig
@@ -117,6 +117,8 @@ CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_AT91=y
+CONFIG_I3C=y
+CONFIG_MIPI_I3C_HCI=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_ATMEL_QUADSPI=y
-- 
2.25.1

Re: [PATCH v7 0/5] Add microchip sama7d65 SoC I3C support

[Claudiu Beznea]

On 5/25/26 12:24, Manikandan Muralidharan wrote:
> Durai Manickam KR (2):
>    ARM: dts: microchip: add I3C controller

Applied to at91-dt, thanks!

> 
> Manikandan Muralidharan (3):
>    ARM: configs: at91: sama7: add sama7d65 i3c-hci

Applied to at91-defconfig, thanks!

Re: (subset) [PATCH v7 0/5] Add microchip sama7d65 SoC I3C support

[Alexandre Belloni]

On Mon, 25 May 2026 14:54:00 +0530, Manikandan Muralidharan wrote:
> Add support for microchip sama7d65 SoC I3C master only IP which is
> based on mipi-i3c-hci from synopsys implementing version 1.0
> specification. The platform specific changes are integrated in the
> mipi-i3c-hci driver using existing quirks.
> 
> I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
> mixed bus mode (I2C and I3C target devices on same i3c bus).
> 
> [...]

Applied, thanks!

[1/5] dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible
      https://git.kernel.org/i3c/c/9092105b87af
[3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk
      https://git.kernel.org/i3c/c/efaa912ab0f1

Best regards,

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com