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From: Conor Dooley <conor@kernel.org>
To: Guodong Xu <docular.xu@gmail.com>
Cc: sashiko-reviews@lists.linux.dev, kvm@vger.kernel.org,
	devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 08/15] riscv: Add Zic64b to cpufeature and hwprobe
Date: Thu, 4 Jun 2026 17:28:58 +0100	[thread overview]
Message-ID: <20260604-activate-antidote-ebb9197b286f@spud> (raw)
In-Reply-To: <u52q565xhv5s7gz3wbh4heplhbm4pv732s5kqvf4deiw6ceb4t@n4bnpzu5kabs>

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On Thu, Jun 04, 2026 at 09:31:36PM -0400, Guodong Xu wrote:
> On 2026-06-04 10:17, Conor Dooley wrote:
> > On Thu, Jun 04, 2026 at 02:42:22PM +0800, Guodong Xu wrote:
> > > On Wed, Jun 3, 2026 at 7:28 AM <sashiko-bot@kernel.org> wrote:
> > > >
> > > > > @@ -154,6 +154,23 @@ static int riscv_ext_zicbop_validate(const struct riscv_isa_ext_data *data,
> > > > >       return 0;
> > > > >  }
> > > > >
> > > > > +static int riscv_ext_zic64b_validate(const struct riscv_isa_ext_data *data,
> > > > > +                                  const unsigned long *isa_bitmap)
> > > > > +{
> > > > > +     /*
> > > > > +      * Zic64b mandates 64-byte naturally aligned cache blocks; cross-check the
> > > > > +      * cbom/cbop/cboz block-size device-tree properties to avoid inconsistency.
> > > > > +      */
> > > > > +     if (riscv_cbom_block_size != 64 ||
> > > > > +         riscv_cbop_block_size != 64 ||
> > > > > +         riscv_cboz_block_size != 64) {
> > > >
> > > > [Severity: Medium]
> > > > Will this check erroneously disable Zic64b if a platform does not implement
> > > > all three CBO extensions?
> > > 
> > > Zic64b is mandatory in RVA22/RVA23, which also mandate Zicbom,
> > > Zicbop and Zicboz, so all three block sizes must be present on any Zic64b
> > > platform.
> > 
> > Where do you get that conclusion from? That's not how we treat any other
> > extension defined in the profiles spec. My understanding was that even
> > if things are defined in the profiles spec that they're fair game for
> > independent use.
> 
> Ok, I get your point. Agree, Zic64b/Zicbom/cbop/cboz can be implemented
> on each hart independently (at least spec doesn't say no). With this in
> mind, the validation of Zic64b should be like this:
> 
>     if ((riscv_cbom_block_size && riscv_cbom_block_size != 64) ||
>        (riscv_cbop_block_size && riscv_cbop_block_size != 64) ||
>        (riscv_cboz_block_size && riscv_cboz_block_size != 64))

Or you could check for the extension instead of the left-hand sides
here, but I think that becomes more complex because you need to start
returning EPROBE_DEFER sometimes etc.

>     return -EINVAL;
> 
> This will allow :
> 1. A Zic64b hart with 0, 1, 2, or 3 CBO extension and block_size 64
>    passes the validation.

I'm not too worried about the 0 case here, people shouldn't be using
zic64b if they don't have a corresponding extension after all.

> 2. A Zic64b hart with CBO extensions but block_size is not 64
>    fails the validation
> 
> Thanks for the catch.
> 
> I will fix that in v4.

btw, can you fix your system time? It's like 12 hours in the future and
that impacts the timestamps on emails you send.

Cheers,
Conor.

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  reply	other threads:[~2026-06-04 16:29 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-03 11:11 [PATCH v3 00/15] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-06-03 11:11 ` [PATCH v3 01/15] riscv: hwprobe.rst: Make indentation consistent Guodong Xu
2026-06-03 11:11 ` [PATCH v3 02/15] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP Guodong Xu
2026-06-03 11:11 ` [PATCH v3 03/15] riscv: Standardize extension capitalization Guodong Xu
2026-06-03 11:11 ` [PATCH v3 04/15] riscv: Add Zicclsm to cpufeature and hwprobe Guodong Xu
2026-06-03 11:12 ` [PATCH v3 05/15] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 06/15] riscv: Add B to hwcap " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 07/15] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-06-02 23:28   ` sashiko-bot
2026-06-04  5:23     ` Guodong Xu
2026-06-04  9:06       ` Conor Dooley
2026-06-03 11:12 ` [PATCH v3 08/15] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-06-02 23:28   ` sashiko-bot
2026-06-04  6:42     ` Guodong Xu
2026-06-04  9:17       ` Conor Dooley
2026-06-05  1:31         ` Guodong Xu
2026-06-04 16:28           ` Conor Dooley [this message]
2026-06-04 16:43           ` Qingwei Hu
2026-06-04 15:48   ` Andrew Jones
2026-06-03 11:12 ` [PATCH v3 09/15] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-06-03 11:12 ` [PATCH v3 10/15] riscv: dts: spacemit: k1: " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 11/15] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 12/15] riscv: Add a getter for user PMLEN support Guodong Xu
2026-06-03 11:12 ` [PATCH v3 13/15] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-06-02 23:37   ` sashiko-bot
2026-06-04  6:46     ` Guodong Xu
2026-06-04  9:06       ` Conor Dooley
2026-06-03 11:12 ` [PATCH v3 14/15] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-06-03 11:12 ` [PATCH v3 15/15] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-06-04 16:03 ` [PATCH v3 00/15] riscv: hwprobe: Expose RVA23U64 " Andrew Jones

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