Devicetree
 help / color / mirror / Atom feed
From: Conor Dooley <conor@kernel.org>
To: Guodong Xu <docular.xu@gmail.com>
Cc: sashiko-reviews@lists.linux.dev, kvm@vger.kernel.org,
	devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 08/15] riscv: Add Zic64b to cpufeature and hwprobe
Date: Thu, 4 Jun 2026 10:17:38 +0100	[thread overview]
Message-ID: <20260604-rice-protegee-3a0b8e4cb609@spud> (raw)
In-Reply-To: <CA+Ck9FbKRM0wjJMg1fQpdwmow8cf_zTfir7V6+T=CRxU+vomdg@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 2496 bytes --]

On Thu, Jun 04, 2026 at 02:42:22PM +0800, Guodong Xu wrote:
> On Wed, Jun 3, 2026 at 7:28 AM <sashiko-bot@kernel.org> wrote:
> >
> > > @@ -154,6 +154,23 @@ static int riscv_ext_zicbop_validate(const struct riscv_isa_ext_data *data,
> > >       return 0;
> > >  }
> > >
> > > +static int riscv_ext_zic64b_validate(const struct riscv_isa_ext_data *data,
> > > +                                  const unsigned long *isa_bitmap)
> > > +{
> > > +     /*
> > > +      * Zic64b mandates 64-byte naturally aligned cache blocks; cross-check the
> > > +      * cbom/cbop/cboz block-size device-tree properties to avoid inconsistency.
> > > +      */
> > > +     if (riscv_cbom_block_size != 64 ||
> > > +         riscv_cbop_block_size != 64 ||
> > > +         riscv_cboz_block_size != 64) {
> >
> > [Severity: Medium]
> > Will this check erroneously disable Zic64b if a platform does not implement
> > all three CBO extensions?
> 
> Zic64b is mandatory in RVA22/RVA23, which also mandate Zicbom,
> Zicbop and Zicboz, so all three block sizes must be present on any Zic64b
> platform.

Where do you get that conclusion from? That's not how we treat any other
extension defined in the profiles spec. My understanding was that even
if things are defined in the profiles spec that they're fair game for
independent use.

> 
> And architecturally, all the block sizes are one quantity: under Zic64b
> that value is 64, so the three must all read 64.
> 
> Anything else is a misconfigured DT, and the kernel should not trust
> the zic64b it claims.
> 
> BR,
> Guodong
> 
> >
> > If a hardware platform implements Zic64b but omits an optional extension
> > like Zicbop, the riscv,cbop-block-size property might be absent from the
> > device tree, leaving riscv_cbop_block_size initialized at 0.
> >
> > This unconditional check evaluates 0 != 64 as true, which would spuriously
> > trigger this error path and disable the valid Zic64b extension.
> >
> > Should this validation only enforce the 64-byte size if the corresponding
> > block size variable is non-zero, indicating the extension is actually present?
> >
> > > +             pr_err("Zic64b detected in ISA string, disabling as the cache block size is not 64 bytes\n");
> > > +             return -EINVAL;
> > > +     }
> > > +
> > > +     return 0;
> > > +}
> >
> > --
> > Sashiko AI review · https://sashiko.dev/#/patchset/20260603-rva23u64-hwprobe-v2-v3-0-5529a7b28384@gmail.com?part=8

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

  reply	other threads:[~2026-06-04  9:17 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-03 11:11 [PATCH v3 00/15] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-06-03 11:11 ` [PATCH v3 01/15] riscv: hwprobe.rst: Make indentation consistent Guodong Xu
2026-06-03 11:11 ` [PATCH v3 02/15] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP Guodong Xu
2026-06-03 11:11 ` [PATCH v3 03/15] riscv: Standardize extension capitalization Guodong Xu
2026-06-03 11:11 ` [PATCH v3 04/15] riscv: Add Zicclsm to cpufeature and hwprobe Guodong Xu
2026-06-03 11:12 ` [PATCH v3 05/15] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 06/15] riscv: Add B to hwcap " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 07/15] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-06-02 23:28   ` sashiko-bot
2026-06-04  5:23     ` Guodong Xu
2026-06-04  9:06       ` Conor Dooley
2026-06-03 11:12 ` [PATCH v3 08/15] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-06-02 23:28   ` sashiko-bot
2026-06-04  6:42     ` Guodong Xu
2026-06-04  9:17       ` Conor Dooley [this message]
2026-06-05  1:31         ` Guodong Xu
2026-06-04 16:28           ` Conor Dooley
2026-06-04 16:43           ` Qingwei Hu
2026-06-04 15:48   ` Andrew Jones
2026-06-03 11:12 ` [PATCH v3 09/15] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-06-03 11:12 ` [PATCH v3 10/15] riscv: dts: spacemit: k1: " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 11/15] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-06-03 11:12 ` [PATCH v3 12/15] riscv: Add a getter for user PMLEN support Guodong Xu
2026-06-03 11:12 ` [PATCH v3 13/15] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-06-02 23:37   ` sashiko-bot
2026-06-04  6:46     ` Guodong Xu
2026-06-04  9:06       ` Conor Dooley
2026-06-03 11:12 ` [PATCH v3 14/15] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-06-03 11:12 ` [PATCH v3 15/15] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-06-04 16:03 ` [PATCH v3 00/15] riscv: hwprobe: Expose RVA23U64 " Andrew Jones

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260604-rice-protegee-3a0b8e4cb609@spud \
    --to=conor@kernel.org \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=docular.xu@gmail.com \
    --cc=kvm@vger.kernel.org \
    --cc=robh@kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox