Re: [PATCH 08/18] arm64: dts: ti: k3-j721s2: Add overlay for fusion application daughter board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The commit message claims the overlay can be reused for J742S2, but the required device tree combination target is missing from the Makefile.
- [Low] The `csi2_phy0` endpoint definition is missing the `bus-type = <4>;` property, while the identical `csi2_phy1` endpoint explicitly defines it.
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commit 38600625d6a88602aa3dc77a7657b2be15b2c563
Author: Vaishnav Achath <vaishnav.a@ti.com>

arm64: dts: ti: k3-j721s2: Add overlay for fusion application daughter board

This patch adds an overlay for the Fusion application daughter board to
connect multiple FPDLink-III based sensors to TI EVMs. The commit message
notes that CSI2RX connectivity on J784S4 and J742S2 is the same as J721S2,
allowing the overlay to be reused.

Link: https://svtronics.com/product/fusion-application-daughter-board-evm577pfusion-v1-0/?srsltid=AfmBOooMsRAd5ibFOGJaKbjsC3j9-loTPK2wWqsqPq2Adj55g1nPluxX

> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 350a8b5ad275c..9dd25a21d738e 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
[ ... ]
> @@ -333,6 +336,8 @@ k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \
>  	k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
>  k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \
>  	k3-j784s4-j742s2-evm-usb0-type-a.dtbo
> +k3-j784s4-evm-fpdlink-fusion-dtbs := k3-j784s4-evm.dtb \
> +	k3-j721s2-evm-fusion.dtbo

[Severity: Medium]
The commit message mentions the overlay can be reused for J742S2, but should
a build target for k3-j742s2-evm-fpdlink-fusion.dtbs also be added here?

>  k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \
>  	k3-j784s4-evm-pcie0-pcie1-ep.dtbo
>  k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
[ ... ]
> @@ -400,11 +405,13 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
>  	k3-j721e-evm-pcie0-ep.dtb \
>  	k3-j721e-evm-pcie1-ep.dtb \
>  	k3-j721e-sk-csi2-dual-imx219.dtb \
> +	k3-j721s2-evm-fpdlink-fusion.dtb \
>  	k3-j721s2-evm-pcie1-ep.dtb \
>  	k3-j721s2-evm-usb0-type-a.dtb \
>  	k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \
>  	k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \
>  	k3-j742s2-evm-usb0-type-a.dtb \
> +	k3-j784s4-evm-fpdlink-fusion.dtb \

[Severity: Medium]
Does k3-j742s2-evm-fpdlink-fusion.dtb need to be appended to this list so
the J742S2 combination device tree gets built?

>  	k3-j784s4-evm-pcie0-pcie1-ep.dtb \
>  	k3-j784s4-evm-quad-port-eth-exp1.dtb \
>  	k3-j784s4-evm-usb0-type-a.dtb \
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso
> new file mode 100644
> index 0000000000000..f200cdaa1bab1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-fusion.dtso
[ ... ]
> +&cdns_csi2rx0 {
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		csi0_port0: port@0 {
> +			reg = <0>;
> +			status = "okay";
> +
> +			csi2_phy0: endpoint {
> +				remote-endpoint = <&ds90ub960_0_csi_out>;

[Severity: Low]
This isn't a bug, but should this endpoint explicitly define bus-type = <4>
to remain consistent with how csi2_phy1 configures it below?

> +				clock-lanes = <0>;
> +				data-lanes = <1 2 3 4>;
> +				link-frequencies = /bits/ 64 <800000000>;
> +
> +			};
> +		};
> +	};
> +};
> +
> +&cdns_csi2rx1 {
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		csi1_port0: port@0 {
> +			reg = <0>;
> +			status = "okay";
> +
> +			csi2_phy1: endpoint {
> +				remote-endpoint = <&ds90ub960_1_csi_out>;
> +				bus-type = <4>; /* CSI2 DPHY */
> +				clock-lanes = <0>;
> +				data-lanes = <1 2 3 4>;
> +				link-frequencies = /bits/ 64 <800000000>;
> +			};
> +		};
> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093123.1048575-1-y-abhilashchandra@ti.com?part=8