Re: [PATCH 09/18] arm64: dts: ti: k3-j721e-sk: Add overlay for fusion application daughter board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] Inconsistent definition of the `bus-type` property between CSI-2 endpoints.
- [Low] Minor DTS styling and whitespace inconsistencies in port definitions.
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commit 6e2c6c33cfd930bf555fb197269fc8e707df6261
Author: Vaishnav Achath <vaishnav.a@ti.com>

arm64: dts: ti: k3-j721e-sk: Add overlay for fusion application daughter board

This commit adds a device tree overlay for the Fusion application daughter
board, enabling FPDLink-III based sensors to connect to TI EVMs. It
configures two DS90UB960 deserializers and is compatible with J721E SK,
AM68-SK, and AM69-SK boards.

> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso
> new file mode 100644
> index 0000000000000..dd82ec3accfed
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-fpdlink-fusion.dtso
[ ... ]
> +		deserializer_0_ports: ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@0{
> +				reg= <0>;

[Severity: Low]
This isn't a bug, but there are a few minor formatting inconsistencies with
whitespace before braces and around equal signs (e.g., port@0{ instead of
port@0 {, and reg= <0>; instead of reg = <0>;). Should these be adjusted to
match standard device tree style?

> +				status = "disabled";
> +			};
[ ... ]
> +&cdns_csi2rx0 {
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		csi0_port0: port@0 {
> +			reg = <0>;
> +			status = "okay";
> +
> +			csi2_phy0: endpoint {
> +				remote-endpoint = <&ds90ub960_0_csi_out>;
> +				clock-lanes = <0>;
> +				data-lanes = <1 2 3 4>;
> +				link-frequencies = /bits/ 64 <800000000>;
> +
> +			};

[Severity: Low]
Is it intentional that the bus-type property is omitted here in csi2_phy0,
while it is explicitly defined in csi2_phy1 below? While the V4L2 framework
might infer V4L2_MBUS_CSI2_DPHY automatically from the clock and data lanes,
would it be better to keep the property definitions consistent between the
two endpoints?

> +		};
> +	};
> +};
> +
> +&cdns_csi2rx1 {
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		csi1_port0: port@0 {
> +			reg = <0>;
> +			status = "okay";
> +
> +			csi2_phy1: endpoint {
> +				remote-endpoint = <&ds90ub960_1_csi_out>;
> +				bus-type = <4>; /* CSI2 DPHY */
> +				clock-lanes = <0>;
> +				data-lanes = <1 2 3 4>;
> +				link-frequencies = /bits/ 64 <800000000>;
> +			};
> +		};
> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093123.1048575-1-y-abhilashchandra@ti.com?part=9