[PATCH 0/5] Add STM32 TAMP nvram support

[PATCH 0/5] Add STM32 TAMP nvram support

[Patrice Chotard]

Add STM32 TAMP nvram support for STM32MP1 and STM32MP2 SoC's family.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
Patrice Chotard (2):
      arm64: dts: st: add TAMP backup register in stm32mp211.dtsi
      arm64: dts: st: add TAMP backup register in stm32mp231.dtsi

Simeon Marijon (3):
      ARM: dts: stm32: add TAMP backup register in stm32mp131.dtsi
      ARM: dts: stm32: add TAMP backup register in stm32mp151.dtsi
      arm64: dts: st: add TAMP backup register in stm32mp251.dtsi

 arch/arm/boot/dts/st/stm32mp131.dtsi   | 34 ++++++++++++++
 arch/arm/boot/dts/st/stm32mp151.dtsi   | 82 ++++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/st/stm32mp211.dtsi | 30 +++++++++++++
 arch/arm64/boot/dts/st/stm32mp231.dtsi | 30 +++++++++++++
 arch/arm64/boot/dts/st/stm32mp251.dtsi | 30 +++++++++++++
 5 files changed, 206 insertions(+)
---
base-commit: 0788b44f68eac08924332af40a93d16ec331b515
change-id: 20260910-upstream_tamp_nvram_dts_part-df0ea0b68e51
prerequisite-change-id: 20260909-upstream_nvram_reworked-f84a4b37817c

Best regards,
--  
Patrice Chotard <patrice.chotard@foss.st.com>

[PATCH 1/5] ARM: dts: stm32: add TAMP backup register in stm32mp131.dtsi

[Patrice Chotard]

From: Simeon Marijon <simeon.marijon@foss.st.com>

TAMP backup registers allow information sharing between different
software components/execution levels.
They are described individually as nvmem cells.

Signed-off-by: Simeon Marijon <simeon.marijon@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp131.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index 83ae59b73dd0..b37c22b1379c 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -1918,5 +1918,39 @@ gpioi: gpio@5000a000 {
 				gpio-ranges = <&pinctrl 0 128 8>;
 			};
 		};
+
+		tamp: tamp@5c00a000 {
+			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x5c00a000 0x400>;
+			ranges;
+
+			nvram: nvram@5c00a100 {
+				compatible = "st,stm32mp15-tamp-nvram";
+				reg = <0x5c00a100 0x80>;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					saes_secret_key: tamp-bkp@0 {
+						/* see saes secret key feature */
+						reg = <0x0 0x20>;
+					};
+
+					boot_mode: tamp-bkp@78 {
+						/* see boot mode selection feature */
+						reg = <0x78 0x4>;
+					};
+
+					boot_counter: tamp-bkp@7c {
+						/* see boot counter feature */
+						reg = <0x7c 0x4>;
+					};
+				};
+			};
+		};
 	};
 };

-- 
2.43.0

[PATCH 2/5] ARM: dts: stm32: add TAMP backup register in stm32mp151.dtsi

[Patrice Chotard]

From: Simeon Marijon <simeon.marijon@foss.st.com>

TAMP backup registers allow information sharing between different
software components/execution levels.
They are described individually as nvmem cells.

Signed-off-by: Simeon Marijon <simeon.marijon@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp151.dtsi | 82 ++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
index 84f68e8563d8..0ad75e010839 100644
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@ -2060,7 +2060,89 @@ i2c6: i2c@5c009000 {
 
 		tamp: tamp@5c00a000 {
 			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
 			reg = <0x5c00a000 0x400>;
+			ranges;
+
+			nvram: nvram@5c00a100 {
+				compatible = "st,stm32mp15-tamp-nvram";
+				reg = <0x5c00a100 0x80>;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+					wakeup_sec: tamp-bkp@0 {
+						reg = <0x0 0x4>;
+					};
+
+					m4_security_perimeter_exti1: tamp-bkp@4 {
+						/* see cortex-m4 wake up feature */
+						reg = <0x4 0x4>;
+					};
+
+					m4_security_perimeter_exti2: tamp-bkp@8 {
+						/* see cortex-m4 wake up feature */
+						reg = <0x8 0x4>;
+					};
+
+					m4_security_perimeter_exti3: tamp-bkp@c {
+						/* see cortex-m4 wtake up feature */
+						reg = <0xc 0x4>;
+					};
+
+					magic_number: tamp-bkp@10 {
+						/* see ddr and cpu wake up management feature */
+						reg = <0x10 0x4>;
+					};
+
+					branch_address: tamp-bkp@14 {
+						/* see ddr and cpu wake up management feature */
+						reg = <0x14 0x4>;
+					};
+
+					fwu_info: tamp-bkp@28 {
+						/* see firmware update info feature */
+						reg = <0x28 0x4>;
+					};
+
+					copro_rsc_tbl_address: tamp-bkp@44 {
+						/* see cortex-m4 management feature */
+						reg = <0x44 0x4>;
+					};
+
+					cortex_m_state: tamp-bkp@48 {
+						/* see cortex-m4 management feature */
+						reg = <0x48 0x4>;
+					};
+
+					boot_mode: tamp-bkp@50 {
+						/* see boot mode selection feature */
+						reg = <0x50 0x4>;
+					};
+
+					boot_counter: tamp-bkp@54 {
+						/* see boot counter feature */
+						reg = <0x54 0x4>;
+					};
+
+					m4_wakeup_area_start: tamp-bkp@58 {
+						/* see cortex-m4 wake up feature */
+						reg = <0x58 0x4>;
+					};
+
+					m4_wakeup_area_length: tamp-bkp@5c {
+						/* see cortex-m4 wake up feature */
+						reg = <0x5c 0x4>;
+					};
+
+					m4_wakeup_area_hash: tamp-bkp@60 {
+						/* SHA-0x100 value see Cortex-M4 wake up feature */
+						reg = <0x60 0x20>;
+					};
+				};
+			};
 		};
 
 		/*

-- 
2.43.0

[PATCH 3/5] arm64: dts: st: add TAMP backup register in stm32mp211.dtsi

[Patrice Chotard]

TAMP backup registers allow information sharing between different
software components/execution levels.
They are described individually as nvmem cells.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm64/boot/dts/st/stm32mp211.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi
index 4bfd58b26b51..764a9a3d108e 100644
--- a/arch/arm64/boot/dts/st/stm32mp211.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi
@@ -133,6 +133,36 @@ syscfg: syscon@44230000 {
 			reg = <0x44230000 0x0 0x10000>;
 		};
 
+		tamp: tamp@46010000 {
+			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <2>;
+			reg = <0x46010000 0x0 0x400>;
+			ranges;
+
+			nvram: nvram@46010100 {
+				compatible = "st,stm32mp25-tamp-nvram";
+				reg = <0x46010100 0x0 0x200>;
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					boot_mode: tamp-bkp@180 {
+						reg = <0x180 0x4>;
+					};
+
+					rsc_tbl_addr: tamp-bkp@184 {
+						reg = <0x184 0x4>;
+					};
+
+					rsc_tbl_size: tamp-bkp@188 {
+						reg = <0x188 0x4>;
+					};
+				};
+			};
+		};
+
 		intc: interrupt-controller@4ac10000 {
 			compatible = "arm,gic-400";
 			reg = <0x4ac10000 0x0 0x1000>,

-- 
2.43.0

[PATCH 4/5] arm64: dts: st: add TAMP backup register in stm32mp231.dtsi

[Patrice Chotard]

TAMP backup registers allow information sharing between different
software components/execution levels.
They are described individually as nvmem cells.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm64/boot/dts/st/stm32mp231.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
index 9e1d240888ff..6d7c16e85d86 100644
--- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
@@ -1102,6 +1102,36 @@ rtc: rtc@46000000 {
 			status = "disabled";
 		};
 
+		tamp: tamp@46010000 {
+			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x46010000 0x400>;
+			ranges;
+
+			nvram: nvram@46010100 {
+				compatible = "st,stm32mp25-tamp-nvram";
+				reg = <0x46010100 0x200>;
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					boot_mode: tamp-bkp@180 {
+						reg = <0x180 0x4>;
+					};
+
+					rsc_tbl_addr: tamp-bkp@184 {
+						reg = <0x184 0x4>;
+					};
+
+					rsc_tbl_size: tamp-bkp@188 {
+						reg = <0x188 0x4>;
+					};
+				};
+			};
+		};
+
 		pinctrl_z: pinctrl@46200000 {
 			compatible = "st,stm32mp257-z-pinctrl";
 			ranges = <0 0x46200000 0x400>;

-- 
2.43.0

[PATCH 5/5] arm64: dts: st: add TAMP backup register in stm32mp251.dtsi

[Patrice Chotard]

From: Simeon Marijon <simeon.marijon@foss.st.com>

TAMP backup registers allow information sharing between different
software components/execution levels.
They are described individually as nvmem cells.

Signed-off-by: Simeon Marijon <simeon.marijon@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm64/boot/dts/st/stm32mp251.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 9c63fdb5a885..aa7ae8b6fd21 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -2118,6 +2118,36 @@ rtc: rtc@46000000 {
 			status = "disabled";
 		};
 
+		tamp: tamp@46010000 {
+			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x46010000 0x400>;
+			ranges;
+
+			nvram: nvram@46010100 {
+				compatible = "st,stm32mp25-tamp-nvram";
+				reg = <0x46010100 0x200>;
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					boot_mode: tamp-bkp@180 {
+						reg = <0x180 0x4>;
+					};
+
+					rsc_tbl_addr: tamp-bkp@184 {
+						reg = <0x184 0x4>;
+					};
+
+					rsc_tbl_size: tamp-bkp@188 {
+						reg = <0x188 0x4>;
+					};
+				};
+			};
+		};
+
 		pinctrl_z: pinctrl@46200000 {
 			#address-cells = <1>;
 			#size-cells = <1>;

-- 
2.43.0

Re: [PATCH 5/5] arm64: dts: st: add TAMP backup register in stm32mp251.dtsi

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] DT Schema Violation: additionalProperties not allowed in syscon node
- [Low] Undocumented DT Binding: st,stm32mp25-tamp-nvram
--

commit d9b7574bfcac6134021b52991b2d481d5704a393
Author: Simeon Marijon <simeon.marijon@foss.st.com>

arm64: dts: st: add TAMP backup register in stm32mp251.dtsi
    
TAMP backup registers allow information sharing between different
software components/execution levels. They are described individually
as nvmem cells.

> diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
> index 9c63fdb5a885a..aa7ae8b6fd21c 100644
> --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
> +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
> @@ -2118,6 +2118,36 @@ rtc: rtc@46000000 {
>  			status = "disabled";
>  		};
>  
> +		tamp: tamp@46010000 {
> +			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x46010000 0x400>;
> +			ranges;
> +
> +			nvram: nvram@46010100 {

[Severity: Low]
Does this configuration trigger warnings during dtbs_check?

The parent schema Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
(which binds to st,stm32-tamp) strictly enforces additionalProperties: false
without defining #address-cells, #size-cells, ranges, or any child nodes.

> +				compatible = "st,stm32mp25-tamp-nvram";

[Severity: Low]
Is this compatible string missing its corresponding YAML binding document?

All new DT hardware bindings must be documented to avoid schema validation
warnings during dtbs_check.

> +				reg = <0x46010100 0x200>;
> +				nvmem-layout {

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260910-upstream_tamp_nvram_dts_part-v1-0-e2bca58a65f4@foss.st.com?part=5

Re: [PATCH 2/5] ARM: dts: stm32: add TAMP backup register in stm32mp151.dtsi

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The compatible string "st,stm32mp15-tamp-nvram" is introduced without any corresponding DT binding documentation.
- [Low] The comment 'SHA-0x100' is a corrupted reference to 'SHA-256', resulting from an accidental search-and-replace of '256' to '0x100'.
--

commit 143934b850adb47535f66b1f12ec54c5c90f65e6
Author: Simeon Marijon <simeon.marijon@foss.st.com>

ARM: dts: stm32: add TAMP backup register in stm32mp151.dtsi

TAMP backup registers allow information sharing between different software
components/execution levels. They are described individually as nvmem cells.

> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
> index 84f68e8563d85..0ad75e0108394 100644
> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
> @@ -2060,7 +2060,89 @@ i2c6: i2c@5c009000 {
>  
>  		tamp: tamp@5c00a000 {
>  			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
>  			reg = <0x5c00a000 0x400>;
> +			ranges;
> +
> +			nvram: nvram@5c00a100 {
> +				compatible = "st,stm32mp15-tamp-nvram";

[Severity: Low]
Is there missing device tree binding documentation for this new compatible
string? dt_binding_check validation will fail because
"st,stm32mp15-tamp-nvram" is undocumented.

> +				reg = <0x5c00a100 0x80>;
> +
> +				nvmem-layout {
> +					compatible = "fixed-layout";
> +					#address-cells = <1>;
> +					#size-cells = <1>;

[ ... ]

> +					m4_wakeup_area_length: tamp-bkp@5c {
> +						/* see cortex-m4 wake up feature */
> +						reg = <0x5c 0x4>;
> +					};
> +
> +					m4_wakeup_area_hash: tamp-bkp@60 {
> +						/* SHA-0x100 value see Cortex-M4 wake up feature */

[Severity: Low]
Was there an accidental search-and-replace here? The comment says
"SHA-0x100", which seems to be a corrupted reference to "SHA-256", likely
resulting from a bulk replace of decimal 256 to hex 0x100.

> +						reg = <0x60 0x20>;
> +					};
> +				};
> +			};
>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260910-upstream_tamp_nvram_dts_part-v1-0-e2bca58a65f4@foss.st.com?part=2

Re: [PATCH 1/5] ARM: dts: stm32: add TAMP backup register in stm32mp131.dtsi

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Adding child nodes and properties to a syscon node that has `additionalProperties: false` in its schema causes immediate validation failure.
--

commit fd4960b03c2c4e269bdd41d3965ee803d12b57df
Author: Simeon Marijon <simeon.marijon@foss.st.com>

ARM: dts: stm32: add TAMP backup register in stm32mp131.dtsi

This commit adds TAMP backup registers as nvmem cells in the stm32mp131
device tree to allow information sharing between different software
components.

> diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
> index 83ae59b73dd09..b37c22b1379cc 100644
> --- a/arch/arm/boot/dts/st/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
> @@ -1918,5 +1918,39 @@ gpioi: gpio@5000a000 {

[ ... ]

> +
> +		tamp: tamp@5c00a000 {
> +			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x5c00a000 0x400>;
> +			ranges;
> +
> +			nvram: nvram@5c00a100 {

[Severity: Low]
Will this introduce a schema validation regression when running make
dtbs_check?

The matching schema in
Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml dictates
additionalProperties: false and does not define #address-cells, #size-cells,
ranges, or child nodes like nvram.

Does the schema need to be updated to support these new properties, or
should they be structured differently?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260910-upstream_tamp_nvram_dts_part-v1-0-e2bca58a65f4@foss.st.com?part=1

Re: [PATCH 1/5] ARM: dts: stm32: add TAMP backup register in stm32mp131.dtsi

[Patrice CHOTARD]

On 9/10/26 17:29, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] Adding child nodes and properties to a syscon node that has `additionalProperties: false` in its schema causes immediate validation failure.
> --
> 
> commit fd4960b03c2c4e269bdd41d3965ee803d12b57df
> Author: Simeon Marijon <simeon.marijon@foss.st.com>
> 
> ARM: dts: stm32: add TAMP backup register in stm32mp131.dtsi
> 
> This commit adds TAMP backup registers as nvmem cells in the stm32mp131
> device tree to allow information sharing between different software
> components.
> 
>> diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
>> index 83ae59b73dd09..b37c22b1379cc 100644
>> --- a/arch/arm/boot/dts/st/stm32mp131.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
>> @@ -1918,5 +1918,39 @@ gpioi: gpio@5000a000 {
> 
> [ ... ]
> 
>> +
>> +		tamp: tamp@5c00a000 {
>> +			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			reg = <0x5c00a000 0x400>;
>> +			ranges;
>> +
>> +			nvram: nvram@5c00a100 {
> 
> [Severity: Low]
> Will this introduce a schema validation regression when running make
> dtbs_check?
> 
> The matching schema in
> Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml dictates
> additionalProperties: false and does not define #address-cells, #size-cells,
> ranges, or child nodes like nvram.
> 
> Does the schema need to be updated to support these new properties, or
> should they be structured differently?
> 

The schema has been updated by this patch which is under review: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20260910-upstream_nvram_reworked-v1-2-521c16175cef@foss.st.com/

Re: [PATCH 2/5] ARM: dts: stm32: add TAMP backup register in stm32mp151.dtsi

[Patrice CHOTARD]

On 9/10/26 17:26, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [Low] The compatible string "st,stm32mp15-tamp-nvram" is introduced without any corresponding DT binding documentation.
> - [Low] The comment 'SHA-0x100' is a corrupted reference to 'SHA-256', resulting from an accidental search-and-replace of '256' to '0x100'.
> --
> 
> commit 143934b850adb47535f66b1f12ec54c5c90f65e6
> Author: Simeon Marijon <simeon.marijon@foss.st.com>
> 
> ARM: dts: stm32: add TAMP backup register in stm32mp151.dtsi
> 
> TAMP backup registers allow information sharing between different software
> components/execution levels. They are described individually as nvmem cells.
> 
>> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
>> index 84f68e8563d85..0ad75e0108394 100644
>> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
>> @@ -2060,7 +2060,89 @@ i2c6: i2c@5c009000 {
>>  
>>  		tamp: tamp@5c00a000 {
>>  			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>>  			reg = <0x5c00a000 0x400>;
>> +			ranges;
>> +
>> +			nvram: nvram@5c00a100 {
>> +				compatible = "st,stm32mp15-tamp-nvram";
> 
> [Severity: Low]
> Is there missing device tree binding documentation for this new compatible
> string? dt_binding_check validation will fail because
> "st,stm32mp15-tamp-nvram" is undocumented.

This new compatibale has been introduced by this patch under review: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20260910-upstream_nvram_reworked-v1-1-521c16175cef@foss.st.com/

> 
>> +				reg = <0x5c00a100 0x80>;
>> +
>> +				nvmem-layout {
>> +					compatible = "fixed-layout";
>> +					#address-cells = <1>;
>> +					#size-cells = <1>;
> 
> [ ... ]
> 
>> +					m4_wakeup_area_length: tamp-bkp@5c {
>> +						/* see cortex-m4 wake up feature */
>> +						reg = <0x5c 0x4>;
>> +					};
>> +
>> +					m4_wakeup_area_hash: tamp-bkp@60 {
>> +						/* SHA-0x100 value see Cortex-M4 wake up feature */
> 
> [Severity: Low]
> Was there an accidental search-and-replace here? The comment says
> "SHA-0x100", which seems to be a corrupted reference to "SHA-256", likely
> resulting from a bulk replace of decimal 256 to hex 0x100.
> 
>> +						reg = <0x60 0x20>;
>> +					};
>> +				};
>> +			};
>>  		};
>