* Re: [PATCH v3 2/2] drm/bridge: waveshare-dsi: support DSI LCD kits with LVDS panels
From: Luca Ceresoli @ 2026-04-16 14:45 UTC (permalink / raw)
To: Dmitry Baryshkov, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thierry Reding, Sam Ravnborg, Joseph Guo, Marek Vasut,
Andrzej Hajda, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec
Cc: dri-devel, devicetree, linux-kernel
In-Reply-To: <20260412-ws-lcd-v3-2-db22c2631828@oss.qualcomm.com>
On Sun Apr 12, 2026 at 7:32 PM CEST, Dmitry Baryshkov wrote:
> Several Waveshare DSI LCD kits use LVDS panels and the ICN6202 DSI2LVDS
> bridge. Support that setup by handling waveshare,dsi2lvds compatible.
> The only difference with the existing waveshare,dsi2dpi is the bridge's
> output type (LVDS vs DPI).
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v2] dt-bindings: iio: gyroscope: add mount-matrix for bmg160
From: Vishwas Rajashekar via B4 Relay @ 2026-04-16 15:03 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
H. Nikolaus Schaller
Cc: linux-iio, devicetree, linux-kernel, luca, Vishwas Rajashekar
From: Vishwas Rajashekar <vishwas.dev@vrajashkr.com>
Adds mount-matrix as an optional property to dt-bindings
for the bmg160 gyroscope as the driver reads this optional
property during probe.
Signed-off-by: Vishwas Rajashekar <vishwas.dev@vrajashkr.com>
---
The bmg160 driver reads an optional mount-matrix using
"iio_read_mount_matrix" in "bmg160_core_probe" and stores
this orientation data in "struct bmg160_data". As the "mount-matrix"
property is used by the driver, this change proposes to add it to
the corresponding dt-bindings.
---
Changes in v2:
- Addressed review feedback: add mount-matrix example for bmg160
- Link to v1: https://patch.msgid.link/20260415-bmg160-mount-matrix-dt-binding-v1-1-0e2c85964ee6@vrajashkr.com
To: Jonathan Cameron <jic23@kernel.org>
To: David Lechner <dlechner@baylibre.com>
To: Nuno Sá <nuno.sa@analog.com>
To: Andy Shevchenko <andy@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: "H. Nikolaus Schaller" <hns@goldelico.com>
Cc: linux-iio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml b/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml
index 3c6fe74af0b8..ec97778cca78 100644
--- a/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml
+++ b/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml
@@ -22,6 +22,9 @@ properties:
vdd-supply: true
vddio-supply: true
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix.
+
spi-max-frequency:
maximum: 10000000
@@ -52,6 +55,9 @@ examples:
reg = <0x69>;
interrupt-parent = <&gpio6>;
interrupts = <18 IRQ_TYPE_EDGE_RISING>;
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "1";
};
};
...
---
base-commit: 591cd656a1bf5ea94a222af5ef2ee76df029c1d2
change-id: 20260414-bmg160-mount-matrix-dt-binding-e76ddde94866
Best regards,
--
Vishwas Rajashekar <vishwas.dev@vrajashkr.com>
^ permalink raw reply related
* Re: [PATCH] dt-bindings: iio: dac: mcp47feb02: Fix binding issues
From: Conor Dooley @ 2026-04-16 15:15 UTC (permalink / raw)
To: Ariana Lazar
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Cameron,
Conor Dooley, linux-iio, devicetree, linux-kernel
In-Reply-To: <20260416-mcp47feb02-fix5-v1-1-9656c2fed6d2@microchip.com>
[-- Attachment #1: Type: text/plain, Size: 8563 bytes --]
Hey,
On Thu, Apr 16, 2026 at 04:33:36PM +0300, Ariana Lazar wrote:
> Change maxItems value from 8 to 1 for the channel number reg property.
> Change example reg value from 0 to 0x60.
> Fix a few typos in property descriptions.
> Sort the part numbers in the enum list lexicographically.
Hmm, this looks like 3 or 4 patches to me. The maxItems change probably
qualifies for a fixes tag, none of the rest do.
>
> Fixes: 4ba12d304175 ("dt-bindings: iio: dac: adding support for Microchip MCP47FEB02")
> Reported-by: Conor Dooley <conor@kernel.org>
> Closes: https://lore.kernel.org/all/20260403-speed-childless-1360de358229@spud/
I didn't report anything, I just commented on something that you had
already "reported" when you fixed it yourself.
> Reported-by: David Lechner <dlechner@baylibre.com>
> Closes: https://lore.kernel.org/all/dd0dbadb-604b-4f12-8674-268b7db096fd@baylibre.com/
David didn't report anything either, he just gave you review feedback on
the change you made to the example.
> Signed-off-by: Ariana Lazar <ariana.lazar@microchip.com>
> ---
> .../bindings/iio/dac/microchip,mcp47feb02.yaml | 57 +++++++++++-----------
> 1 file changed, 28 insertions(+), 29 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
> index d2466aa6bda2106a8b695347a0edf38462294d03..88a1495f2967a3d821ada7e7e9a7fbb466401040 100644
> --- a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
> +++ b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
> @@ -61,29 +61,29 @@ properties:
> compatible:
> enum:
> - microchip,mcp47feb01
> - - microchip,mcp47feb11
> - - microchip,mcp47feb21
> - microchip,mcp47feb02
> + - microchip,mcp47feb04
> + - microchip,mcp47feb08
> + - microchip,mcp47feb11
> - microchip,mcp47feb12
> + - microchip,mcp47feb14
> + - microchip,mcp47feb18
> + - microchip,mcp47feb21
> - microchip,mcp47feb22
> + - microchip,mcp47feb24
> + - microchip,mcp47feb28
> - microchip,mcp47fvb01
> - - microchip,mcp47fvb11
> - - microchip,mcp47fvb21
> - microchip,mcp47fvb02
> - - microchip,mcp47fvb12
> - - microchip,mcp47fvb22
> - microchip,mcp47fvb04
> - - microchip,mcp47fvb14
> - - microchip,mcp47fvb24
> - microchip,mcp47fvb08
> + - microchip,mcp47fvb11
> + - microchip,mcp47fvb12
> + - microchip,mcp47fvb14
> - microchip,mcp47fvb18
> + - microchip,mcp47fvb21
> + - microchip,mcp47fvb22
> + - microchip,mcp47fvb24
> - microchip,mcp47fvb28
> - - microchip,mcp47feb04
> - - microchip,mcp47feb14
> - - microchip,mcp47feb24
> - - microchip,mcp47feb08
> - - microchip,mcp47feb18
> - - microchip,mcp47feb28
>
> reg:
> maxItems: 1
> @@ -111,13 +111,13 @@ properties:
> - for single-channel device: Vout0;
> - for dual-channel device: Vout0, Vout1;
> - for quad-channel device: Vout0, Vout2;
> - - for octal-channel device: Vout0, Vout2, Vout6, Vout8;
> + - for octal-channel device: Vout0, Vout2, Vout4, Vout6;
>
> vref1-supply:
> description: |
> Vref1 pin may be used as a voltage reference when this supply is specified.
> The internal reference will be taken into account for voltage reference
> - beside VDD if this supply does not exist.
> + besides VDD if this supply does not exist.
ngl, I don't think this is a typo, the sentence doesn't make sense
either before or after the change. Should this be something like "The
internal reference and VDD will be used as the voltage reference if this
supply does not exist?
>
> This supply will be voltage reference for the following outputs:
> - for quad-channel device: Vout1, Vout3;
> @@ -141,7 +141,7 @@ properties:
> description:
> Enable buffering of the external Vref/Vref0 pin in cases where the
> external reference voltage does not have sufficient current capability in
> - order not to drop it’s voltage when connected to the internal resistor
> + order not to drop its voltage when connected to the internal resistor
> ladder circuit.
>
> microchip,vref1-buffered:
> @@ -149,7 +149,7 @@ properties:
> description:
> Enable buffering of the external Vref1 pin in cases where the external
> reference voltage does not have sufficient current capability in order not
> - to drop it’s voltage when connected to the internal resistor ladder
> + to drop its voltage when connected to the internal resistor ladder
> circuit.
>
> patternProperties:
> @@ -161,8 +161,7 @@ patternProperties:
> properties:
> reg:
> description: The channel number.
> - minItems: 1
> - maxItems: 8
> + maxItems: 1
>
> label:
> description: Unique name to identify which channel this is.
> @@ -227,12 +226,12 @@ allOf:
> compatible:
> contains:
> enum:
> - - microchip,mcp47fvb04
> - - microchip,mcp47fvb14
> - - microchip,mcp47fvb24
> - microchip,mcp47feb04
> - microchip,mcp47feb14
> - microchip,mcp47feb24
> + - microchip,mcp47fvb04
> + - microchip,mcp47fvb14
> + - microchip,mcp47fvb24
> then:
> patternProperties:
> "^channel@[0-3]$":
> @@ -245,12 +244,12 @@ allOf:
> compatible:
> contains:
> enum:
> - - microchip,mcp47fvb08
> - - microchip,mcp47fvb18
> - - microchip,mcp47fvb28
> - microchip,mcp47feb08
> - microchip,mcp47feb18
> - microchip,mcp47feb28
> + - microchip,mcp47fvb08
> + - microchip,mcp47fvb18
> + - microchip,mcp47fvb28
> then:
> patternProperties:
> "^channel@[0-7]$":
> @@ -280,9 +279,9 @@ examples:
>
> #address-cells = <1>;
> #size-cells = <0>;
> - dac@0 {
> + dac@60 {
> compatible = "microchip,mcp47feb02";
> - reg = <0>;
> + reg = <0x60>;
> vdd-supply = <&vdac_vdd>;
> vref-supply = <&vref_reg>;
>
> @@ -297,6 +296,6 @@ examples:
> reg = <0x1>;
> label = "Adjustable_voltage_ch1";
> };
> - };
> + };
> };
This whitespace change looks odd. You've aligned the opening and closing
braces, but the indent is not consistent as there's mixed 4- and 2-space
indentation used in this example. I think you need to do:
diff --git a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
index d2466aa6bda21..a36874c4ae276 100644
--- a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
@@ -278,25 +278,25 @@ examples:
- |
i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dac@0 {
+ compatible = "microchip,mcp47feb02";
+ reg = <0>;
+ vdd-supply = <&vdac_vdd>;
+ vref-supply = <&vref_reg>;
+
#address-cells = <1>;
#size-cells = <0>;
- dac@0 {
- compatible = "microchip,mcp47feb02";
+ channel@0 {
reg = <0>;
- vdd-supply = <&vdac_vdd>;
- vref-supply = <&vref_reg>;
+ label = "Adjustable_voltage_ch0";
+ };
- #address-cells = <1>;
- #size-cells = <0>;
- channel@0 {
- reg = <0>;
- label = "Adjustable_voltage_ch0";
- };
-
- channel@1 {
- reg = <0x1>;
- label = "Adjustable_voltage_ch1";
- };
+ channel@1 {
+ reg = <0x1>;
+ label = "Adjustable_voltage_ch1";
+ };
};
};
...
Cheers,
Conor.
> ...
>
> ---
> base-commit: d2a4ec19d2a2e54c23b5180e939994d3da4a6b91
> change-id: 20260416-mcp47feb02-fix5-26994c5b428c
>
> Best regards,
> --
> Ariana Lazar <ariana.lazar@microchip.com>
>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply related
* Re: [PATCH 02/10] dt-bindings: mfd: syscon: add qcom,msm8960-sps-sic
From: Antony Kurniawan Soemardi @ 2026-04-16 14:18 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Lee Jones, Konrad Dybcio,
linux-arm-msm, linux-clk, devicetree, linux-kernel, phone-devel,
Rudraksha Gupta
In-Reply-To: <bac33524-1caa-4bff-be36-df909917cf3b@kernel.org>
On 4/15/2026 1:51 PM, Krzysztof Kozlowski wrote:
> On 14/04/2026 20:34, Antony Kurniawan Soemardi wrote:
>> On 4/14/2026 2:19 PM, Krzysztof Kozlowski wrote:
>>> This was also sent. Where is the changelog and versioning? What changed
>>> here?
>> Sorry, the cover letter should have referenced the earlier dt-bindings
>> series [1] and explained about it.
>>
>> In this patch series, I combined the original 2 patches into a larger 10
>> patch series to make it more complete. Especially since earlier feedback
>> noted that the bindings were not used by any in-tree consumers. Since
>> the scope changed significantly from the original, I resent it as a new
>> series rather than a v2.
>>
>> Would you prefer splitting this series into separate series like before,
>> for example:
>
> No, you need to keep versioning, changelogs and make clear how previous
> comments got resolved.
I see, thanks for the clarification.
To confirm my understanding, since this series already went out without
proper versioning, the next resend should be labeled v3, with a
changelog covering both what changed from the original dt-bindings
series (v1) and from this series (v2).
Is that correct?
--
Thanks,
Antony K. S.
^ permalink raw reply
* Re: [PATCH RFC 06/10] arm64: dts: qcom: msm8939-asus-z00t: add Venus
From: Konrad Dybcio @ 2026-04-16 15:17 UTC (permalink / raw)
To: Erikas Bitovtas, Bryan O'Donoghue, Vikash Garodia,
Dikshita Agarwal, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, André Apitzsch,
Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <20260416-msm8939-venus-rfc-v1-6-a09fcf2c23df@gmail.com>
On 4/16/26 3:43 PM, Erikas Bitovtas wrote:
> Enable Venus video encoder/decoder for Asus ZenFone 2 Laser/Selfie.
>
> Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
> index 90e966242720..231a3e9c1929 100644
> --- a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
> +++ b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
> @@ -267,6 +267,14 @@ &usb_hs_phy {
> extcon = <&usb_id>;
> };
>
> +&venus {
> + status = "okay";
You need a firmware path here
Konrad
^ permalink raw reply
* Re: [PATCH RFC 05/10] arm64: dts: qcom: msm8939-longcheer-l9100: Enable venus node
From: Konrad Dybcio @ 2026-04-16 15:17 UTC (permalink / raw)
To: Erikas Bitovtas, Bryan O'Donoghue, Vikash Garodia,
Dikshita Agarwal, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, André Apitzsch,
Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <20260416-msm8939-venus-rfc-v1-5-a09fcf2c23df@gmail.com>
On 4/16/26 3:43 PM, Erikas Bitovtas wrote:
> From: André Apitzsch <git@apitzsch.eu>
>
> Enable the venus node so that the video encoder/decoder will start
> working.
>
> Signed-off-by: André Apitzsch <git@apitzsch.eu>
> ---
> arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts
> index 13422a19c26a..48514c3df718 100644
> --- a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts
> +++ b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts
> @@ -314,6 +314,14 @@ &usb_hs_phy {
> extcon = <&usb_id>;
> };
>
> +&venus {
> + status = "okay";
Likewise
Konrad
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: socfpga: Add the Agilex7 series SoC's
From: Dinh Nguyen @ 2026-04-16 15:20 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: robh, krzk+dt, conor+dt, devicetree
In-Reply-To: <321be4a9-2633-403b-ac44-4ec9102f7d14@kernel.org>
On 4/14/26 07:55, Krzysztof Kozlowski wrote:
> On 14/04/2026 14:53, Dinh Nguyen wrote:
>>
>>
>> On 4/14/26 02:17, Krzysztof Kozlowski wrote:
>>> On Mon, Apr 13, 2026 at 09:45:52AM -0500, Dinh Nguyen wrote:
>>>> The Agilex7 is a series of devices from Altera that are derived from
>>>> the Agilex family.
>>>>
>>>> The Agilex7F device supports PCIE 4.0 and DDR4. The Agilex7I device supports
>>>> PCIE 5.0 and DDR4, while the Agilex7M device supports DDR4, DDR5, LPDDR5
>>>> and PCIE 5.0.
>>>>
>>>> All other peripherals from these devices are the same as the Agilex
>>>> device.
>>>>
>>>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>>>> ---
>>>> Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++
>>>> 1 file changed, 10 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
>>>> index 206686f3eebc..5ee09f8d4698 100644
>>>> --- a/Documentation/devicetree/bindings/arm/altera.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/altera.yaml
>>>> @@ -115,6 +115,16 @@ properties:
>>>> - intel,socfpga-agilex5-socdk-nand
>>>> - const: intel,socfpga-agilex5
>>>>
>>>> + - description: Agilex7 series F, I and M boards
>>>> + items:
>>>> + - enum:
>>>> + - intel,socfpga-agilex7m-socdk
>>>> + - enum:
>>>> + - intel,socfpga-agilex7f
>>>> + - intel,socfpga-agilex7i
>>>> + - intel,socfpga-agilex7m
>>>> + - const: intel,socfpga-agilex
>>>
>>> And separate question - why previous soc "agilex" is used as fallback?
>>> Even more confusing.
>>>
>>
>> You're right. Sorry for the confusion. The Agilex7M, I, F devices are
>> basically "agilex" devices with some few additions (PCIE, DDR5). Maybe I
>> should place the Agilex7M/I/F devices into the "agilex" boards area?
>
> Compatibles should be specific and not based on families, thus what is
> "intel,socfpga-agilex"? SoC, right?
>
> Then "intel,socfpgaa-agilex7f" is a new SoC, no?
>
The Agilex7 is re-branded name for the original Agilex soc,
"intel, socfga-agilex". From a software perspective, they are the same
device. I looked over the commits to see how I could handle a
rebranding, but couldn't come up with a conclusion.
I could create a new SoC like you've suggested:
+ - description: Agilex7m boards
+ items:
+ - enum:
+ - altr,socfpga-agilex7m-socdk
+ - const: altr,socfpga-agilex7m
+ - const: altr,socfpga-agilex7
Or I can use the original "intel,socfpga-agilex"?
+ - description: Agilex7m boards
+ items:
+ - enum:
+ - altr,socfpga-agilex7m-socdk
+ - const: altr,socfpga-agilex7m
+ - const: altr,socfpga-agilex
If I create a new "altr,socfpga-agilex7" binding, then I would have to
add the new binding to a few drivers. But if I use the original
"intel,socfpga-agilex", then no drivers will need to be updated.
Thanks,
Dinh
^ permalink raw reply
* Re: [PATCH RFC 07/10] clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled
From: Konrad Dybcio @ 2026-04-16 15:21 UTC (permalink / raw)
To: Erikas Bitovtas, Bryan O'Donoghue, Vikash Garodia,
Dikshita Agarwal, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, André Apitzsch,
Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <20260416-msm8939-venus-rfc-v1-7-a09fcf2c23df@gmail.com>
On 4/16/26 3:43 PM, Erikas Bitovtas wrote:
> Since in downstream kernel VENUS_CORE0_GDSC and VENUS_CORE1_GDSC have a
> device tree property "qcom,supports-hw-trigger", add a HW_CTRL flag
> to these GDSCs to indicate that they are hardware controlled.
>
> Because they can be switched off at any moment, also skip voting for
> it so it can be enabled later.
The second paragraph bears no connection with what the effect of
the changes you made is, whatsoever
Konrad
^ permalink raw reply
* [PATCH] ASoC: dt-bindings: cdns: Convert xtfpga I2S to dt-schema
From: Chaitanya Sabnis @ 2026-04-16 15:23 UTC (permalink / raw)
To: Max Filippov, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, devicetree, linux-kernel, Chaitanya Sabnis
Convert the Cadence XTensa FPGA I2S controller plain-text binding
documentation to standard dt-schema (YAML).
The hardware requires exactly one memory region, one interrupt line,
and one phandle to the master clock. Verified these constraints against
the driver source in sound/soc/xtensa/xtfpga-i2s.c.
Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
---
.../bindings/sound/cdns,xtfpga-i2s.txt | 18 -------
.../bindings/sound/cdns,xtfpga-i2s.yaml | 48 +++++++++++++++++++
2 files changed, 48 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
create mode 100644 Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
deleted file mode 100644
index 860fc0da39c0..000000000000
--- a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Bindings for I2S controller built into xtfpga Xtensa bitstreams.
-
-Required properties:
-- compatible: shall be "cdns,xtfpga-i2s".
-- reg: memory region (address and length) with device registers.
-- interrupts: interrupt for the device.
-- clocks: phandle to the clk used as master clock. I2S bus clock
- is derived from it.
-
-Examples:
-
- i2s0: xtfpga-i2s@d080000 {
- #sound-dai-cells = <0>;
- compatible = "cdns,xtfpga-i2s";
- reg = <0x0d080000 0x40>;
- interrupts = <2 1>;
- clocks = <&cdce706 4>;
- };
diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
new file mode 100644
index 000000000000..9a4a9db3c159
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/cdns,xtfpga-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence XTensa FPGA I2S Controller
+
+maintainers:
+ - Max Filippov <jcmvbkbc@gmail.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: cdns,xtfpga-i2s
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: phandle to the clk used as master clock. I2S bus clock is derived from it.
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2s@d080000 {
+ compatible = "cdns,xtfpga-i2s";
+ reg = <0x0d080000 0x40>;
+ interrupts = <2 1>;
+ clocks = <&cdce706 4>;
+ #sound-dai-cells = <0>;
+ };
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v5 4/4] MAINTAINERS: Add entry on Allwinner sun8i/H616 PWM driver
From: Uwe Kleine-König @ 2026-04-16 15:28 UTC (permalink / raw)
To: Krzysztof Kozlowski, Richard Genoud
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Philipp Zabel, Paul Kocialkowski,
Thomas Petazzoni, John Stultz, Joao Schim, bigunclemax, linux-pwm,
devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
In-Reply-To: <e9904440-b08d-4f9d-8d66-121633289695@kernel.org>
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Hello,
On Thu, Apr 16, 2026 at 03:23:49PM +0200, Krzysztof Kozlowski wrote:
> On 16/04/2026 15:14, Richard Genoud wrote:
> > Add myself as maintainer of Allwinner SUN8I PWM driver.
> >
> > Tested-by: John Stultz <jstultz@google.com>
>
> Please drop or help me understand how one can test maintainers change?
> Build process tools are not testing.
For me that is fine. This is the only way we have to record that John
tested the series. Also if I applied the original series I would have
let b4 add it to all patches in reply to a "tested-by" send in reply to
the cover letter.
My feedback here would be more: Don't send a new revision for such
comments within 30 min, also not for
> And you have commit msg trailing junk.
. Maintainers differ, but if this is the only concern and the series is
fine otherwise, I'd just fix that when applying. (But I think the "don't
send a new iteration on the same day" is more universal, also for more
fundamental feedback.) There is no need to bother all subscribers of 5
mailing lists with a new thread in such quick sequence.
Best regards
Uwe
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^ permalink raw reply
* Re: Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional
From: Conor Dooley @ 2026-04-16 15:29 UTC (permalink / raw)
To: Xuyang Dong
Cc: Krzysztof Kozlowski, ukleinek, robh, krzk+dt, conor+dt, ben-linux,
ben.dooks, p.zabel, linux-pwm, devicetree, linux-kernel, ningyu,
linmin, xuxiang, wangguosheng, pinkesh.vaghela
In-Reply-To: <281f7aa3.5575.19d95a879f8.Coremail.dongxuyang@eswincomputing.com>
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On Thu, Apr 16, 2026 at 05:38:59PM +0800, Xuyang Dong wrote:
> > > >
> > > > The DesignWare PWM includes separate reset signals dedicated to each clock
> > > > domain:
> > > > The presetn signal resets logic in pclk domain.
> > > > The timer_N_resetn signal resets logic in the timer_N_clk domain.
> > > > The resets are active-low.
> > > >
> > > > Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> > >
> > > This commit implies that your hardware differs from existing devices,
> > > I think you should add a device-specific compatible.
> > >
>
> Hi Conor and Krzysztof,
>
> The DesignWare PWM Databook for 2.13a says: "The DW_apb_timers includes
> separate reset signals dedicated to each clock domain". They are:
> The presetn signal resets logic in pclk domain (i.e., the bus clock in DT).
> The timer_N_resetn signal resets logic in the timer_N_clk domain (i.e.,
> the timer clock in DT).
>
> These reset signals are optional; it is up to the designer's
> implementation.
Right, and it's that "designer's implementation" that warrants a
device-specific compatible.
>
> According to [1], the applied YAML is also based on 2.13a, so our
> hardware is the same as the existing devices. It's just that these two
> reset signals were missing from the original YAML binding.
>
> [1] https://lore.kernel.org/linux-pwm/8bb5103d-803e-90d2-fd93-132bb2aac2d6@sifive.com/
>
> > > > ---
> > > > .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++
> > > > 1 file changed, 3 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> > > > index 7523a89a1773..a8bbad0360f8 100644
> > > > --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> > > > +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> > > > @@ -43,6 +43,9 @@ properties:
> > > > - const: bus
> > > > - const: timer
> > > >
> > > > + resets:
> > > > + maxItems: 2
> >
> > And this should really be listed with description, because order is
> > fixed.
> >
>
> The description of resets will be listed in next version.
>
> Best regards,
> Xuyang Dong
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^ permalink raw reply
* Re: [PATCH v2] dt-bindings: iio: gyroscope: add mount-matrix for bmg160
From: Conor Dooley @ 2026-04-16 15:42 UTC (permalink / raw)
To: vishwas.dev
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
H. Nikolaus Schaller, linux-iio, devicetree, linux-kernel, luca
In-Reply-To: <20260416-bmg160-mount-matrix-dt-binding-v2-1-e66cf5cff8e8@vrajashkr.com>
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On Thu, Apr 16, 2026 at 08:33:21PM +0530, Vishwas Rajashekar via B4 Relay wrote:
> From: Vishwas Rajashekar <vishwas.dev@vrajashkr.com>
>
> Adds mount-matrix as an optional property to dt-bindings
> for the bmg160 gyroscope as the driver reads this optional
> property during probe.
Ultimately, what the driver does is not relevant here. All that matters
is that the property is relevant to the hardware. Please come up with a
commit message that avoids mentioning linux drivers and instead explains
why it is relevant to the hardware.
pw-bot: changes-requested
Cheers,
Conor.
>
> Signed-off-by: Vishwas Rajashekar <vishwas.dev@vrajashkr.com>
> ---
> The bmg160 driver reads an optional mount-matrix using
> "iio_read_mount_matrix" in "bmg160_core_probe" and stores
> this orientation data in "struct bmg160_data". As the "mount-matrix"
> property is used by the driver, this change proposes to add it to
> the corresponding dt-bindings.
> ---
> Changes in v2:
> - Addressed review feedback: add mount-matrix example for bmg160
> - Link to v1: https://patch.msgid.link/20260415-bmg160-mount-matrix-dt-binding-v1-1-0e2c85964ee6@vrajashkr.com
>
> To: Jonathan Cameron <jic23@kernel.org>
> To: David Lechner <dlechner@baylibre.com>
> To: Nuno Sá <nuno.sa@analog.com>
> To: Andy Shevchenko <andy@kernel.org>
> To: Rob Herring <robh@kernel.org>
> To: Krzysztof Kozlowski <krzk+dt@kernel.org>
> To: Conor Dooley <conor+dt@kernel.org>
> To: "H. Nikolaus Schaller" <hns@goldelico.com>
> Cc: linux-iio@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
> Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml b/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml
> index 3c6fe74af0b8..ec97778cca78 100644
> --- a/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml
> +++ b/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml
> @@ -22,6 +22,9 @@ properties:
> vdd-supply: true
> vddio-supply: true
>
> + mount-matrix:
> + description: an optional 3x3 mounting rotation matrix.
> +
> spi-max-frequency:
> maximum: 10000000
>
> @@ -52,6 +55,9 @@ examples:
> reg = <0x69>;
> interrupt-parent = <&gpio6>;
> interrupts = <18 IRQ_TYPE_EDGE_RISING>;
> + mount-matrix = "0", "1", "0",
> + "1", "0", "0",
> + "0", "0", "1";
> };
> };
> ...
>
> ---
> base-commit: 591cd656a1bf5ea94a222af5ef2ee76df029c1d2
> change-id: 20260414-bmg160-mount-matrix-dt-binding-e76ddde94866
>
> Best regards,
> --
> Vishwas Rajashekar <vishwas.dev@vrajashkr.com>
>
>
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^ permalink raw reply
* Re: [PATCH v7 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings
From: Conor Dooley @ 2026-04-16 15:43 UTC (permalink / raw)
To: iansdannapel
Cc: linux-fpga, devicetree, linux-kernel, mdf, yilun.xu, trix, robh,
krzk+dt, conor+dt, neil.armstrong, heiko, marex,
prabhakar.mahadev-lad.rj, dev
In-Reply-To: <20260416144237.373852-3-iansdannapel@gmail.com>
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On Thu, Apr 16, 2026 at 04:42:35PM +0200, iansdannapel@gmail.com wrote:
> From: Ian Dannapel <iansdannapel@gmail.com>
>
> Add device tree bindings documentation for configuring Efinix FPGA
> using serial SPI passive programming mode.
>
> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: hwmon: pmbus: add max20830
From: Conor Dooley @ 2026-04-16 15:51 UTC (permalink / raw)
To: Alexis Czezar Torreno
Cc: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Corbet, Shuah Khan, linux-hwmon, devicetree,
linux-kernel, linux-doc
In-Reply-To: <20260416-dev_max20830-v2-1-2c7d676dc0bd@analog.com>
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On Thu, Apr 16, 2026 at 03:59:10PM +0800, Alexis Czezar Torreno wrote:
> Add device tree documentation for MAX20830 step-down DC-DC switching
> regulator with PMBus interface.
>
> Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
> ---
> .../bindings/hwmon/pmbus/adi,max20830.yaml | 61 ++++++++++++++++++++++
> MAINTAINERS | 7 +++
> 2 files changed, 68 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..8b3ec1ffa0c9460de2122f6606ce3dcbcdfbbcc7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,max20830.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices MAX20830 Step-Down Switching Regulator with PMBus
> +
> +maintainers:
> + - Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
> +
> +description: |
> + The MAX20830 is a fully integrated step-down DC-DC switching regulator with
> + PMBus interface. It provides 2.7V to 16V input, 0.4V to 5.8V adjustable
> + output, and up to 30A output current. It allows monitoring of input/output
> + voltage, output current and temperature through the PMBus serial interface.
> + Datasheet:
> + https://www.analog.com/en/products/max20830.html
> +
> +allOf:
> + - $ref: /schemas/regulator/regulator.yaml#
> +
> +properties:
> + compatible:
> + const: adi,max20830
> +
> + reg:
> + maxItems: 1
On the previous version, you got an LLM comment about not having the
interrupts property amongst other things.
I think the other things got implemented, but I didn't see any reply to
the bot about that?
I think the answer is that it shouldn't because the pin it referenced
doesn't exist, but when looking at the schematic I have to wonder if
there should be an interrupts property for dealing with "pgood"?
Cheers,
Conor.
> +
> + vddh-supply:
> + description:
> + Phandle to the regulator that provides the VDDH power supply.
> +
> + avdd-supply:
> + description:
> + Phandle to the regulator that provides the AVDD power supply.
> +
> + ldoin-supply:
> + description:
> + Optional 2.5V to 5.5V LDO input supply.
> +
> +required:
> + - compatible
> + - reg
> + - vddh-supply
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + regulator@30 {
> + compatible = "adi,max20830";
> + reg = <0x30>;
> + vddh-supply = <&vddh>;
> + };
> + };
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0a3991c10ade20dd79cc7d1bf2a1d307ba6bd19d..031c743e979521a92ed9ac67915c178ce31727bd 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -15579,6 +15579,13 @@ F: Documentation/devicetree/bindings/hwmon/pmbus/adi,max17616.yaml
> F: Documentation/hwmon/max17616.rst
> F: drivers/hwmon/pmbus/max17616.c
>
> +MAX20830 HARDWARE MONITOR DRIVER
> +M: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
> +L: linux-hwmon@vger.kernel.org
> +S: Supported
> +W: https://ez.analog.com/linux-software-drivers
> +F: Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
> +
> MAX2175 SDR TUNER DRIVER
> M: Ramesh Shanmugasundaram <rashanmu@gmail.com>
> L: linux-media@vger.kernel.org
>
> --
> 2.34.1
>
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* Re: [PATCH v7 1/3] dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl
From: Conor Dooley @ 2026-04-16 15:54 UTC (permalink / raw)
To: Billy Tsai
Cc: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery, Linus Walleij, Bartosz Golaszewski,
Ryan Chen, Andrew Jeffery, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc, linux-gpio, linux-clk
In-Reply-To: <20260416-upstream_pinctrl-v7-1-d72762253163@aspeedtech.com>
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On Thu, Apr 16, 2026 at 03:29:43PM +0800, Billy Tsai wrote:
> Add a device tree binding for the pin controller found in the
> ASPEED AST2700 SoC0.
>
> The controller manages various peripheral functions such as eMMC, USB,
> VGA DDC, JTAG, and PCIe root complex signals.
>
> Describe the AST2700 SoC0 pin controller using standard pin multiplexing
> and configuration properties.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> .../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 162 +++++++++++++++++++++
> 1 file changed, 162 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> new file mode 100644
> index 000000000000..947f3cd09fcc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> @@ -0,0 +1,162 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED AST2700 SoC0 Pin Controller
> +
> +maintainers:
> + - Billy Tsai <billy_tsai@aspeedtech.com>
> +
> +description:
> + The AST2700 features a dual-SoC architecture with two interconnected SoCs,
> + each having its own System Control Unit (SCU) for independent pin control.
> + This pin controller manages the pin multiplexing for SoC0.
> +
> + The SoC0 pin controller manages pin functions including eMMC, VGA DDC,
> + dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces.
> +
> +properties:
> + compatible:
> + const: aspeed,ast2700-soc0-pinctrl
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + '-state$':
> + type: object
> + allOf:
> + - $ref: pinmux-node.yaml#
> + - $ref: pincfg-node.yaml#
> +
> + additionalProperties: false
> +
> + properties:
> + function:
> + enum:
> + - EMMC
> + - JTAGDDR
> + - JTAGM0
> + - JTAGPCIEA
> + - JTAGPCIEB
> + - JTAGPSP
> + - JTAGSSP
> + - JTAGTSP
> + - JTAGUSB3A
> + - JTAGUSB3B
> + - PCIERC0PERST
> + - PCIERC1PERST
> + - TSPRSTN
> + - UFSCLKI
> + - USB2AD0
> + - USB2AD1
> + - USB2AH
> + - USB2AHP
> + - USB2AHPD0
> + - USB2AXH
> + - USB2AXH2B
> + - USB2AXHD1
> + - USB2AXHP
> + - USB2AXHP2B
> + - USB2AXHPD1
> + - USB2BD0
> + - USB2BD1
> + - USB2BH
> + - USB2BHP
> + - USB2BHPD0
> + - USB2BXH
> + - USB2BXH2A
> + - USB2BXHD1
> + - USB2BXHP
> + - USB2BXHP2A
> + - USB2BXHPD1
> + - USB3AXH
> + - USB3AXH2B
> + - USB3AXHD
> + - USB3AXHP
> + - USB3AXHP2B
> + - USB3AXHPD
> + - USB3BXH
> + - USB3BXH2A
> + - USB3BXHD
> + - USB3BXHP
> + - USB3BXHP2A
> + - USB3BXHPD
> + - VB
> + - VGADDC
> +
> + groups:
> + enum:
> + - EMMCCDN
> + - EMMCG1
> + - EMMCG4
> + - EMMCG8
> + - EMMCWPN
> + - JTAG0
> + - PCIERC0PERST
> + - PCIERC1PERST
> + - TSPRSTN
> + - UFSCLKI
> + - USB2A
> + - USB2AAP
> + - USB2ABP
> + - USB2ADAP
> + - USB2AH
> + - USB2AHAP
> + - USB2B
> + - USB2BAP
> + - USB2BBP
> + - USB2BDBP
> + - USB2BH
> + - USB2BHBP
> + - USB3A
> + - USB3AAP
> + - USB3ABP
> + - USB3B
> + - USB3BAP
> + - USB3BBP
> + - VB0
> + - VB1
> + - VGADDC
> + pins:
> + enum:
> + - AB13
> + - AB14
> + - AC13
> + - AC14
> + - AD13
> + - AD14
> + - AE13
> + - AE14
> + - AE15
> + - AF13
> + - AF14
> + - AF15
Why do you have groups and pins?
Is it valid in your device to have groups and pins in the same node?
> +
> + drive-strength:
> + enum: [3, 6, 8, 11, 16, 18, 20, 23, 30, 32, 33, 35, 37, 38, 39, 41]
> +
> + bias-disable: true
> + bias-pull-up: true
> + bias-pull-down: true
> +
> +required:
> + - compatible
> + - reg
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pinctrl@400 {
> + compatible = "aspeed,ast2700-soc0-pinctrl";
> + reg = <0x400 0x318>;
> + emmc-state {
> + function = "EMMC";
> + groups = "EMMCG1";
> + };
> + };
>
> --
> 2.34.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v6 10/21] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC
From: Laurent Pinchart @ 2026-04-16 16:34 UTC (permalink / raw)
To: Tommaso Merciai
Cc: tomm.merciai, geert, linux-renesas-soc, biju.das.jz,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm,
Tomi Valkeinen, dri-devel, devicetree, linux-kernel, linux-clk
In-Reply-To: <191a4bc7-f19e-4771-b70d-e54dd5506799@bp.renesas.com>
On Fri, Apr 10, 2026 at 03:21:44PM +0200, Tommaso Merciai wrote:
> On 4/9/26 15:24, Laurent Pinchart wrote:
> > On Thu, Apr 09, 2026 at 01:15:18PM +0200, Tommaso Merciai wrote:
> >> On 4/8/26 17:00, Laurent Pinchart wrote:
> >>> On Wed, Apr 08, 2026 at 04:44:48PM +0200, Tommaso Merciai wrote:
> >>>> On 4/8/26 16:16, Laurent Pinchart wrote:
> >>>>> On Wed, Apr 08, 2026 at 04:02:14PM +0200, Tommaso Merciai wrote:
> >>>>>> On 4/8/26 14:24, Laurent Pinchart wrote:
> >>>>>>> On Wed, Apr 08, 2026 at 12:36:55PM +0200, Tommaso Merciai wrote:
> >>>>>>>> The RZ/G3E SoC has 2 LCD controllers (LCDC), each containing a Frame
> >>>>>>>> Compression Processor (FCPVD), a Video Signal Processor (VSPD), and a
> >>>>>>>> Display Unit (DU).
> >>>>>>>>
> >>>>>>>> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >>>>>>>> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> >>>>>>>>
> >>>>>>>> Add a new SoC-specific compatible string 'renesas,r9a09g047-du'.
> >>>>>>>>
> >>>>>>>> Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" to
> >>>>>>>> allow up to four output ports, and explicitly disable port@2 and port@3
> >>>>>>>> for existing SoCs that do not expose them.
> >>>>>>>>
> >>>>>>>> Describe the four output ports of the RZ/G3E DU:
> >>>>>>>>
> >>>>>>>> - port@0: DSI (available on both LCDC instances)
> >>>>>>>> - port@1: DPAD / parallel RGB (LCDC1 only)
> >>>>>>>> - port@2: LVDS channel 0 (LCDC0 only)
> >>>>>>>> - port@3: LVDS channel 1 (available on both LCDC instances)
> >>>>>>>>
> >>>>>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >>>>>>>> ---
> >>>>>>>> v5->v6:
> >>>>>>>> - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
> >>>>>>>> explicitly disable port@2 and port@3 for existing SoCs that do not expose
> >>>>>>>> them.
> >>>>>>>> - Reworked ports numbering + improved/fixed ports descriptions in the
> >>>>>>>> bindings documentation.
> >>>>>>>> - Improved commit body.
> >>>>>>>>
> >>>>>>>> v4->v5:
> >>>>>>>> - Dropped renesas,id property and updated bindings
> >>>>>>>> accordingly.
> >>>>>>>>
> >>>>>>>> v2->v3:
> >>>>>>>> - No changes.
> >>>>>>>>
> >>>>>>>> v2->v3:
> >>>>>>>> - No changes.
> >>>>>>>>
> >>>>>>>> v1->v2:
> >>>>>>>> - Use single compatible string instead of multiple compatible strings
> >>>>>>>> for the two DU instances, leveraging a 'renesas,id' property to
> >>>>>>>> differentiate between DU0 and DU1.
> >>>>>>>> - Updated commit message accordingly.
> >>>>>>>>
> >>>>>>>> .../bindings/display/renesas,rzg2l-du.yaml | 30 ++++++++++++++++++-
> >>>>>>>> 1 file changed, 29 insertions(+), 1 deletion(-)
> >>>>>>>>
> >>>>>>>> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>>>>>> index 5add3b832eab..32da0b5ec88c 100644
> >>>>>>>> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>>>>>> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>>>>>> @@ -20,6 +20,7 @@ properties:
> >>>>>>>> - enum:
> >>>>>>>> - renesas,r9a07g043u-du # RZ/G2UL
> >>>>>>>> - renesas,r9a07g044-du # RZ/G2{L,LC}
> >>>>>>>> + - renesas,r9a09g047-du # RZ/G3E
> >>>>>>>> - renesas,r9a09g057-du # RZ/V2H(P)
> >>>>>>>> - items:
> >>>>>>>> - enum:
> >>>>>>>> @@ -61,7 +62,7 @@ properties:
> >>>>>>>> model-dependent. Each port shall have a single endpoint.
> >>>>>>>>
> >>>>>>>> patternProperties:
> >>>>>>>> - "^port@[0-1]$":
> >>>>>>>> + "^port@[0-3]$":
> >>>>>>>> $ref: /schemas/graph.yaml#/properties/port
> >>>>>>>> unevaluatedProperties: false
> >>>>>>>>
> >>>>>>>> @@ -103,6 +104,8 @@ allOf:
> >>>>>>>> port@0:
> >>>>>>>> description: DPI
> >>>>>>>> port@1: false
> >>>>>>>> + port@2: false
> >>>>>>>> + port@3: false
> >>>>>>>>
> >>>>>>>> required:
> >>>>>>>> - port@0
> >>>>>>>> @@ -119,6 +122,8 @@ allOf:
> >>>>>>>> description: DSI
> >>>>>>>> port@1:
> >>>>>>>> description: DPI
> >>>>>>>> + port@2: false
> >>>>>>>> + port@3: false
> >>>>>>>>
> >>>>>>>> required:
> >>>>>>>> - port@0
> >>>>>>>> @@ -135,9 +140,32 @@ allOf:
> >>>>>>>> port@0:
> >>>>>>>> description: DSI
> >>>>>>>> port@1: false
> >>>>>>>> + port@2: false
> >>>>>>>> + port@3: false
> >>>>>>>>
> >>>>>>>> required:
> >>>>>>>> - port@0
> >>>>>>>> + - if:
> >>>>>>>> + properties:
> >>>>>>>> + compatible:
> >>>>>>>> + contains:
> >>>>>>>> + const: renesas,r9a09g047-du
> >>>>>>>> + then:
> >>>>>>>> + properties:
> >>>>>>>> + ports:
> >>>>>>>> + properties:
> >>>>>>>> + port@0:
> >>>>>>>> + description: DSI
> >>>>>>>> + port@1:
> >>>>>>>> + description: DPAD
> >>>>>>>> + port@2:
> >>>>>>>> + description: LVDS, Channel 0
> >>>>>>>> + port@3:
> >>>>>>>> + description: LVDS, Channel 1
> >>>>>>>> +
> >>>>>>>> + required:
> >>>>>>>> + - port@0
> >>>>>>>> + - port@3
> >>>>>>>
> >>>>>>> Why are ports 1 and 2 not required ?
> >>>>>>
> >>>>>> About this we had a similar discussion on v5[0]
> >>>>>> We are using the same compatible and:
> >>>>>>
> >>>>>> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >>>>>> |
> >>>>>> --> then has:
> >>>>>> port@0
> >>>>>> port@2
> >>>>>> port@3
> >>>>>>
> >>>>>>
> >>>>>> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> >>>>>> |
> >>>>>> --> then has:
> >>>>>> port@0
> >>>>>> port@1
> >>>>>> port@3
> >>>>>
> >>>>> Ah yes, I forget there are two LCDC instances with different output
> >>>>> configurations.
> >>>>>
> >>>>> Something still looks a bit weird to me though. For LCDC1, which
> >>>>> supports a single LVDS channel, you use the port described as the second
> >>>>> LVDS channel. Is there a reason not to use port@2 ?
> >>>>
> >>>> 9.11 Low Voltage Differential Signaling (LVDS)
> >>>> 9.11.1.2 Block Diagram
> >>>> Figure 9.11-1 shows a block diagram of LVDS.
> >>>>
> >>>> LCDC1 is connected to LVDS, Channel 1
> >>>> For this reason I'm using port@3.
> >>>
> >>> Re-reading that, I think I've misinterpreted the hardware architecture.
> >>> Doesn't the DU have a single output, that is connected the multiple
> >>> encoders (LVDS and DSI for LCDC0 and LVDS, DSI and DPI for LCDC1) ? It
> >>> seems modelling it with a single port and multiple endpoints would
> >>> better match the device.
> >>>
> >>> For LVDS in particular, I see a single LVDS encoder with two channels,
> >>> so there should not be two LVDS output ports in the DU. The two ports
> >>> should be on the output of the LVDS device.
> >>
> >> You are suggesting the following dt architecture:
> >>
> >> du0: display@16460000 {
> >> compatible = "renesas,r9a09g047-du";
> >> reg = <0 0x16460000 0 0x10000>;
> >> interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
> >> clocks = <&cpg CPG_MOD 0xed>,
> >> <&cpg CPG_MOD 0xee>,
> >> <&cpg CPG_MOD 0xef>;
> >> clock-names = "aclk", "pclk", "vclk";
> >> power-domains = <&cpg>;
> >> resets = <&cpg 0xdc>;
> >> renesas,vsps = <&vspd0 0>;
> >> status = "disabled";
> >>
> >> port {
> >> du0_out_dsi: endpoint@0 {
> >> reg = <0>;
> >> };
> >>
> >> du0_out_lvds0: endpoint@2 {
> >> reg = <2>;
> >> };
> >>
> >> du0_out_lvds1: endpoint@3 {
> >> reg = <3>;
> >> };
> >> }
> >> };
> >>
> >> du1: display@16490000 {
> >> compatible = "renesas,r9a09g047-du";
> >> reg = <0 0x16490000 0 0x10000>;
> >> interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
> >> clocks = <&cpg CPG_MOD 0x1a8>,
> >> <&cpg CPG_MOD 0x1a9>,
> >> <&cpg CPG_MOD 0x1aa>;
> >> clock-names = "aclk", "pclk", "vclk";
> >> power-domains = <&cpg>;
> >> resets = <&cpg 0x11e>;
> >> renesas,vsps = <&vspd1 0>;
> >> status = "disabled";
> >>
> >> port {
> >> du1_out_dsi: endpoint@0 {
> >> reg = <0>;
> >> };
> >>
> >> du1_out_rgb: endpoint@1 {
> >> reg = <1>;
> >> };
> >>
> >> du1_out_lvds1: endpoint@3 {
> >> reg = <3>;
> >> };
> >> }
> >> };
> >>
> >>
> >> Please correct me if I'm wrong.
> >
> > That's right. It would match the hardware, or at least my understanding
> > of the hardware based on the documentation. As far as I can tell, each
> > DU has a single 24-bit output port connected to multiple encoders.
>
> Thanks for the clarification.
>
> I want to make sure I understand the intended architecture correctly,
> because I see a potential conflict between your feedback on the two patches.
>
> For [1], you confirmed the two separate DU nodes (DU0 and DU1) with the
> single-port/multi-endpoint model. That maps to two separate platform
> devices, which means two separate DRM devices.
Not necessarily, it would be possible to instantiate a single drm_device
to cover both platform_device instances. It would require a bit of
manual work in the driver though.
> For [2], you suggested:
>
> "you can have one DRM device that covers two LCDCs, with one CRTC each,
> both connected to the same DSI encoder. Userspace then selects which
> CRTC drives which connector."
>
> Please correct me if I'm wrong but to me these two appear to be
> incompatible. With two separate DRM devices,the DSI encoder and its
> connector can only belong to one of them. Userspace cannot select
> between CRTCs across two DRM devices.
>
> To support the single-DRM-device model you describe, both DU0 and DU1
> would need to be managed by a single driver instance, similar to R-Car
> DU which aggregate multiple LCDC channels into one DRM device.
>
> Using a single DRM device that spawn 2 crtc (1 du dt node ) this use
> case can be tested with the following cmds:
>
> modetest -M rzg2l-du -s 58@55:800x600-56.25@XR24
> modetest -M rzg2l-du -s 58@56:800x600-56.25@XR24
>
> Could you clarify which architecture is the intended direction?
>
> Option A: Two separate DRM devices (2 DU dt nodes, current approach),
> with the DSI input selected via DT configuration.
> The dynamic vclk selection I implemented still applies,
> but runtime CRTC switching from userspace is not possible.
>
> Option B: A single DRM device aggregating both DU instances (1 DU dt node),
> with two CRTCs both connected to the DSI encoder.
I meant option B.
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/8f814f22ff62dcde6153260e2c8c29a5415c9a89.1775636898.git.tommaso.merciai.xr@bp.renesas.com/
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/9e0f64dd5e1efb0d27219416121c91a19da96ebd.1775636898.git.tommaso.merciai.xr@bp.renesas.com/
>
> >>>>>> Then port@1 is required for DU1 but not for DU0.
> >>>>>> Same port@2 is required for DU0 but not for DU1.
> >>>>>>
> >>>>>> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/ca022fdbba5236c36e0cb3095db4c31e8e0cb1b8.1770996493.git.tommaso.merciai.xr@bp.renesas.com/
> >>>>>>
> >>>>>>>>
> >>>>>>>> examples:
> >>>>>>>> # RZ/G2L DU
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH RFC 06/10] arm64: dts: qcom: msm8939-asus-z00t: add Venus
From: Erikas Bitovtas @ 2026-04-16 16:57 UTC (permalink / raw)
To: Konrad Dybcio, Bryan O'Donoghue, Vikash Garodia,
Dikshita Agarwal, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, André Apitzsch,
Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <0a5f9bd6-d3ea-4819-8be3-cc5a06ec0339@oss.qualcomm.com>
On 4/16/26 6:17 PM, Konrad Dybcio wrote:
> On 4/16/26 3:43 PM, Erikas Bitovtas wrote:
>> Enable Venus video encoder/decoder for Asus ZenFone 2 Laser/Selfie.
>>
>> Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
>> ---
>> arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
>> index 90e966242720..231a3e9c1929 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
>> +++ b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
>> @@ -267,6 +267,14 @@ &usb_hs_phy {
>> extcon = <&usb_id>;
>> };
>>
>> +&venus {
>> + status = "okay";
>
> You need a firmware path here
When I tested Venus on my device, it loaded without one specified -
msm-firmware-loader creates a symbolic link from modem partition for
firmware. Additionally, none of the MSM8916 devices seem to include a
firmware name. Has something changed since then?
> Konrad
^ permalink raw reply
* Re: [PATCH RFC 00/10] media: qcom: venus: add MSM8939 support
From: Erikas Bitovtas @ 2026-04-16 17:00 UTC (permalink / raw)
To: Konrad Dybcio, Bryan O'Donoghue, Vikash Garodia,
Dikshita Agarwal, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, André Apitzsch,
Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <b7b6c3e7-f8e6-4b73-b17a-e5e1691a54f8@oss.qualcomm.com>
>> 3. MSM8939 supports HEVC decoding, however, as the patchset is written
>> now, it does not work. It can be enabled, however, it will result in
>> breakage of Venus for faulty MSM8916 firmwares, because the code
>> disabling HEVC for HFI v1 needs to be removed, and as per commit
>> c50cc6dc6c48 ("media: venus: hfi_parser: Ignore HEVC encoding for V1"),
>> this would break support for some MSM8916 devices. What could be the
>> best way to work around this?
>
> if (!device_is_compatible(core->dev, "qcom,msm8939-venus"))?
>
> Also, you mentioned HEVC *de*coding, while the commit you pointed to
> disables *en*coding (decoding had been already disabled prior to that
> commit)
>
> Konrad
From the commit message I assumed HEVC decoding had already been
disabled for the same reasons encoding was - faulty firmware reporting
codecs it doesn't actually support.
^ permalink raw reply
* [PATCH 0/2] clocksource/timer-econet-en751221: Support irq number per timer
From: Caleb James DeLisle @ 2026-04-16 17:50 UTC (permalink / raw)
To: linux-mips
Cc: naseefkm, daniel.lezcano, tglx, robh, krzk+dt, conor+dt,
linux-kernel, devicetree, Caleb James DeLisle
In prep for adding EN751627 and EN7528 SoCs, we need to support the GIC
interrupt controller. Unlike the intc in the EN751221, this intc does
not create a percpu interrupt for the timers, so we update the timer
driver to support both models.
Caleb James DeLisle (2):
dt-bindings: timer: econet: Update EN751627 for multi-IRQ
clocksource/timer-econet-en751221: Support irq number per timer
.../bindings/timer/econet,en751221-timer.yaml | 16 +-
drivers/clocksource/Kconfig | 5 +-
drivers/clocksource/timer-econet-en751221.c | 137 ++++++++++++++----
3 files changed, 127 insertions(+), 31 deletions(-)
base-commit: ff1c0c5d07028a84837950b619d30da623f8ddb2
--
2.39.5
^ permalink raw reply
* [PATCH 1/2] dt-bindings: timer: econet: Update EN751627 for multi-IRQ
From: Caleb James DeLisle @ 2026-04-16 17:51 UTC (permalink / raw)
To: linux-mips
Cc: naseefkm, daniel.lezcano, tglx, robh, krzk+dt, conor+dt,
linux-kernel, devicetree, Caleb James DeLisle
In-Reply-To: <20260416175101.958073-1-cjd@cjdns.fr>
From conception, this driver supported EN751627 as it is the same
hardware that is used in EN751221. However, it was expected that
EN751627 would use a percpu IRQ as does EN751221, this is how it
works in vendor code. However upon finding that the "mti,gic" intc
works on EN751627 with no modification - but it provides a unique
interrupt per-timer, it is deemed best to make this driver use
multiple IRQs when on the EN751627 platform.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
.../bindings/timer/econet,en751221-timer.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
index c1e7c2b6afde..f338739e039c 100644
--- a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
@@ -28,8 +28,8 @@ properties:
maxItems: 2
interrupts:
- maxItems: 1
- description: A percpu-devid timer interrupt shared across CPUs.
+ minItems: 1
+ maxItems: 4
clocks:
maxItems: 1
@@ -52,21 +52,31 @@ allOf:
items:
- description: VPE timers 0 and 1
- description: VPE timers 2 and 3
+ interrupts:
+ description: An interrupt for each timer (one per VPE)
+ minItems: 4
else:
properties:
reg:
items:
- description: VPE timers 0 and 1
+ interrupts:
+ description: A percpu-devid timer interrupt shared across timers
+ maxItems: 1
additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
timer@1fbf0400 {
compatible = "econet,en751627-timer", "econet,en751221-timer";
reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>;
interrupt-parent = <&intc>;
- interrupts = <30>;
+ interrupts = <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hpt_clock>;
};
- |
--
2.39.5
^ permalink raw reply related
* [PATCH 2/2] clocksource/timer-econet-en751221: Support irq number per timer
From: Caleb James DeLisle @ 2026-04-16 17:51 UTC (permalink / raw)
To: linux-mips
Cc: naseefkm, daniel.lezcano, tglx, robh, krzk+dt, conor+dt,
linux-kernel, devicetree, Caleb James DeLisle
In-Reply-To: <20260416175101.958073-1-cjd@cjdns.fr>
This timer was first developed on the EN751221 which is a MIPS 34Kc
and therefore has a custom interrupt controller. The hardware for
econet,en751221-intc implements percpu routing of the timer
interrupts.
However, the EN751627 and EN7528 are MIPS 1004Kc based, and
therefore use the standard mti,gic compatible interrupt controller.
This interrupt controller uses a different IRQ number for each
timer interrupt.
Add support for both models in this timer driver.
Co-developed-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Ahmed Naseef <naseefkm@gmail.com>
Link: https://github.com/openwrt/openwrt/commit/fab098cb6121647ca9cc6e501d56ebe8a9ea550b#diff-a09ee5e4166e89df337d03c1455dce7b81eb89797b1d0f714476b188e6685334
[cjd@cjdns.fr minor changes:
Set ECONET_MAX_IRQS to NR_CPUS rather than 4
Use is_percpu_irq() instead of field
Do not set CLOCK_EVT_FEAT_PERCPU in non-percpu mode
Fold cevt_init() into timer_init()
]
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
drivers/clocksource/Kconfig | 5 +-
drivers/clocksource/timer-econet-en751221.c | 137 ++++++++++++++++----
2 files changed, 114 insertions(+), 28 deletions(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index d1a33a231a44..9a77f38d5fb7 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -79,7 +79,10 @@ config ECONET_EN751221_TIMER
select CLKSRC_MMIO
select TIMER_OF
help
- Support for CPU timer found on EcoNet MIPS based SoCs.
+ Support for CPU timer found on EcoNet EN75xx MIPS based SoCs
+ (EN751221, EN751627, EN7528). The driver supports both GIC-based
+ (separate IRQ per CPU) and legacy interrupt controller (percpu IRQ)
+ modes.
config FTTMR010_TIMER
bool "Faraday Technology timer driver" if COMPILE_TEST
diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksource/timer-econet-en751221.c
index 4008076b1a21..e280ee8c2b1c 100644
--- a/drivers/clocksource/timer-econet-en751221.c
+++ b/drivers/clocksource/timer-econet-en751221.c
@@ -3,11 +3,13 @@
* Timer present on EcoNet EN75xx MIPS based SoCs.
*
* Copyright (C) 2025 by Caleb James DeLisle <cjd@cjdns.fr>
+ * Copyright (C) 2025 by Ahmed Naseef <naseefkm@gmail.com>
*/
#include <linux/io.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
@@ -21,14 +23,26 @@
#define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0)
/* 34Kc hardware has 1 block and 1004Kc has 2. */
#define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2)
+#define ECONET_MAX_IRQS NR_CPUS
static struct {
void __iomem *membase[ECONET_NUM_BLOCKS];
u32 freq_hz;
+ int irqs[ECONET_MAX_IRQS];
+ int num_irqs;
} econet_timer __ro_after_init;
static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu);
+/* This timer supports two interrupt controller models, either 1 IRQ which is in per-cpu
+ * mode which is used on 34Kc CPUs, and separate IRQ number per CPU which is used on
+ * 1004Kc CPUs with GIC intc.
+ */
+static inline bool is_percpu_irq(void)
+{
+ return econet_timer.num_irqs == 1;
+}
+
/* Each memory block has 2 timers, the order of registers is:
* CTL, CMR0, CNT0, CMR1, CNT1
*/
@@ -98,12 +112,21 @@ static int cevt_init_cpu(uint cpu)
struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, cpu);
u32 reg;
+ if (!is_percpu_irq() && cpu >= econet_timer.num_irqs)
+ return -EINVAL;
+
pr_debug("%s: Setting up clockevent for CPU %d\n", cd->name, cpu);
reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu);
iowrite32(reg, reg_ctl(cpu));
- enable_percpu_irq(cd->irq, IRQ_TYPE_NONE);
+ if (is_percpu_irq()) {
+ enable_percpu_irq(cd->irq, IRQ_TYPE_NONE);
+ } else {
+ if (irq_force_affinity(econet_timer.irqs[cpu], cpumask_of(cpu)))
+ pr_warn("%s: failed to set IRQ %d affinity to CPU %d\n",
+ cd->name, econet_timer.irqs[cpu], cpu);
+ }
/* Do this last because it synchronously configures the timer */
clockevents_config_and_register(cd, econet_timer.freq_hz,
@@ -126,7 +149,20 @@ static void __init cevt_dev_init(uint cpu)
iowrite32(U32_MAX, reg_compare(cpu));
}
-static int __init cevt_init(struct device_node *np)
+static void __init cevt_setup_clockevent(struct clock_event_device *cd,
+ struct device_node *np,
+ int irq, int cpu)
+{
+ cd->rating = 310;
+ cd->features = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_C3STOP;
+ cd->set_next_event = cevt_set_next_event;
+ cd->irq = irq;
+ cd->cpumask = cpumask_of(cpu);
+ cd->name = np->name;
+}
+
+static int __init cevt_init_percpu(struct device_node *np)
{
int i, irq, ret;
@@ -137,42 +173,65 @@ static int __init cevt_init(struct device_node *np)
}
ret = request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_pcpu);
-
if (ret < 0) {
pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret);
- goto err_unmap_irq;
+ irq_dispose_mapping(irq);
+ return ret;
}
for_each_possible_cpu(i) {
struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, i);
- cd->rating = 310;
- cd->features = CLOCK_EVT_FEAT_ONESHOT |
- CLOCK_EVT_FEAT_C3STOP |
- CLOCK_EVT_FEAT_PERCPU;
- cd->set_next_event = cevt_set_next_event;
- cd->irq = irq;
- cd->cpumask = cpumask_of(i);
- cd->name = np->name;
+ cevt_setup_clockevent(cd, np, irq, i);
+ cd->features |= CLOCK_EVT_FEAT_PERCPU;
+ cevt_dev_init(i);
+ }
+
+ return 0;
+}
+static int __init cevt_init_separate(struct device_node *np)
+{
+ int i, ret;
+
+ for (i = 0; i < econet_timer.num_irqs; i++) {
+ struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, i);
+
+ econet_timer.irqs[i] = irq_of_parse_and_map(np, i);
+ if (econet_timer.irqs[i] <= 0) {
+ pr_err("%pOFn: irq_of_parse_and_map failed", np);
+ ret = -EINVAL;
+ goto err_free_irqs;
+ }
+
+ ret = request_irq(econet_timer.irqs[i], cevt_interrupt,
+ IRQF_TIMER | IRQF_NOBALANCING,
+ np->name, NULL);
+ if (ret < 0) {
+ pr_err("%pOFn: IRQ %d setup failed (%d)\n", np,
+ econet_timer.irqs[i], ret);
+ irq_dispose_mapping(econet_timer.irqs[i]);
+ goto err_free_irqs;
+ }
+
+ cevt_setup_clockevent(cd, np, econet_timer.irqs[i], i);
cevt_dev_init(i);
}
- cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
- "clockevents/econet/timer:starting",
- cevt_init_cpu, NULL);
return 0;
-err_unmap_irq:
- irq_dispose_mapping(irq);
+err_free_irqs:
+ while (--i >= 0) {
+ free_irq(econet_timer.irqs[i], NULL);
+ irq_dispose_mapping(econet_timer.irqs[i]);
+ }
return ret;
}
static int __init timer_init(struct device_node *np)
{
- int num_blocks = DIV_ROUND_UP(num_possible_cpus(), 2);
struct clk *clk;
- int ret;
+ int ret, i;
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
@@ -182,11 +241,18 @@ static int __init timer_init(struct device_node *np)
econet_timer.freq_hz = clk_get_rate(clk);
- for (int i = 0; i < num_blocks; i++) {
+ econet_timer.num_irqs = of_irq_count(np);
+ if (econet_timer.num_irqs <= 0 || econet_timer.num_irqs > ECONET_MAX_IRQS) {
+ pr_err("%pOFn: invalid IRQ count %d\n", np, econet_timer.num_irqs);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ECONET_NUM_BLOCKS; i++) {
econet_timer.membase[i] = of_iomap(np, i);
if (!econet_timer.membase[i]) {
pr_err("%pOFn: failed to map register [%d]\n", np, i);
- return -ENXIO;
+ ret = -ENXIO;
+ goto err_unmap;
}
}
@@ -196,21 +262,38 @@ static int __init timer_init(struct device_node *np)
clocksource_mmio_readl_up);
if (ret) {
pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret);
- return ret;
+ goto err_unmap;
}
- ret = cevt_init(np);
+ if (is_percpu_irq())
+ ret = cevt_init_percpu(np);
+ else
+ ret = cevt_init_separate(np);
+
if (ret < 0)
- return ret;
+ goto err_unmap;
+
+ cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+ "clockevents/econet/timer:starting",
+ cevt_init_cpu, NULL);
sched_clock_register(sched_clock_read, ECONET_BITS,
econet_timer.freq_hz);
- pr_info("%pOFn: using %u.%03u MHz high precision timer\n", np,
+ pr_info("%pOFn: using %u.%03u MHz high precision timer (%s mode)\n", np,
econet_timer.freq_hz / 1000000,
- (econet_timer.freq_hz / 1000) % 1000);
+ (econet_timer.freq_hz / 1000) % 1000,
+ is_percpu_irq() ? "percpu" : "separate IRQ");
return 0;
+
+err_unmap:
+ for (i = 0; i < ECONET_NUM_BLOCKS; i++) {
+ if (econet_timer.membase[i])
+ iounmap(econet_timer.membase[i]);
+ }
+
+ return ret;
}
-TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init);
+TIMER_OF_DECLARE(econet_en751221_timer, "econet,en751221-timer", timer_init);
--
2.39.5
^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: hwmon: pmbus: add max20830
From: Guenter Roeck @ 2026-04-16 18:01 UTC (permalink / raw)
To: Conor Dooley
Cc: Alexis Czezar Torreno, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jonathan Corbet, Shuah Khan, linux-hwmon,
devicetree, linux-kernel, linux-doc
In-Reply-To: <20260416-diaphragm-corrode-494560404ed4@spud>
On Thu, Apr 16, 2026 at 04:51:37PM +0100, Conor Dooley wrote:
> On Thu, Apr 16, 2026 at 03:59:10PM +0800, Alexis Czezar Torreno wrote:
> > Add device tree documentation for MAX20830 step-down DC-DC switching
> > regulator with PMBus interface.
> >
> > Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
> > ---
> > .../bindings/hwmon/pmbus/adi,max20830.yaml | 61 ++++++++++++++++++++++
> > MAINTAINERS | 7 +++
> > 2 files changed, 68 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..8b3ec1ffa0c9460de2122f6606ce3dcbcdfbbcc7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml
> > @@ -0,0 +1,61 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,max20830.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Analog Devices MAX20830 Step-Down Switching Regulator with PMBus
> > +
> > +maintainers:
> > + - Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
> > +
> > +description: |
> > + The MAX20830 is a fully integrated step-down DC-DC switching regulator with
> > + PMBus interface. It provides 2.7V to 16V input, 0.4V to 5.8V adjustable
> > + output, and up to 30A output current. It allows monitoring of input/output
> > + voltage, output current and temperature through the PMBus serial interface.
> > + Datasheet:
> > + https://www.analog.com/en/products/max20830.html
> > +
> > +allOf:
> > + - $ref: /schemas/regulator/regulator.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: adi,max20830
> > +
> > + reg:
> > + maxItems: 1
>
> On the previous version, you got an LLM comment about not having the
> interrupts property amongst other things.
> I think the other things got implemented, but I didn't see any reply to
> the bot about that?
> I think the answer is that it shouldn't because the pin it referenced
> doesn't exist, but when looking at the schematic I have to wonder if
I had to look this up in the datasheet. A SMBus chip with no alert pin is
a bit odd, but you are correct.
> there should be an interrupts property for dealing with "pgood"?
>
FWIW, I have never seen that. Normally such pins are used to take devices
out of reset.
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH 02/16] dt-bindings: interrupt-controller: Describe EIP-201 AIC
From: Aleksander Jan Bajkowski @ 2026-04-16 18:04 UTC (permalink / raw)
To: Miquel Raynal (Schneider Electric), Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thomas Gleixner, Olivia Mackall, Herbert Xu, Jayesh Choudhary,
David S. Miller, Christian Marangi, Antoine Tenart,
Geert Uytterhoeven, Magnus Damm
Cc: Thomas Petazzoni, Pascal EBERHARD, Wolfram Sang, linux-clk,
devicetree, linux-kernel, linux-crypto, linux-renesas-soc
In-Reply-To: <20260327-schneider-v7-0-rc1-crypto-v1-2-5e6ff7853994@bootlin.com>
Hi Miquel,
On 27/03/2026 21:09, Miquel Raynal (Schneider Electric) wrote:
> diff --git a/include/dt-bindings/interrupt-controller/inside-secure,safexcel-eip201.h b/include/dt-bindings/interrupt-controller/inside-secure,safexcel-eip201.h
> new file mode 100644
> index 000000000000..ead73bd96296
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/inside-secure,safexcel-eip201.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +
> +#ifndef _DT_BINDINGS_IRQ_SAFEXCEL_EIP201_AIC_H
> +#define _DT_BINDINGS_IRQ_SAFEXCEL_EIP201_AIC_H
> +
> +#define AIC_PKA_INT0 0
> +#define AIC_PKA_INT1 1
> +#define AIC_PKA_INT2 2
> +#define AIC_TRNG_INT 3
> +#define AIC_RESERVED 4
> +#define AIC_SL_ERR_INT 5
> +#define AIC_PROTECTION_INT 6
> +
> +#endif
This interrupt mapping is specific to the EIP-150. The EIP-201 is also
integrated
into other accelerators, such as the EIP-97, EIP-196, and EIP-197, and the
interrupt mapping is likely different there. Maybe it would be better to use
eip150 name instead of eip201?
As for EIP-28, it is also part of EIP-94. EIP-94 is supported by the
amcc driver.
EIP-94 consists of four components:
* crypto accelerator (unnamed?),
* PRNG (EIP-73d),
* TRNG (unnamed?),
* PKA (EIP-28).
Only the first three components are supported by the amcc driver.
Best regards,
Aleksander
^ permalink raw reply
* Re: [PATCH v2 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC
From: Yao Zi @ 2026-04-16 18:28 UTC (permalink / raw)
To: Shuwei Wu, Anand Moon
Cc: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Yixun Lan, linux-pm, linux-kernel, linux-riscv,
spacemit, devicetree
In-Reply-To: <DHUCL24GMX7D.369IWK9DLPZPX@mailbox.org>
On Thu, Apr 16, 2026 at 01:59:05PM +0800, Shuwei Wu wrote:
> On Tue Apr 14, 2026 at 9:25 PM CST, Anand Moon wrote:
> > Hi Shuwei,
> >
> > On Fri, 10 Apr 2026 at 13:30, Shuwei Wu <shuwei.wu@mailbox.org> wrote:
> >>
> >> Add Operating Performance Points (OPP) tables and CPU clock properties
> >> for the two clusters in the SpacemiT K1 SoC.
> >>
> >> Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3
> >> board to fully enable CPU DVFS.
> >>
> >> Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
> >>
> >> ---
> >> Changes in v2:
> >> - Add k1-opp.dtsi with OPP tables for both CPU clusters
> >> - Assign CPU supplies and include OPP table for Banana Pi BPI-F3
> >> ---
> >> arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++++-
> >> arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++++++++
> >> arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++
> >> 3 files changed, 147 insertions(+), 1 deletion(-)
> >>
...
> Regarding the necessity of listing these clocks in the DT, my analysis is as follows:
> 1. For CCI550, I did not find a clear definition of this clock's specific role
> in the SoC datasheet. Although the vendor kernel increases its frequency,
> my benchmarks show that maintaining the mainline default (245.76MHz) has a
> negligible impact on CPU performance.
FYI, CCI550 is used for naming an ARM interconnect IP[1], which matches
your observation.
...
> Best regards,
> Shuwei Wu
Regards,
Yao Zi.
[1]: https://developer.arm.com/Processors/CoreLink%20CCI-550
^ permalink raw reply
* Re: [PATCH v5 05/14] ASoC: rsnd: Add audmacpp clock and reset support for RZ/G3E
From: Mark Brown @ 2026-04-16 18:57 UTC (permalink / raw)
To: John Madieu
Cc: Kuninori Morimoto, Liam Girdwood, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
Geert Uytterhoeven, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260415124731.3684773-6-john.madieu.xa@bp.renesas.com>
[-- Attachment #1: Type: text/plain, Size: 918 bytes --]
On Wed, Apr 15, 2026 at 12:47:22PM +0000, John Madieu wrote:
> + /*
> + * Audio DMAC peri-peri clock and reset for RZ/G3E.
> + * These use optional APIs, so they gracefully return NULL
> + * (no error) on platforms whose DT does not provide them.
> + */
> + dmac->audmapp_rstc =
> + devm_reset_control_get_optional_exclusive_deasserted(dev, "audmapp");
> + if (IS_ERR(dmac->audmapp_rstc)) {
> + return dev_err_probe(dev, PTR_ERR(dmac->audmapp_rstc),
> + "failed to get audmapp reset\n");
> + }
> +
> + dmac->audmapp_clk = devm_clk_get_optional_enabled(dev, "audmapp");
> + if (IS_ERR(dmac->audmapp_clk)) {
> + return dev_err_probe(dev, PTR_ERR(dmac->audmapp_clk),
> + "failed to get audmapp clock\n");
> + }
Do we need the clock running before deasserting reset? Usually the flow
is to get the resources the hardware requires stable before we release,
that helps everything start up cleanly.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
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