* [PATCH v10 2/2] media: i2c: add Himax HM1246 image sensor driver
From: Matthias Fend @ 2026-06-19 12:28 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans Verkuil, Sakari Ailus, Hans de Goede,
Ricardo Ribalda, André Apitzsch, Tarang Raval,
Andy Shevchenko, Benjamin Mugnier, Sylvain Petinot, Dongcheng Yan,
Bryan O'Donoghue, Alan Stern, Jingjing Xiong,
Heimir Thor Sverrisson, Mehdi Djait, Vladimir Zapolskiy,
Laurent Pinchart, Hardevsinh Palaniya, Svyatoslav Ryhel,
Philipp Zabel, Hans Verkuil, Hans de Goede, Xiaolei Wang,
Walter Werner Schneider, Kate Hsuan, Bartosz Golaszewski,
Miguel Vadillo
Cc: linux-media, devicetree, linux-kernel, Hao Yao, Himanshu Bhavani,
Matthias Fend
In-Reply-To: <20260619-hm1246-v10-0-d88e431a6c11@emfend.at>
Add a V4L2 sub-device driver for Himax HM1246 image sensor.
The Himax HM1246-AWD is a 1/3.7-Inch CMOS image sensor SoC with an active
array size of 1296 x 976. It is programmable through an I2C interface and
connected via parallel bus.
The sensor has an internal ISP with a complete image processing pipeline
including control loops. However, this driver uses the sensor in raw mode
and the entire ISP is bypassed.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
---
MAINTAINERS | 1 +
drivers/media/i2c/Kconfig | 10 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/hm1246.c | 1291 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 1303 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c320e7e9a2bd88319945bfe1202bc891d35f0f7c..ca13a5b21306e921e077e2548f6242041c6ee24c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11558,6 +11558,7 @@ M: Matthias Fend <matthias.fend@emfend.at>
L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/i2c/himax,hm1246.yaml
+F: drivers/media/i2c/hm1246.c
HIMAX HX83112B TOUCHSCREEN SUPPORT
M: Job Noorman <job@noorman.info>
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 5d173e0ecf424f2f204f8d426be818e44357f8e4..52398bad32a0989c40097524ee9dde04e76813b8 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -137,6 +137,16 @@ config VIDEO_HI847
To compile this driver as a module, choose M here: the
module will be called hi847.
+config VIDEO_HM1246
+ tristate "Himax HM1246 sensor support"
+ select V4L2_CCI_I2C
+ help
+ This is a Video4Linux2 sensor driver for the Himax
+ HM1246 camera.
+
+ To compile this driver as a module, choose M here: the
+ module will be called hm1246.
+
config VIDEO_IMX111
tristate "Sony IMX111 sensor support"
select V4L2_CCI_I2C
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index e45359efe0e41e13e3c0869e5ead7d6cf4aca3a7..df420ff4e1d6304ef62f9cd84c8ddb9e2db30a11 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_VIDEO_GC2145) += gc2145.o
obj-$(CONFIG_VIDEO_HI556) += hi556.o
obj-$(CONFIG_VIDEO_HI846) += hi846.o
obj-$(CONFIG_VIDEO_HI847) += hi847.o
+obj-$(CONFIG_VIDEO_HM1246) += hm1246.o
obj-$(CONFIG_VIDEO_I2C) += video-i2c.o
obj-$(CONFIG_VIDEO_IMX111) += imx111.o
obj-$(CONFIG_VIDEO_IMX208) += imx208.o
diff --git a/drivers/media/i2c/hm1246.c b/drivers/media/i2c/hm1246.c
new file mode 100644
index 0000000000000000000000000000000000000000..ba120967814f3b2b4a5d2d6b1b6e4f5e5139944f
--- /dev/null
+++ b/drivers/media/i2c/hm1246.c
@@ -0,0 +1,1291 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Himax HM1246 image sensor
+ *
+ * Copyright 2026 Matthias Fend <matthias.fend@emfend.at>
+ */
+
+#include <linux/array_size.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/limits.h>
+#include <linux/math.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/types.h>
+#include <linux/units.h>
+#include <media/media-entity.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-cci.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-subdev.h>
+
+/* Status registers */
+#define HM1246_MODEL_ID_REG CCI_REG16(0x0000)
+
+/* General setup registers */
+#define HM1246_MODE_SELECT_REG CCI_REG8(0x0100)
+#define HM1246_MODE_SELECT_STANDBY 0x00
+#define HM1246_MODE_SELECT_STREAM 0x01
+#define HM1246_MODE_SELECT_STOP 0x02
+#define HM1246_IMAGE_ORIENTATION_REG CCI_REG8(0x0101)
+#define HM1246_IMAGE_ORIENTATION_VFLIP BIT(1)
+#define HM1246_IMAGE_ORIENTATION_HFLIP BIT(0)
+#define HM1246_CMU_UPDATE_REG CCI_REG8(0x0104)
+
+/* Output setup registers */
+#define HM1246_COARSE_INTG_REG CCI_REG16(0x0202)
+#define HM1246_ANALOG_GLOBAL_GAIN_REG CCI_REG8(0x0205)
+
+/* Clock setup registers */
+#define HM1246_PLL1CFG_REG CCI_REG8(0x0303)
+#define HM1246_PLL1CFG_MULTIPLIER(x) (((x) & 0xff) << 0)
+#define HM1246_PLL2CFG_REG CCI_REG8(0x0305)
+#define HM1246_PLL2CFG_PRE_DIV(x) (((x) & 0x1f) << 1)
+#define HM1246_PLL2CFG_MULTIPLIER(x) (((x) & 0x01) << 0)
+#define HM1246_PLL3CFG_REG CCI_REG8(0x0307)
+#define HM1246_PLL3CFG_POST_DIV(x) (((x) & 0x3) << 6)
+#define HM1246_PLL3CFG_SYSCLK_DIV(x) (((x) & 0x3) << 4)
+#define HM1246_PLL3CFG_PCLK_DIV(x) (((x) & 0x7) << 0)
+
+/* Frame timing registers */
+#define HM1246_FRAME_LENGTH_LINES_REG CCI_REG16(0x0340)
+#define HM1246_LINE_LENGTH_PCK_REG CCI_REG16(0x0342)
+
+/* Image size registers */
+#define HM1246_X_ADDR_START_REG CCI_REG16(0x0344)
+#define HM1246_Y_ADDR_START_REG CCI_REG16(0x0346)
+#define HM1246_X_ADDR_END_REG CCI_REG16(0x0348)
+#define HM1246_Y_ADDR_END_REG CCI_REG16(0x034a)
+#define HM1246_X_LA_START_REG CCI_REG16(0x0351)
+#define HM1246_X_LA_END_REG CCI_REG16(0x0353)
+#define HM1246_Y_LA_START_REG CCI_REG16(0x0355)
+#define HM1246_Y_LA_END_REG CCI_REG16(0x0357)
+
+/* Test pattern registers */
+#define HM1246_TEST_PATTERN_MODE_REG CCI_REG8(0x0601)
+#define HM1246_TEST_PATTERN_MODE_MODE(x) (((x) & 0xf) << 4)
+#define HM1246_TEST_PATTERN_MODE_ENABLE BIT(0)
+#define HM1246_TEST_DATA_BLUE_REG CCI_REG16(0x0602)
+#define HM1246_TEST_DATA_GB_REG CCI_REG16(0x0604)
+#define HM1246_TEST_DATA_RED_REG CCI_REG16(0x0606)
+#define HM1246_TEST_DATA_GR_REG CCI_REG16(0x0608)
+
+/* SBC registers */
+#define HM1246_SBC_BOOT_REF2_REG CCI_REG8(0x2001)
+#define HM1246_SBC_BOOT_REF2_PLL_LOCK BIT(4)
+#define HM1246_SBC_CTRL_REG CCI_REG8(0x2003)
+#define HM1246_SBC_CTRL_PLL_EN BIT(0)
+
+/* System registers */
+#define HM1246_OUTPUT_PRT_CTRL_REG CCI_REG8(0x2f02)
+#define HM1246_POLARITY_CTRL_REG CCI_REG8(0x2f20)
+#define HM1246_POLARITY_CTRL_HSYNC BIT(7)
+#define HM1246_POLARITY_CTRL_VSYNC BIT(6)
+#define HM1246_PCLK_CTRL_REG CCI_REG8(0x2f24)
+#define HM1246_PCLK_CTRL_POL BIT(3)
+
+/* Digital window control & parameter registers */
+#define HM1246_DWIN_XOFFSET_REG CCI_REG16(0xd5e4)
+#define HM1246_DWIN_XSIZE_REG CCI_REG16(0xd5e6)
+#define HM1246_DWIN_YOFFSET_REG CCI_REG16(0xd5e8)
+#define HM1246_DWIN_YSIZE_REG CCI_REG16(0xd5ea)
+
+#define HM1246_MODEL_ID 0x1245
+
+#define HM1246_NATIVE_WIDTH 1296
+#define HM1246_NATIVE_HEIGHT 976
+
+#define HM1246_VTS_MAX 65535
+
+#define HM1246_COARSE_INTG_MARGIN 2
+#define HM1246_COARSE_INTG_MIN 4
+#define HM1246_COARSE_INTG_STEP 1
+
+#define HM1246_ANALOG_GLOBAL_GAIN_MIN 0x00
+#define HM1246_ANALOG_GLOBAL_GAIN_MAX 0xe8
+#define HM1246_ANALOG_GLOBAL_GAIN_STEP 0x01
+
+#define HM1246_XCLK_MIN (6 * HZ_PER_MHZ)
+#define HM1246_XCLK_MAX (27 * HZ_PER_MHZ)
+
+#define HM1246_PCLK_MIN (8 * HZ_PER_MHZ)
+#define HM1246_PCLK_MAX (96 * HZ_PER_MHZ)
+
+#define HM1246_PLL_VCO_MIN (360 * HZ_PER_MHZ)
+#define HM1246_PLL_VCO_MAX (680 * HZ_PER_MHZ)
+
+#define HM1246_PLL_INCLK_MIN (1000 * HZ_PER_KHZ)
+#define HM1246_PLL_INCLK_MAX (2500 * HZ_PER_KHZ)
+
+#define HM1246_PLL_MULTI_L_MIN 1
+#define HM1246_PLL_MULTI_L_MAX 256
+
+#define HM1246_PLL_MULTI_H_MIN 2
+#define HM1246_PLL_MULTI_H_MAX 3
+
+#define HM1246_PLL_MULTI_MIN \
+ (HM1246_PLL_MULTI_H_MIN * HM1246_PLL_MULTI_L_MIN)
+#define HM1246_PLL_MULTI_MAX \
+ (HM1246_PLL_MULTI_H_MAX * HM1246_PLL_MULTI_L_MAX)
+
+static const char *const hm1246_test_pattern_menu[] = {
+ "Disabled",
+ "Checkboard",
+ "Ramp",
+ "Moving ones",
+ "Blending color bars",
+ "Color bars",
+ "Solid white",
+ "Solid black",
+ "Solid red",
+ "Solid green",
+ "Solid blue",
+};
+
+static const char *const hm1246_supply_names[] = {
+ "avdd",
+ "iovdd",
+ "dvdd",
+};
+
+struct hm1246 {
+ struct v4l2_subdev sd;
+ struct media_pad pad;
+ struct device *dev;
+
+ struct regulator_bulk_data supplies[ARRAY_SIZE(hm1246_supply_names)];
+ struct clk *xclk;
+ unsigned long xclk_freq;
+ struct reset_control *reset;
+ unsigned int mbus_flags;
+ s64 link_frequency;
+
+ struct v4l2_ctrl_handler ctrls;
+ struct v4l2_ctrl *exposure_ctrl;
+ struct v4l2_ctrl *hflip_ctrl;
+ struct v4l2_ctrl *vflip_ctrl;
+
+ struct regmap *regmap;
+
+ bool identified;
+};
+
+static const struct cci_reg_sequence mode_1296x976_raw[] = {
+ { HM1246_X_LA_START_REG, 60 },
+ { HM1246_X_LA_END_REG, 1355 },
+ { HM1246_Y_LA_START_REG, 0 },
+ { HM1246_Y_LA_END_REG, 975 },
+ { HM1246_OUTPUT_PRT_CTRL_REG, 0x20 },
+ { CCI_REG8(0x300a), 0x01 },
+ { CCI_REG8(0x300b), 0x00 },
+ { CCI_REG8(0x50f5), 0x01 },
+ { CCI_REG8(0x50dd), 0x00 },
+ { CCI_REG8(0x50a1), 0x02 },
+ { CCI_REG8(0x50aa), 0x1c },
+ { CCI_REG8(0x50ac), 0xdd },
+ { CCI_REG8(0x50ad), 0x08 },
+ { CCI_REG8(0x50ab), 0x04 },
+ { CCI_REG8(0x50a0), 0x40 },
+ { CCI_REG8(0x50a2), 0x12 },
+ { CCI_REG8(0x50ae), 0x30 },
+ { CCI_REG8(0x50b3), 0x04 },
+ { CCI_REG8(0x5204), 0x40 },
+ { CCI_REG8(0x5208), 0x55 },
+ { CCI_REG8(0x520b), 0x05 },
+ { CCI_REG8(0x520d), 0x40 },
+ { CCI_REG8(0x5214), 0x18 },
+ { CCI_REG8(0x5215), 0x0f },
+ { CCI_REG8(0x5217), 0x01 },
+ { CCI_REG8(0x5218), 0x07 },
+ { CCI_REG8(0x5219), 0x01 },
+ { CCI_REG8(0x521a), 0x50 },
+ { CCI_REG8(0x521b), 0x24 },
+ { CCI_REG8(0x5232), 0x01 },
+ { CCI_REG8(0x5220), 0x11 },
+ { CCI_REG8(0x5227), 0x01 },
+ { CCI_REG8(0x5106), 0xc1 },
+ { CCI_REG8(0x5115), 0xc0 },
+ { CCI_REG8(0x5116), 0xc1 },
+ { CCI_REG8(0x5138), 0x40 },
+ { CCI_REG8(0x5139), 0x60 },
+ { CCI_REG8(0x513a), 0x80 },
+ { CCI_REG8(0x513b), 0xa0 },
+ { CCI_REG8(0x513c), 0xa1 },
+ { CCI_REG8(0x513d), 0xa2 },
+ { CCI_REG8(0x513e), 0xa3 },
+ { CCI_REG8(0x5140), 0x40 },
+ { CCI_REG8(0x5141), 0x60 },
+ { CCI_REG8(0x5142), 0x80 },
+ { CCI_REG8(0x5143), 0x81 },
+ { CCI_REG8(0x5144), 0x82 },
+ { CCI_REG8(0x5145), 0x83 },
+ { CCI_REG8(0x5146), 0x93 },
+ { CCI_REG8(0x51c1), 0xc3 },
+ { CCI_REG8(0x51c5), 0xc3 },
+ { CCI_REG8(0x51c9), 0xc3 },
+ { CCI_REG8(0x51cd), 0xc2 },
+ { CCI_REG8(0x51d1), 0xc1 },
+ { CCI_REG8(0x51d5), 0xc1 },
+ { CCI_REG8(0x51d9), 0x81 },
+ { CCI_REG8(0x51dd), 0x81 },
+ { CCI_REG8(0x51c2), 0x49 },
+ { CCI_REG8(0x51c6), 0x49 },
+ { CCI_REG8(0x51ca), 0x49 },
+ { CCI_REG8(0x51ce), 0x49 },
+ { CCI_REG8(0x51d2), 0x49 },
+ { CCI_REG8(0x51d6), 0x59 },
+ { CCI_REG8(0x51da), 0x59 },
+ { CCI_REG8(0x51de), 0x59 },
+ { CCI_REG8(0x51c3), 0x20 },
+ { CCI_REG8(0x51c7), 0x38 },
+ { CCI_REG8(0x51cb), 0x21 },
+ { CCI_REG8(0x51cf), 0x11 },
+ { CCI_REG8(0x51d3), 0x11 },
+ { CCI_REG8(0x51d7), 0x13 },
+ { CCI_REG8(0x51db), 0x13 },
+ { CCI_REG8(0x51df), 0x13 },
+ { CCI_REG8(0x51e0), 0x03 },
+ { CCI_REG8(0x51e2), 0x03 },
+ { CCI_REG8(0x51f0), 0x42 },
+ { CCI_REG8(0x51f1), 0x40 },
+ { CCI_REG8(0x51f2), 0x4a },
+ { CCI_REG8(0x51f3), 0x48 },
+ { CCI_REG8(0x5015), 0x73 },
+ { CCI_REG8(0x504a), 0x04 },
+ { CCI_REG8(0x5044), 0x07 },
+ { CCI_REG8(0x5040), 0x03 },
+ { CCI_REG8(0x5135), 0xc4 },
+ { CCI_REG8(0x5136), 0xc5 },
+ { CCI_REG8(0x5166), 0xc4 },
+ { CCI_REG8(0x5196), 0xc4 },
+ { CCI_REG8(0x51c0), 0x10 },
+ { CCI_REG8(0x51c4), 0x10 },
+ { CCI_REG8(0x51c8), 0xa0 },
+ { CCI_REG8(0x51cc), 0xa0 },
+ { CCI_REG8(0x51d0), 0xa1 },
+ { CCI_REG8(0x51d4), 0xa5 },
+ { CCI_REG8(0x51d8), 0xa5 },
+ { CCI_REG8(0x51dc), 0xa5 },
+ { CCI_REG8(0x5200), 0xe4 },
+ { CCI_REG8(0x5209), 0x04 },
+ { CCI_REG8(0x301b), 0x01 },
+ { CCI_REG8(0x3130), 0x01 },
+ { CCI_REG8(0x5013), 0x07 },
+ { CCI_REG8(0x5016), 0x01 },
+ { CCI_REG8(0x501d), 0x50 },
+ { CCI_REG8(0x0350), 0xfe },
+ { CCI_REG8(0x2f03), 0x15 },
+ { CCI_REG8(0xd380), 0x00 },
+ { CCI_REG8(0x3047), 0x7f },
+ { CCI_REG8(0x304d), 0x34 },
+ { CCI_REG8(0x3041), 0x4b },
+ { CCI_REG8(0x3042), 0x2d },
+ { CCI_REG8(0x3056), 0x64 },
+ { CCI_REG8(0x3059), 0x1e },
+ { CCI_REG8(0x305e), 0x10 },
+ { CCI_REG8(0x305f), 0x10 },
+ { CCI_REG8(0x306d), 0x10 },
+ { CCI_REG8(0x306e), 0x0c },
+ { CCI_REG8(0x3064), 0x50 },
+ { CCI_REG8(0x3067), 0x78 },
+ { CCI_REG8(0x3068), 0x4b },
+ { CCI_REG8(0x306a), 0x78 },
+ { CCI_REG8(0x306b), 0x4b },
+ { CCI_REG8(0xd442), 0x3d },
+ { CCI_REG8(0xd443), 0x06 },
+ { CCI_REG8(0xd440), 0x63 },
+ { CCI_REG8(0xd446), 0xb0 },
+ { CCI_REG8(0xd447), 0x60 },
+ { CCI_REG8(0xd448), 0x48 },
+ { CCI_REG8(0xd449), 0x30 },
+ { CCI_REG8(0xd44a), 0x18 },
+ { CCI_REG8(0xd360), 0x03 },
+ { CCI_REG8(0x30ac), 0x10 },
+ { CCI_REG8(0x30ad), 0x10 },
+ { CCI_REG8(0x30ae), 0x10 },
+ { CCI_REG8(0x3040), 0x0b },
+ { CCI_REG8(0x2002), 0x00 },
+ { CCI_REG8(0x2000), 0x08 },
+};
+
+struct hm1246_reg_list {
+ u32 num_of_regs;
+ const struct cci_reg_sequence *regs;
+};
+
+struct hm1246_mode {
+ u32 codes[4];
+ u32 clocks_per_pixel;
+ struct v4l2_rect rect;
+ u32 hts;
+ u32 vts_min;
+ const struct hm1246_reg_list reg_list;
+};
+
+#define FLIP_FORMAT_INDEX(v, h) ((v ? 2 : 0) | (h ? 1 : 0))
+
+/* Get the format code of the mode considering current flip setting. */
+static u32 hm1246_get_format_code(struct hm1246 *hm1246,
+ const struct hm1246_mode *hm1246_mode)
+{
+ return hm1246_mode->codes[FLIP_FORMAT_INDEX(hm1246->vflip_ctrl->val,
+ hm1246->hflip_ctrl->val)];
+}
+
+static const struct hm1246_mode hm1246_modes[] = {
+ {
+ .codes = {
+ [FLIP_FORMAT_INDEX(0, 0)] = MEDIA_BUS_FMT_SBGGR10_1X10,
+ [FLIP_FORMAT_INDEX(0, 1)] = MEDIA_BUS_FMT_SGBRG10_1X10,
+ [FLIP_FORMAT_INDEX(1, 0)] = MEDIA_BUS_FMT_SGRBG10_1X10,
+ [FLIP_FORMAT_INDEX(1, 1)] = MEDIA_BUS_FMT_SRGGB10_1X10,
+ },
+ .clocks_per_pixel = 1,
+ .rect.top = 0,
+ .rect.left = 0,
+ .rect.width = 1296,
+ .rect.height = 976,
+ .hts = 1420,
+ .vts_min = 990,
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(mode_1296x976_raw),
+ .regs = mode_1296x976_raw,
+ },
+ },
+};
+
+static inline struct hm1246 *to_hm1246(struct v4l2_subdev *sd)
+{
+ return container_of_const(sd, struct hm1246, sd);
+}
+
+static const struct hm1246_mode *
+hm1246_find_mode_by_mbus_code(struct hm1246 *hm1246, u32 code)
+{
+ for (unsigned int i = 0; i < ARRAY_SIZE(hm1246_modes); i++) {
+ if (code == hm1246_get_format_code(hm1246, &hm1246_modes[i]))
+ return &hm1246_modes[i];
+ }
+
+ return NULL;
+}
+
+static int hm1246_power_on(struct device *dev)
+{
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct hm1246 *hm1246 = to_hm1246(sd);
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(hm1246_supply_names),
+ hm1246->supplies);
+ if (ret) {
+ dev_err(hm1246->dev, "failed to enable regulators\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(hm1246->xclk);
+ if (ret) {
+ regulator_bulk_disable(ARRAY_SIZE(hm1246_supply_names),
+ hm1246->supplies);
+ dev_err(hm1246->dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ reset_control_deassert(hm1246->reset);
+
+ /*
+ * XSHUTDOWN to crystal clock oscillation (tcrystal): 650us (typical)
+ * Sample bootstrap pin (tsample): 2000us (maximum)
+ * Built in self test (tbist): 3000us (maximum)
+ */
+ fsleep(6 * USEC_PER_MSEC);
+
+ return 0;
+}
+
+static int hm1246_power_off(struct device *dev)
+{
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct hm1246 *hm1246 = to_hm1246(sd);
+
+ reset_control_assert(hm1246->reset);
+
+ clk_disable_unprepare(hm1246->xclk);
+
+ regulator_bulk_disable(ARRAY_SIZE(hm1246_supply_names),
+ hm1246->supplies);
+
+ return 0;
+}
+
+static int hm1246_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct hm1246 *hm1246 = to_hm1246(sd);
+
+ if (code->index >= ARRAY_SIZE(hm1246_modes))
+ return -EINVAL;
+
+ code->code = hm1246_get_format_code(hm1246, &hm1246_modes[code->index]);
+
+ return 0;
+}
+
+static int hm1246_enum_frame_size(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ struct hm1246 *hm1246 = to_hm1246(subdev);
+ const struct hm1246_mode *mode;
+
+ if (fse->index > 0)
+ return -EINVAL;
+
+ mode = hm1246_find_mode_by_mbus_code(hm1246, fse->code);
+ if (!mode)
+ return -EINVAL;
+
+ fse->min_width = mode->rect.width;
+ fse->max_width = mode->rect.width;
+ fse->min_height = mode->rect.height;
+ fse->max_height = mode->rect.height;
+
+ return 0;
+}
+
+static void hm1246_update_pad_format(struct hm1246 *hm1246,
+ const struct hm1246_mode *hm1246_mode,
+ struct v4l2_mbus_framefmt *fmt)
+{
+ fmt->width = hm1246_mode->rect.width;
+ fmt->height = hm1246_mode->rect.height;
+ fmt->code = hm1246_get_format_code(hm1246, hm1246_mode);
+ fmt->field = V4L2_FIELD_NONE;
+ fmt->colorspace = V4L2_COLORSPACE_RAW;
+ fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
+ fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+ fmt->xfer_func = V4L2_XFER_FUNC_NONE;
+}
+
+static int hm1246_set_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct hm1246 *hm1246 = to_hm1246(sd);
+ struct v4l2_mbus_framefmt *mbus_fmt;
+ struct v4l2_rect *crop;
+ const struct hm1246_mode *mode;
+
+ mode = hm1246_find_mode_by_mbus_code(hm1246, fmt->format.code);
+ if (!mode)
+ mode = &hm1246_modes[0];
+
+ crop = v4l2_subdev_state_get_crop(state, 0);
+ *crop = mode->rect;
+
+ hm1246_update_pad_format(hm1246, mode, &fmt->format);
+ mbus_fmt = v4l2_subdev_state_get_format(state, 0);
+ *mbus_fmt = fmt->format;
+
+ return 0;
+}
+
+static int hm1246_get_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_selection *sel)
+{
+ const struct v4l2_mbus_framefmt *format;
+ const struct hm1246_mode *mode;
+
+ format = v4l2_subdev_state_get_format(state, 0);
+ mode = v4l2_find_nearest_size(hm1246_modes, ARRAY_SIZE(hm1246_modes),
+ rect.width, rect.height, format->width,
+ format->height);
+
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+ sel->r = *v4l2_subdev_state_get_crop(state, 0);
+ return 0;
+
+ case V4L2_SEL_TGT_NATIVE_SIZE:
+ sel->r.top = 0;
+ sel->r.left = 0;
+ sel->r.width = HM1246_NATIVE_WIDTH;
+ sel->r.height = HM1246_NATIVE_HEIGHT;
+ return 0;
+
+ case V4L2_SEL_TGT_CROP_DEFAULT:
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ sel->r = mode->rect;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int hm1246_init_state(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state)
+{
+ struct hm1246 *hm1246 = to_hm1246(sd);
+ struct v4l2_subdev_format fmt = {
+ .which = V4L2_SUBDEV_FORMAT_TRY,
+ .pad = 0,
+ .format = {
+ .code = hm1246_get_format_code(hm1246,
+ &hm1246_modes[0]),
+ .width = hm1246_modes[0].rect.width,
+ .height = hm1246_modes[0].rect.height,
+ },
+ };
+
+ hm1246_set_format(sd, state, &fmt);
+
+ return 0;
+}
+
+static int hm1246_calc_pll(u32 xclk, u32 link_freq, u32 clocks_per_pixel,
+ u8 *pll1, u8 *pll2, u8 *pll3)
+{
+ static const u8 pclk_div_table[] = { 4, 5, 6, 7, 8, 12, 14, 16 };
+ static const u8 sysclk_div_table[] = { 1, 2, 3, 4 };
+ static const u8 post_div_table[] = { 1, 2, 4, 8 };
+ static const int sysclk_pclk_ratio = 3; /* Recommended value */
+ u32 pclk, vco_out;
+ int pclk_div_index, sysclk_div_index, post_div_index;
+ bool sysclk_pclk_ratio_found = false;
+
+ if (link_freq < HM1246_PCLK_MIN || link_freq > HM1246_PCLK_MAX)
+ return -EINVAL;
+
+ /*
+ * In raw mode (1 pixel per clock) the pixel clock is internally
+ * divided by two.
+ */
+ pclk = 2 * link_freq / clocks_per_pixel;
+
+ /* Find suitable PCLK and SYSCLK dividers. */
+ for (pclk_div_index = 0; pclk_div_index < ARRAY_SIZE(pclk_div_table);
+ pclk_div_index++) {
+ for (sysclk_div_index = 0;
+ sysclk_div_index < ARRAY_SIZE(sysclk_div_table);
+ sysclk_div_index++) {
+ if (sysclk_div_table[sysclk_div_index] *
+ sysclk_pclk_ratio ==
+ pclk_div_table[pclk_div_index]) {
+ sysclk_pclk_ratio_found = true;
+ break;
+ }
+ }
+ if (sysclk_pclk_ratio_found)
+ break;
+ }
+
+ if (!sysclk_pclk_ratio_found)
+ return -EINVAL;
+
+ /* Determine an appropriate post divider. */
+ for (post_div_index = 0; post_div_index < ARRAY_SIZE(post_div_table);
+ post_div_index++) {
+ vco_out = pclk * pclk_div_table[pclk_div_index] *
+ post_div_table[post_div_index];
+
+ if (vco_out >= HM1246_PLL_VCO_MIN &&
+ vco_out <= HM1246_PLL_VCO_MAX)
+ break;
+ }
+ if (post_div_index >= ARRAY_SIZE(post_div_table))
+ return -EINVAL;
+
+ /* Find pre-divider and multiplier values. */
+ for (u32 div = DIV_ROUND_UP(xclk, HM1246_PLL_INCLK_MAX);
+ div <= xclk / HM1246_PLL_INCLK_MIN; div++) {
+ u32 multi, multi_h, multi_l, vco;
+
+ multi = DIV_ROUND_CLOSEST_ULL((u64)vco_out * div, xclk);
+ if (multi < HM1246_PLL_MULTI_MIN ||
+ multi > HM1246_PLL_MULTI_MAX)
+ continue;
+
+ multi_h = multi / (HM1246_PLL_MULTI_H_MIN *
+ HM1246_PLL_MULTI_L_MAX) +
+ 2;
+ multi_l = multi / multi_h;
+ vco = div_u64((u64)xclk * multi_h * multi_l, div);
+
+ if (vco != vco_out)
+ continue;
+
+ if (pll1 && pll2 && pll3) {
+ *pll1 = HM1246_PLL1CFG_MULTIPLIER(multi_l - 1);
+ *pll2 = HM1246_PLL2CFG_PRE_DIV(div - 1) |
+ HM1246_PLL2CFG_MULTIPLIER(multi_h - 2);
+ *pll3 = HM1246_PLL3CFG_POST_DIV(post_div_index) |
+ HM1246_PLL3CFG_SYSCLK_DIV(sysclk_div_index) |
+ HM1246_PLL3CFG_PCLK_DIV(pclk_div_index);
+ }
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int hm1246_cci_write_pll(struct hm1246 *hm1246, u8 pll1, u8 pll2,
+ u8 pll3)
+{
+ const struct cci_reg_sequence pll_regs[] = {
+ { HM1246_PLL1CFG_REG, pll1 },
+ { HM1246_PLL2CFG_REG, pll2 },
+ { HM1246_PLL3CFG_REG, pll3 },
+ { HM1246_SBC_CTRL_REG, HM1246_SBC_CTRL_PLL_EN },
+ };
+
+ return cci_multi_reg_write(hm1246->regmap, pll_regs,
+ ARRAY_SIZE(pll_regs), NULL);
+}
+
+static int hm1246_pll_check_locked(struct hm1246 *hm1246)
+{
+ u64 boot_ref2;
+ int ret;
+
+ ret = cci_read(hm1246->regmap, HM1246_SBC_BOOT_REF2_REG, &boot_ref2,
+ NULL);
+ if (ret)
+ return ret;
+
+ return (boot_ref2 & HM1246_SBC_BOOT_REF2_PLL_LOCK) ? 0 : -EIO;
+}
+
+static int hm1246_setup_pll(struct hm1246 *hm1246,
+ const struct hm1246_mode *mode)
+{
+ u8 pll1, pll2, pll3;
+ int ret;
+
+ ret = hm1246_calc_pll(hm1246->xclk_freq, hm1246->link_frequency,
+ mode->clocks_per_pixel, &pll1, &pll2, &pll3);
+ if (ret)
+ return ret;
+
+ ret = hm1246_cci_write_pll(hm1246, pll1, pll2, pll3);
+ if (ret)
+ return ret;
+
+ /* PLL lock time (tpll): 100us (typical) */
+ fsleep(200);
+
+ return hm1246_pll_check_locked(hm1246);
+}
+
+static int hm1246_cci_write_test_pattern(struct hm1246 *hm1246, u8 mode,
+ u16 r, u16 g, u16 b)
+{
+ const struct cci_reg_sequence tpg_enable_regs[] = {
+ { HM1246_TEST_DATA_RED_REG, r },
+ { HM1246_TEST_DATA_GR_REG, g },
+ { HM1246_TEST_DATA_GB_REG, g },
+ { HM1246_TEST_DATA_BLUE_REG, b },
+ { HM1246_TEST_PATTERN_MODE_REG, mode },
+ };
+
+ return cci_multi_reg_write(hm1246->regmap, tpg_enable_regs,
+ ARRAY_SIZE(tpg_enable_regs), NULL);
+}
+
+static int hm1246_test_pattern(struct hm1246 *hm1246, u32 index)
+{
+ static const u16 RGBMIN = 0, RGBMAX = 0x3ff;
+ static const struct tp {
+ int pattern;
+ u16 r, g, b;
+ } tps[] = {
+ /* Disabled */
+ [0] = { .pattern = 0, .r = RGBMIN, .g = RGBMIN, .b = RGBMIN },
+ /* Checkboard pattern */
+ [1] = { .pattern = 0, .r = RGBMIN, .g = RGBMIN, .b = RGBMIN },
+ /* Ramp */
+ [2] = { .pattern = 1, .r = RGBMIN, .g = RGBMIN, .b = RGBMIN },
+ /* Moving ones */
+ [3] = { .pattern = 2, .r = RGBMIN, .g = RGBMIN, .b = RGBMIN },
+ /* Blending color bars */
+ [4] = { .pattern = 3, .r = RGBMIN, .g = RGBMIN, .b = RGBMIN },
+ /* Color bars */
+ [5] = { .pattern = 4, .r = RGBMIN, .g = RGBMIN, .b = RGBMIN },
+ /* Solid white */
+ [6] = { .pattern = 15, .r = RGBMAX, .g = RGBMAX, .b = RGBMAX },
+ /* Solid black */
+ [7] = { .pattern = 15, .r = RGBMIN, .g = RGBMIN, .b = RGBMIN },
+ /* Solid red */
+ [8] = { .pattern = 15, .r = RGBMAX, .g = RGBMIN, .b = RGBMIN },
+ /* Solid green */
+ [9] = { .pattern = 15, .r = RGBMIN, .g = RGBMAX, .b = RGBMIN },
+ /* Solid blue */
+ [10] = { .pattern = 15, .r = RGBMIN, .g = RGBMIN, .b = RGBMAX },
+ };
+ u8 mode;
+
+ if (index >= ARRAY_SIZE(tps))
+ return -EINVAL;
+
+ mode = HM1246_TEST_PATTERN_MODE_MODE(tps[index].pattern);
+ if (index)
+ mode |= HM1246_TEST_PATTERN_MODE_ENABLE;
+
+ return hm1246_cci_write_test_pattern(hm1246, mode, tps[index].r,
+ tps[index].g, tps[index].b);
+}
+
+static int hm1246_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct hm1246 *hm1246 =
+ container_of_const(ctrl->handler, struct hm1246, ctrls);
+ struct v4l2_subdev_state *state;
+ const struct v4l2_mbus_framefmt *format;
+ u32 val;
+ bool needs_cmu_update = true;
+ int ret;
+
+ state = v4l2_subdev_get_locked_active_state(&hm1246->sd);
+ format = v4l2_subdev_state_get_format(state, 0);
+
+ if (ctrl->id == V4L2_CID_VBLANK) {
+ s64 exposure_max;
+
+ exposure_max =
+ format->height + ctrl->val - HM1246_COARSE_INTG_MARGIN;
+ ret = __v4l2_ctrl_modify_range(hm1246->exposure_ctrl,
+ hm1246->exposure_ctrl->minimum,
+ exposure_max,
+ hm1246->exposure_ctrl->step,
+ exposure_max);
+
+ if (ret) {
+ dev_err(hm1246->dev, "exposure ctrl range update failed\n");
+ return ret;
+ }
+ }
+
+ if (!pm_runtime_get_if_active(hm1246->dev))
+ return 0;
+
+ ret = 0;
+ switch (ctrl->id) {
+ case V4L2_CID_EXPOSURE:
+ cci_write(hm1246->regmap, HM1246_COARSE_INTG_REG, ctrl->val,
+ &ret);
+ break;
+
+ case V4L2_CID_ANALOGUE_GAIN:
+ cci_write(hm1246->regmap, HM1246_ANALOG_GLOBAL_GAIN_REG,
+ ctrl->val, &ret);
+ break;
+
+ case V4L2_CID_VBLANK:
+ val = format->height + ctrl->val;
+ cci_write(hm1246->regmap, HM1246_FRAME_LENGTH_LINES_REG, val,
+ &ret);
+ break;
+
+ case V4L2_CID_HFLIP:
+ case V4L2_CID_VFLIP:
+ val = 0;
+ if (hm1246->hflip_ctrl->val)
+ val |= HM1246_IMAGE_ORIENTATION_HFLIP;
+ if (hm1246->vflip_ctrl->val)
+ val |= HM1246_IMAGE_ORIENTATION_VFLIP;
+
+ cci_write(hm1246->regmap, HM1246_IMAGE_ORIENTATION_REG, val,
+ &ret);
+ break;
+
+ case V4L2_CID_TEST_PATTERN:
+ ret = hm1246_test_pattern(hm1246, ctrl->val);
+ needs_cmu_update = false;
+ break;
+
+ default:
+ ret = -EINVAL;
+ needs_cmu_update = false;
+ break;
+ }
+
+ if (needs_cmu_update)
+ cci_write(hm1246->regmap, HM1246_CMU_UPDATE_REG, 0, &ret);
+
+ pm_runtime_put(hm1246->dev);
+
+ return ret;
+}
+
+static const struct v4l2_ctrl_ops hm1246_ctrl_ops = {
+ .s_ctrl = hm1246_set_ctrl,
+};
+
+static int hm1246_identify_module(struct hm1246 *hm1246)
+{
+ u64 model_id;
+ int ret;
+
+ if (hm1246->identified)
+ return 0;
+
+ ret = cci_read(hm1246->regmap, HM1246_MODEL_ID_REG, &model_id, NULL);
+ if (ret)
+ return ret;
+
+ if (model_id != HM1246_MODEL_ID) {
+ dev_err(hm1246->dev, "model id mismatch: 0x%llx!=0x%x\n",
+ model_id, HM1246_MODEL_ID);
+ return -ENXIO;
+ }
+
+ hm1246->identified = true;
+
+ return 0;
+}
+
+static int hm1246_setup_moderegs(struct hm1246 *hm1246,
+ const struct hm1246_mode *mode)
+{
+ const struct hm1246_reg_list *reg_list = &mode->reg_list;
+ const struct cci_reg_sequence modeaw[] = {
+ { HM1246_X_ADDR_START_REG, mode->rect.left },
+ { HM1246_Y_ADDR_START_REG, mode->rect.top },
+ { HM1246_X_ADDR_END_REG, mode->rect.width - 1 },
+ { HM1246_Y_ADDR_END_REG, mode->rect.height - 1 },
+ { HM1246_DWIN_XOFFSET_REG, mode->rect.left },
+ { HM1246_DWIN_YOFFSET_REG, mode->rect.top },
+ { HM1246_DWIN_XSIZE_REG, mode->rect.width },
+ { HM1246_DWIN_YSIZE_REG, mode->rect.height },
+ { HM1246_LINE_LENGTH_PCK_REG, mode->hts },
+ };
+ int ret = 0;
+
+ cci_multi_reg_write(hm1246->regmap, modeaw, ARRAY_SIZE(modeaw), &ret);
+ cci_multi_reg_write(hm1246->regmap, reg_list->regs,
+ reg_list->num_of_regs, &ret);
+
+ return ret;
+}
+
+static int hm1246_setup_bus(struct hm1246 *hm1246)
+{
+ u64 polarity_ctrl = 0, pclk_ctrl = 0;
+ int ret = 0;
+
+ if (hm1246->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
+ polarity_ctrl |= HM1246_POLARITY_CTRL_HSYNC;
+
+ if (hm1246->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
+ polarity_ctrl |= HM1246_POLARITY_CTRL_VSYNC;
+
+ cci_write(hm1246->regmap, HM1246_POLARITY_CTRL_REG, polarity_ctrl,
+ &ret);
+
+ /*
+ * If the clock output polarity flag PCLK_CTRL[3] is set (high), the
+ * data lines change state on the falling edge of PCLK and should
+ * therefore be sampled on the rising edge.
+ * This is different than described in the data sheet.
+ */
+ if (hm1246->mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
+ pclk_ctrl |= HM1246_PCLK_CTRL_POL;
+
+ cci_write(hm1246->regmap, HM1246_PCLK_CTRL_REG, pclk_ctrl, &ret);
+
+ return ret;
+}
+
+static int hm1246_enable_streams(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state, u32 pad,
+ u64 streams_mask)
+{
+ struct hm1246 *hm1246 = to_hm1246(sd);
+ const struct v4l2_mbus_framefmt *format;
+ const struct hm1246_mode *mode;
+ int ret;
+
+ format = v4l2_subdev_state_get_format(state, 0);
+ mode = v4l2_find_nearest_size(hm1246_modes, ARRAY_SIZE(hm1246_modes),
+ rect.width, rect.height, format->width,
+ format->height);
+
+ ret = pm_runtime_resume_and_get(hm1246->dev);
+ if (ret)
+ return ret;
+
+ ret = hm1246_identify_module(hm1246);
+ if (ret)
+ goto err_rpm_put;
+
+ ret = hm1246_setup_pll(hm1246, mode);
+ if (ret) {
+ dev_err(hm1246->dev, "failed to setup PLL\n");
+ goto err_rpm_put;
+ }
+
+ ret = hm1246_setup_moderegs(hm1246, mode);
+ if (ret)
+ goto err_rpm_put;
+
+ ret = hm1246_setup_bus(hm1246);
+ if (ret)
+ goto err_rpm_put;
+
+ ret = __v4l2_ctrl_handler_setup(&hm1246->ctrls);
+ if (ret) {
+ dev_err(hm1246->dev, "failed to setup v4l2 controls\n");
+ goto err_rpm_put;
+ }
+
+ ret = cci_write(hm1246->regmap, HM1246_MODE_SELECT_REG,
+ HM1246_MODE_SELECT_STREAM, NULL);
+ if (ret)
+ goto err_rpm_put;
+
+ /*
+ * Since mirroring may change the actual pixel format, it must not be
+ * changed during streaming.
+ */
+ __v4l2_ctrl_grab(hm1246->vflip_ctrl, true);
+ __v4l2_ctrl_grab(hm1246->hflip_ctrl, true);
+
+ return 0;
+
+err_rpm_put:
+ pm_runtime_put_autosuspend(hm1246->dev);
+
+ return ret;
+}
+
+static int hm1246_disable_streams(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state, u32 pad,
+ u64 streams_mask)
+{
+ struct hm1246 *hm1246 = to_hm1246(sd);
+ int ret;
+
+ ret = cci_write(hm1246->regmap, HM1246_MODE_SELECT_REG,
+ HM1246_MODE_SELECT_STANDBY, NULL);
+
+ __v4l2_ctrl_grab(hm1246->vflip_ctrl, false);
+ __v4l2_ctrl_grab(hm1246->hflip_ctrl, false);
+
+ pm_runtime_put_autosuspend(hm1246->dev);
+
+ return ret;
+}
+
+static const struct v4l2_subdev_video_ops hm1246_video_ops = {
+ .s_stream = v4l2_subdev_s_stream_helper,
+};
+
+static const struct v4l2_subdev_pad_ops hm1246_subdev_pad_ops = {
+ .enum_mbus_code = hm1246_enum_mbus_code,
+ .enum_frame_size = hm1246_enum_frame_size,
+ .get_fmt = v4l2_subdev_get_fmt,
+ .set_fmt = hm1246_set_format,
+ .get_selection = hm1246_get_selection,
+ .enable_streams = hm1246_enable_streams,
+ .disable_streams = hm1246_disable_streams,
+};
+
+static const struct v4l2_subdev_ops hm1246_subdev_ops = {
+ .video = &hm1246_video_ops,
+ .pad = &hm1246_subdev_pad_ops,
+};
+
+static const struct v4l2_subdev_internal_ops hm1246_internal_ops = {
+ .init_state = hm1246_init_state,
+};
+
+static int hm1246_get_regulators(struct device *dev, struct hm1246 *hm1246)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(hm1246_supply_names); i++)
+ hm1246->supplies[i].supply = hm1246_supply_names[i];
+
+ return devm_regulator_bulk_get(dev, ARRAY_SIZE(hm1246_supply_names),
+ hm1246->supplies);
+}
+
+static int hm1246_parse_fwnode(struct hm1246 *hm1246)
+{
+ struct fwnode_handle *endpoint;
+ struct v4l2_fwnode_endpoint bus_cfg = {
+ .bus_type = V4L2_MBUS_PARALLEL,
+ };
+ int ret;
+
+ endpoint = fwnode_graph_get_endpoint_by_id(dev_fwnode(hm1246->dev),
+ 0, 0,
+ FWNODE_GRAPH_ENDPOINT_NEXT);
+ if (!endpoint)
+ return dev_err_probe(hm1246->dev, -EINVAL,
+ "missing endpoint node\n");
+
+ ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
+ fwnode_handle_put(endpoint);
+ if (ret)
+ return dev_err_probe(hm1246->dev, ret,
+ "parsing endpoint node failed\n");
+
+ hm1246->mbus_flags = bus_cfg.bus.parallel.flags;
+
+ if (bus_cfg.nr_of_link_frequencies == 1)
+ hm1246->link_frequency = bus_cfg.link_frequencies[0];
+
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+
+ if (!hm1246->link_frequency)
+ return dev_err_probe(hm1246->dev, -EINVAL,
+ "one link frequency expected\n");
+
+ return 0;
+}
+
+static int hm1246_init_controls(struct hm1246 *hm1246)
+{
+ const struct hm1246_mode *mode = &hm1246_modes[0];
+ struct v4l2_fwnode_device_properties props;
+ struct v4l2_ctrl_handler *ctrl_hdlr = &hm1246->ctrls;
+ struct v4l2_ctrl *ctrl;
+ s64 pixel_rate, exposure_max, vblank_min, hblank;
+ int ret;
+
+ ret = v4l2_fwnode_device_parse(hm1246->dev, &props);
+ if (ret)
+ return ret;
+
+ v4l2_ctrl_handler_init(ctrl_hdlr, 11);
+
+ hm1246->hflip_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &hm1246_ctrl_ops,
+ V4L2_CID_HFLIP, 0, 1, 1, 0);
+ if (hm1246->hflip_ctrl)
+ hm1246->hflip_ctrl->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
+
+ hm1246->vflip_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &hm1246_ctrl_ops,
+ V4L2_CID_VFLIP, 0, 1, 1, 0);
+ if (hm1246->vflip_ctrl)
+ hm1246->vflip_ctrl->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
+
+ v4l2_ctrl_cluster(2, &hm1246->hflip_ctrl);
+
+ ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr, &hm1246_ctrl_ops,
+ V4L2_CID_LINK_FREQ,
+ 0, 0,
+ &hm1246->link_frequency);
+ if (ctrl)
+ ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ pixel_rate = div_u64(hm1246->link_frequency, mode->clocks_per_pixel);
+ ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &hm1246_ctrl_ops,
+ V4L2_CID_PIXEL_RATE,
+ pixel_rate, pixel_rate, 1,
+ pixel_rate);
+
+ vblank_min = mode->vts_min - mode->rect.height;
+ ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &hm1246_ctrl_ops,
+ V4L2_CID_VBLANK, vblank_min,
+ HM1246_VTS_MAX - mode->rect.height,
+ 1, vblank_min);
+
+ hblank = mode->hts - mode->rect.width;
+ ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &hm1246_ctrl_ops,
+ V4L2_CID_HBLANK, hblank, hblank,
+ 1, hblank);
+ if (ctrl)
+ ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ v4l2_ctrl_new_std(ctrl_hdlr, &hm1246_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
+ HM1246_ANALOG_GLOBAL_GAIN_MIN,
+ HM1246_ANALOG_GLOBAL_GAIN_MAX,
+ HM1246_ANALOG_GLOBAL_GAIN_STEP,
+ HM1246_ANALOG_GLOBAL_GAIN_MIN);
+
+ exposure_max = mode->vts_min - HM1246_COARSE_INTG_MARGIN;
+ hm1246->exposure_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &hm1246_ctrl_ops,
+ V4L2_CID_EXPOSURE,
+ HM1246_COARSE_INTG_MIN,
+ exposure_max,
+ HM1246_COARSE_INTG_STEP,
+ exposure_max);
+
+ v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &hm1246_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(hm1246_test_pattern_menu) - 1,
+ 0, 0, hm1246_test_pattern_menu);
+
+ v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &hm1246_ctrl_ops, &props);
+
+ if (ctrl_hdlr->error) {
+ v4l2_ctrl_handler_free(ctrl_hdlr);
+ return ctrl_hdlr->error;
+ }
+
+ hm1246->sd.ctrl_handler = ctrl_hdlr;
+
+ return 0;
+}
+
+static int hm1246_probe(struct i2c_client *client)
+{
+ struct hm1246 *hm1246;
+ int ret;
+
+ hm1246 = devm_kzalloc(&client->dev, sizeof(*hm1246), GFP_KERNEL);
+ if (!hm1246)
+ return -ENOMEM;
+
+ hm1246->dev = &client->dev;
+
+ ret = hm1246_parse_fwnode(hm1246);
+ if (ret)
+ return ret;
+
+ hm1246->regmap = devm_cci_regmap_init_i2c(client, 16);
+ if (IS_ERR(hm1246->regmap))
+ return dev_err_probe(hm1246->dev, PTR_ERR(hm1246->regmap),
+ "failed to init CCI\n");
+
+ hm1246->xclk = devm_v4l2_sensor_clk_get(hm1246->dev, NULL);
+ if (IS_ERR(hm1246->xclk))
+ return dev_err_probe(hm1246->dev, PTR_ERR(hm1246->xclk),
+ "failed to get xclk\n");
+
+ hm1246->xclk_freq = clk_get_rate(hm1246->xclk);
+ if (hm1246->xclk_freq < HM1246_XCLK_MIN ||
+ hm1246->xclk_freq > HM1246_XCLK_MAX)
+ return dev_err_probe(hm1246->dev, -EINVAL,
+ "xclk frequency out of range: %luHz\n",
+ hm1246->xclk_freq);
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(hm1246_modes); i++) {
+ ret = hm1246_calc_pll(hm1246->xclk_freq, hm1246->link_frequency,
+ hm1246_modes[i].clocks_per_pixel,
+ NULL, NULL, NULL);
+ if (ret)
+ return dev_err_probe(hm1246->dev, ret,
+ "no PLL setup for %lld Hz\n",
+ hm1246->link_frequency);
+ }
+
+ ret = hm1246_get_regulators(hm1246->dev, hm1246);
+ if (ret)
+ return dev_err_probe(hm1246->dev, ret,
+ "failed to get regulators\n");
+
+ hm1246->reset = devm_reset_control_get_optional(hm1246->dev, NULL);
+ if (IS_ERR(hm1246->reset))
+ return dev_err_probe(hm1246->dev, PTR_ERR(hm1246->reset),
+ "failed to get reset\n");
+ reset_control_assert(hm1246->reset);
+
+ v4l2_i2c_subdev_init(&hm1246->sd, client, &hm1246_subdev_ops);
+ hm1246->sd.internal_ops = &hm1246_internal_ops;
+
+ ret = hm1246_init_controls(hm1246);
+ if (ret)
+ return dev_err_probe(hm1246->dev, ret,
+ "failed to init controls\n");
+
+ hm1246->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ hm1246->pad.flags = MEDIA_PAD_FL_SOURCE;
+ hm1246->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+
+ ret = media_entity_pads_init(&hm1246->sd.entity, 1, &hm1246->pad);
+ if (ret) {
+ dev_err_probe(hm1246->dev, ret, "failed to init media pads\n");
+ goto err_v4l2_ctrl_handler_free;
+ }
+
+ hm1246->sd.state_lock = hm1246->ctrls.lock;
+ ret = v4l2_subdev_init_finalize(&hm1246->sd);
+ if (ret) {
+ dev_err_probe(hm1246->dev, ret, "failed to init v4l2 subdev\n");
+ goto err_media_entity_cleanup;
+ }
+
+ pm_runtime_enable(hm1246->dev);
+ pm_runtime_set_autosuspend_delay(hm1246->dev, 1000);
+ pm_runtime_use_autosuspend(hm1246->dev);
+ pm_runtime_idle(hm1246->dev);
+
+ ret = v4l2_async_register_subdev_sensor(&hm1246->sd);
+ if (ret) {
+ dev_err_probe(hm1246->dev, ret,
+ "failed to register v4l2 subdev\n");
+ goto err_subdev_cleanup;
+ }
+
+ return 0;
+
+err_subdev_cleanup:
+ v4l2_subdev_cleanup(&hm1246->sd);
+ pm_runtime_disable(hm1246->dev);
+ pm_runtime_set_suspended(hm1246->dev);
+
+err_media_entity_cleanup:
+ media_entity_cleanup(&hm1246->sd.entity);
+
+err_v4l2_ctrl_handler_free:
+ v4l2_ctrl_handler_free(&hm1246->ctrls);
+
+ return ret;
+}
+
+static void hm1246_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct hm1246 *hm1246 = to_hm1246(sd);
+
+ v4l2_async_unregister_subdev(&hm1246->sd);
+ v4l2_subdev_cleanup(sd);
+ media_entity_cleanup(&hm1246->sd.entity);
+ v4l2_ctrl_handler_free(&hm1246->ctrls);
+
+ pm_runtime_disable(&client->dev);
+ if (!pm_runtime_status_suspended(&client->dev)) {
+ hm1246_power_off(hm1246->dev);
+ pm_runtime_set_suspended(&client->dev);
+ }
+}
+
+static const struct of_device_id hm1246_of_match[] = {
+ { .compatible = "himax,hm1246" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, hm1246_of_match);
+
+static DEFINE_RUNTIME_DEV_PM_OPS(hm1246_pm_ops,
+ hm1246_power_off, hm1246_power_on, NULL);
+
+static struct i2c_driver hm1246_i2c_driver = {
+ .driver = {
+ .of_match_table = hm1246_of_match,
+ .pm = pm_ptr(&hm1246_pm_ops),
+ .name = "hm1246",
+ },
+ .probe = hm1246_probe,
+ .remove = hm1246_remove,
+};
+module_i2c_driver(hm1246_i2c_driver);
+
+MODULE_DESCRIPTION("Himax HM1246 camera driver");
+MODULE_AUTHOR("Matthias Fend <matthias.fend@emfend.at>");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* [PATCH v10 1/2] media: dt-bindings: i2c: add Himax HM1246 image sensor
From: Matthias Fend @ 2026-06-19 12:28 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans Verkuil, Sakari Ailus, Hans de Goede,
Ricardo Ribalda, André Apitzsch, Tarang Raval,
Andy Shevchenko, Benjamin Mugnier, Sylvain Petinot, Dongcheng Yan,
Bryan O'Donoghue, Alan Stern, Jingjing Xiong,
Heimir Thor Sverrisson, Mehdi Djait, Vladimir Zapolskiy,
Laurent Pinchart, Hardevsinh Palaniya, Svyatoslav Ryhel,
Philipp Zabel, Hans Verkuil, Hans de Goede, Xiaolei Wang,
Walter Werner Schneider, Kate Hsuan, Bartosz Golaszewski,
Miguel Vadillo
Cc: linux-media, devicetree, linux-kernel, Hao Yao, Himanshu Bhavani,
Matthias Fend
In-Reply-To: <20260619-hm1246-v10-0-d88e431a6c11@emfend.at>
Add YAML device tree binding for Himax HM1246 image sensor.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
---
.../bindings/media/i2c/himax,hm1246.yaml | 120 +++++++++++++++++++++
MAINTAINERS | 6 ++
2 files changed, 126 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/i2c/himax,hm1246.yaml b/Documentation/devicetree/bindings/media/i2c/himax,hm1246.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..a65488fcc643fd1e2b9435224813f35f2b4397c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/himax,hm1246.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2025 Matthias Fend <matthias.fend@emfend.at>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/himax,hm1246.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Himax HM1246-AWD 1/3.7-Inch megapixel SoC image sensor
+
+maintainers:
+ - Matthias Fend <matthias.fend@emfend.at>
+
+description:
+ The Himax HM1246-AWD is a 1/3.7-Inch CMOS image sensor SoC with an active
+ array size of 1296 x 976. It is programmable through an I2C interface and
+ connected via parallel bus.
+
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: himax,hm1246
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: Input reference clock (6 - 27 MHz)
+ maxItems: 1
+
+ reset-gpios:
+ description: Active low XSHUTDOWN pin
+ maxItems: 1
+
+ avdd-supply:
+ description: Power for analog circuit (3.0 - 3.6 V)
+
+ iovdd-supply:
+ description: Power for I/O circuit (1.7 - 3.6 V)
+
+ dvdd-supply:
+ description: Power for digital circuit (1.5 / 1.8 V)
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+ description: Parallel video output port
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-width:
+ default: 10
+
+ hsync-active:
+ default: 1
+
+ vsync-active:
+ default: 1
+
+ pclk-sample:
+ default: 0
+
+ required:
+ - link-frequencies
+
+ required:
+ - endpoint
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - avdd-supply
+ - iovdd-supply
+ - dvdd-supply
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/media/video-interfaces.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@24 {
+ compatible = "himax,hm1246";
+ reg = <0x24>;
+
+ clocks = <&hm1246_clk>;
+
+ reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&hm1246_avdd>;
+ iovdd-supply = <&hm1246_iovdd>;
+ dvdd-supply = <&hm1246_dvdd>;
+
+ orientation = <2>;
+ rotation = <0>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&isp_par_in>;
+ bus-width = <10>;
+ hsync-active = <1>; /* active high */
+ vsync-active = <1>; /* active high */
+ pclk-sample = <1>; /* sample on rising edge */
+ link-frequencies = /bits/ 64 <42200000>;
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index efbf808063e5066004180c36af88cb1f32c76a80..c320e7e9a2bd88319945bfe1202bc891d35f0f7c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11553,6 +11553,12 @@ L: linux-kernel@vger.kernel.org
S: Maintained
F: drivers/misc/hisi_hikey_usb.c
+HIMAX HM1246 SENSOR DRIVER
+M: Matthias Fend <matthias.fend@emfend.at>
+L: linux-media@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/media/i2c/himax,hm1246.yaml
+
HIMAX HX83112B TOUCHSCREEN SUPPORT
M: Job Noorman <job@noorman.info>
L: linux-input@vger.kernel.org
--
2.34.1
^ permalink raw reply related
* [PATCH v10 0/2] media: add Himax HM1246 image sensor
From: Matthias Fend @ 2026-06-19 12:28 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans Verkuil, Sakari Ailus, Hans de Goede,
Ricardo Ribalda, André Apitzsch, Tarang Raval,
Andy Shevchenko, Benjamin Mugnier, Sylvain Petinot, Dongcheng Yan,
Bryan O'Donoghue, Alan Stern, Jingjing Xiong,
Heimir Thor Sverrisson, Mehdi Djait, Vladimir Zapolskiy,
Laurent Pinchart, Hardevsinh Palaniya, Svyatoslav Ryhel,
Philipp Zabel, Hans Verkuil, Hans de Goede, Xiaolei Wang,
Walter Werner Schneider, Kate Hsuan, Bartosz Golaszewski,
Miguel Vadillo
Cc: linux-media, devicetree, linux-kernel, Hao Yao, Himanshu Bhavani,
Matthias Fend
Hello,
this series adds support for the Himax HM1246 image sensor.
The Himax HM1246-AWD is a 1/3.7-Inch CMOS image sensor SoC with an active
array size of 1296 x 976.
Currently, only the native RAW mode is supported. Other modes and the
internal image signal processing pipeline are not currently supported.
The data sheet is available on the manufacturer's website [1].
Tested on i.MX8MP hardware. A Toshiba TC358746 bridge was used to convert
the sensor's parallel video output into MIPI signals for the i.MX8MP.
Best regards
~Matthias
[1] https://www.himax.com.tw/wp-content/uploads/2024/03/HM1246-AWD_DS_v01.pdf
v4l2-compliance 1.28.1, 64 bits, 64-bit time_t
Compliance test for device /dev/v4l-subdev4:
Driver Info:
Driver version : 6.12.0
Capabilities : 0x00000000
Client Capabilities: 0x0000000000000003
streams interval-uses-which
Required ioctls:
test VIDIOC_SUDBEV_QUERYCAP: OK
test invalid ioctls: OK
Allow for multiple opens:
test second /dev/v4l-subdev4 open: OK
test VIDIOC_SUBDEV_QUERYCAP: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 15 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK (Not Supported)
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK (Not Supported)
test VIDIOC_TRY_FMT: OK (Not Supported)
test VIDIOC_S_FMT: OK (Not Supported)
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK (Not Supported)
test CREATE_BUFS maximum buffers: OK
test VIDIOC_REMOVE_BUFS: OK
test VIDIOC_EXPBUF: OK (Not Supported)
test Requests: OK (Not Supported)
Total for device /dev/v4l-subdev4: 45, Succeeded: 45, Failed: 0, Warnings: 0
Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
---
Changes in v10:
- Reordered struct hm1246 to place embedded struct first (Andy)
- Used hex format (0x01) for gain step definition (Andy)
- Marked local tables and constants as static const (Andy)
- Improved line wrapping in hm1246_cci_write_test_pattern (Andy)
- Decoupled declaration and initialization of ret in hm1246_set_ctrl (Andy)
- Rebased
- Link to v9: https://lore.kernel.org/r/20260128-hm1246-v9-0-f9c996486a95@emfend.at
Changes in v9:
- Use v4l2_rect in hm1246_mode
- Return in default case of hm1246_get_selection()
- Convert gpio based reset handling to use generic reset controller
- Link to v8: https://lore.kernel.org/r/20260113-hm1246-v8-0-ea93947b192e@emfend.at
Changes in v8:
- Adjusted copyright year (Sakari)
- Use local var for unreferenced v4l2 controls (Sakari)
- Return NULL instead of PTR_ERR if hm1246_find_mode_by_mbus_code() fails (Sakari)
- Removed unnecessary parentheses (Sakari)
- Dropped git reference in MAINTAINER entry (Sakari)
- Added default for bus-width in bindings (Sakari)
- Link to v7: https://lore.kernel.org/r/20260112-hm1246-v7-0-fee8587f2808@emfend.at
Changes in v7:
- Expect the PLL to generate the exact link frequency specified in DT (Laurent, Sakari)
- Dropped {g,s}_register functions
- Link to v6: https://lore.kernel.org/r/20251202-hm1246-v6-0-3e96ed6b3ffa@emfend.at
Changes in v6:
- Rework includes to follow include-what-you-use (Andy)
- Replace 'fsleep(6000)' with 'fsleep(6 * USEC_PER_MSEC)' (Andy)
- Simplify hm1246_get_selection() return (Andy)
- Use explicit indexes for test pattern array (Andy)
- Improve some line-wrappings (Andy)
- Avoid using __maybe_unused (Andy)
- Drop an unnecessary type cast (Andy)
- Use '0' instead of '0x0' (Andy)
- Reword comments about timings (Andy)
- Simplify error handling of hm1246_init_controls() (Sakari)
- Revert 'rework PLL calc to use goto' (Andy, Sakari)
- Link to v5: https://lore.kernel.org/r/20251104-hm1246-v5-0-97c8f25b5419@emfend.at
Changes in v5:
- Converted to lower case hexadecimals
- Use consistent returns in switch of hm1246_get_selection()
- Adjust some variable types/attributes
- Removed redundant parentheses
- Rework PLL calc to use goto
- Simplified some function returns
- Use array definition for test patterns
- Source format adjustments
- Properly init minimum of pixel_rate control
- dropped hm1246_update_controls()
- require and check DT link frequencies
- Link to v4: https://lore.kernel.org/r/20251017-hm1246-v4-0-e3388ea2f08c@emfend.at
Changes in v4:
- Split changes to MAINTAINERS into commits
- Fix comma after statement (use semicolon)
- Replace abs() with abs_diff() in PLL calculation
- Inverse needs_cmu_update logic
- Drop mode from hm1246_set_ctrl()
- Return if xclk frequency is out of range
- Fix reset_gpio dev_err_probe()
- Rebased on media-committers/next
- Link to v3: https://lore.kernel.org/r/20250912-hm1246-v3-0-3b89f47dfa43@emfend.at
Changes in v3:
- Bindings: Remove bus-type and add default polarity values
- Select V4L2_CCI_I2C
- Convert additional macros to use HZ_PER_*
- Replace cur_mode with v4l2_find_nearest_size()
- Remove duplicates in the register init sequence
- Use container_of_const
- Check return of hm1246_update_controls()
- Correct multi-line comments
- Replace hm1246_cci_write_cmu()
- Consistently use hm1246->dev
- Use pm_runtime_put_autosuspend()
- Remove v4l2 event handling
- Convert to devm_v4l2_sensor_clk_get()
- Configure PM before registering subdev
- Link to v2: https://lore.kernel.org/r/20250526-hm1246-v2-0-6b882827a3a5@emfend.at
- Depends-on: https://lore.kernel.org/all/20250707143253.167910-1-mehdi.djait@linux.intel.com/
Changes in v2:
- Use macros for 64-bit division
- Avoid compiler warnings about potentially uninitialized variables
- Fix two uses of dev_err_probe
- Link to v1: https://lore.kernel.org/r/20250403-hm1246-v1-0-30990d71bc42@emfend.at
---
Matthias Fend (2):
media: dt-bindings: i2c: add Himax HM1246 image sensor
media: i2c: add Himax HM1246 image sensor driver
.../bindings/media/i2c/himax,hm1246.yaml | 120 ++
MAINTAINERS | 7 +
drivers/media/i2c/Kconfig | 10 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/hm1246.c | 1291 ++++++++++++++++++++
5 files changed, 1429 insertions(+)
---
base-commit: 06cb687a5132fcffe624c0070576ab852ac6b568
change-id: 20250403-hm1246-96b0cdab773c
Best regards,
--
Matthias Fend <matthias.fend@emfend.at>
^ permalink raw reply
* Re: [PATCH 0/6] arm64: dts: qcom: sc8280xp: set GPI DMA channels according to DSDT
From: Konrad Dybcio @ 2026-06-19 12:27 UTC (permalink / raw)
To: Icenowy Zheng, Pengyu Luo
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <cd1910faf5b7b20d9154798b05449fe30cb1cba1.camel@iscas.ac.cn>
On 6/18/26 12:34 PM, Icenowy Zheng wrote:
> 在 2026-06-18四的 11:05 +0200，Konrad Dybcio写道：
>> On 6/18/26 11:04 AM, Konrad Dybcio wrote:
>>> On 6/9/26 5:54 PM, Icenowy Zheng wrote:
>>>> 在 2026-06-09二的 14:23 +0200，Konrad Dybcio写道：
>>>>> On 6/7/26 10:49 AM, Icenowy Zheng wrote:
>>>>>> 在 2026-06-06六的 21:51 +0800，Pengyu Luo写道：
>>>>>>> On Sat, Jun 6, 2026 at 9:21 PM Icenowy Zheng
>>>>>>> <zhengxingda@iscas.ac.cn> wrote:
>>>>>>>>
>>>>>>>> 在 2026-06-06六的 17:46 +0800，Pengyu Luo写道：
>>>>>>>>> On 2026-06-06 17:28:35+08:00, Icenowy Zheng wrote:
>>>>>>>>>> 在 2026-06-06六的 17:22 +0800，Pengyu Luo写道：
>>>>>>>>>>
>>>>>>>>>>> On 2026-06-02 21:21:27+08:00, Icenowy Zheng wrote:
>>>>>>>>>>>
>>>>>>>>>>> The magnetic keyboard (USB HID) can't be connected
>>>>>>>>>>> somehow,
>>>>>>>>>>> others
>>>>>>>>>>> are
>>>>>>>>>>> fine, such as the spi touchscreen (not upstream
>>>>>>>>>>> yet),
>>>>>>>>>>> which
>>>>>>>>>>> utilizes
>>>>>>>>>>> DMA definitely. My config is here
>>>>>>>>>>> https://pastebin.com/SdjuyJYk
>>>>>>>>>>
>>>>>>>>>> Is this a defconfig?
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Yes.
>>>>>>>>>
>>>>>>>>>> BTW it seems that CONFIG_ASYNC_TX_DMA needs to be
>>>>>>>>>> selected
>>>>>>>>>> too
>>>>>>>>>> for
>>>>>>>>>> exhibiting the problem (because there should be
>>>>>>>>>> "public"
>>>>>>>>>> GPI
>>>>>>>>>> DMA
>>>>>>>>>> consumers to trigger the stuck/reset).
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Is this still necessary? I checked the fedora
>>>>>>>>> discussion and
>>>>>>>>> your
>>>>>>>>> GPI
>>>>>>>>> DMA fix. And GPI DMA is only for the QUP-supported
>>>>>>>>> peripherals as
>>>>>>>>> the
>>>>>>>>> binding mentioned,
>>>>>>>>> devicetree/bindings/dma/qcom,gpi.yaml
>>>>>>>>
>>>>>>>> The devicetree without this fix seems to be still
>>>>>>>> incorrect,
>>>>>>>> because
>>>>>>>> with the device tree fix even if the GPI DMA driver
>>>>>>>> misbehaves
>>>>>>>> the
>>>>>>>> system won't be stuck (although it will iterate all GPI
>>>>>>>> channels
>>>>>>>> and
>>>>>>>> then fail to function at all).
>>>>>>>>
>>>>>>>
>>>>>>> Back to the start. You said some GPI interfaces aren't
>>>>>>> available
>>>>>>> to
>>>>>>> HLOS, your mask is 0xb(0b1011), so I use 0x4(0b100) did a
>>>>>>> quick
>>>>>>> test,
>>>>>>> and spi6 consumed it, no stuck or reset. Could you give me
>>>>>>> a
>>>>>>> unavailable channel?
>>>>>>
>>>>>> I think channel 0b10000 of gpi_dma2 could be an example?
>>>>>>
>>>>>> It seems that 4 channels are tried on gpi_dma2 before hang on
>>>>>> my
>>>>>> gaokun3, but as gaokun3 has no known serial access, it's
>>>>>> possible
>>>>>> that
>>>>>> 0b100000 or 0b1000 is problematic.
>>>>>>
>>>>>> (The reason gpi_dma2 is checked first is because it's the GPI
>>>>>> DMA
>>>>>> controller with the smallest address)
>>>>>>
>>>>>> BTW I just took the values from Windows DSDT, which is quite
>>>>>> conservative.
>>>>>
>>>>> So, with DMA_PRIVATE set, is this series made redundant?
>>>>
>>>> I assume technically the trustzone is still protecting some
>>>> channels,
>>>> although the system stuck issue is fixed.
>>>>
>>>> This series should still be relevant, although not so emergent.
>>>
>>> So now we're down to the case of the TZ reserving some of the GPI
>>> channels (presumably for locked down/TZ-driven QUPs) crashing the
>>> device on access, is that right?
>>
>> i.e. now, is requesting these channels through (wrongfully) enabling
>> the devices in DT the only remaining concern?
>
> Yes, I think so; although I think few devices will use GPI on these
> devices (usually only one or two SPI controllers according to the
> DSDTs).
IIRC there's a configuration table that lets OEMs decide which ones
should fall under the secure umbrella (although most never seem to
change the defaults).
I don't think we need to care too much about the mask being ultra-correct,
since as we've established only QUPs are "valid" consumers and we're not
going to enable them globally by default, since there are conflicting pin
assignments (i.e. there are many more QUPs than allocated GPIOs)
Konrad
^ permalink raw reply
* [PATCH v3] dt-bindings: misc: convert lis302.txt to YAML
From: Jad Keskes @ 2026-06-19 12:24 UTC (permalink / raw)
To: Eric Piel, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-kernel, Jad Keskes
In-Reply-To: <20260619115649.840676-1-inasj268@gmail.com>
Replace the old lis302.txt with a YAML binding covering all four
compatibles (st,lis3lv02d, st,lis302dl-spi, st,lis331dlh,
st,lis33de) and their ~35 DT properties.
The old txt documented st,click-thresh-* and st,click-click-time-limit
but the code reads st,click-threshold-* and st,click-time-limit.
Keep the old names as deprecated so existing DTBs don't break.
Use a select block that matches only nodes with misc-driver
compatibles (including standalone st,lis3lv02d for omap3-n950-n9
and similar), paired with the IIO schema which handles the IIO
side. This avoids both schemas validating the same node.
Tested: dt_binding_check. dtbs_check against 7 omap/am335x DTBs
(am335x-evm, am335x-evmsk, am335x-pepper, am437x-sk-evm, omap3-n900,
omap3-n950, omap3-gta04a3) — no misc schema errors. Pre-existing
IIO schema errors on paired compatible nodes unchanged.
Signed-off-by: Jad Keskes <inasj268@gmail.com>
---
v3:
- Add st,lis3lv02d to select block (fixes Sashiko review #1)
- Drop Patch 2 entirely (fixes Sashiko review #2 — IIO SPI driver still matches st,lis302dl-spi)
- Single patch, no IIO schema changes
v2:
- Rebase onto Linux 7.1-rc6
- Drop IIO changes, this is a single patch now
.../devicetree/bindings/iio/accel/lis302.txt | 119 ------
.../bindings/misc/st,lis3lv02d.yaml | 400 ++++++++++++++++++
MAINTAINERS | 1 +
3 files changed, 401 insertions(+), 119 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/accel/lis302.txt
create mode 100644 Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
diff --git a/Documentation/devicetree/bindings/iio/accel/lis302.txt b/Documentation/devicetree/bindings/iio/accel/lis302.txt
deleted file mode 100644
index 457539647f36..000000000000
--- a/Documentation/devicetree/bindings/iio/accel/lis302.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-LIS302 accelerometer devicetree bindings
-
-This device is matched via its bus drivers, and has a number of properties
-that apply in on the generic device (independent from the bus).
-
-
-Required properties for the SPI bindings:
- - compatible: should be set to "st,lis3lv02d-spi"
- - reg: the chipselect index
- - spi-max-frequency: maximal bus speed, should be set to 1000000 unless
- constrained by external circuitry
- - interrupts: the interrupt generated by the device
-
-Required properties for the I2C bindings:
- - compatible: should be set to "st,lis3lv02d"
- - reg: i2c slave address
- - Vdd-supply: The input supply for Vdd
- - Vdd_IO-supply: The input supply for Vdd_IO
-
-
-Optional properties for all bus drivers:
-
- - st,click-single-{x,y,z}: if present, tells the device to issue an
- interrupt on single click events on the
- x/y/z axis.
- - st,click-double-{x,y,z}: if present, tells the device to issue an
- interrupt on double click events on the
- x/y/z axis.
- - st,click-thresh-{x,y,z}: set the x/y/z axis threshold
- - st,click-click-time-limit: click time limit, from 0 to 127.5msec
- with step of 0.5 msec
- - st,click-latency: click latency, from 0 to 255 msec with
- step of 1 msec.
- - st,click-window: click window, from 0 to 255 msec with
- step of 1 msec.
- - st,irq{1,2}-disable: disable IRQ 1/2
- - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition
- - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition
- - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready condition
- - st,irq{1,2}-click: raise IRQ 1/2 on click condition
- - st,irq-open-drain: consider IRQ lines open-drain
- - st,irq-active-low: make IRQ lines active low
- - st,wu-duration-1: duration register for Free-Fall/Wake-Up
- interrupt 1
- - st,wu-duration-2: duration register for Free-Fall/Wake-Up
- interrupt 2
- - st,wakeup-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for
- upper/lower limit
- - st,wakeup-threshold: set wakeup threshold
- - st,wakeup2-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for
- upper/lower limit for second wakeup
- engine.
- - st,wakeup2-threshold: set wakeup threshold for second wakeup
- engine.
- - st,highpass-cutoff-hz=: 1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of
- highpass cut-off frequency
- - st,hipass{1,2}-disable: disable highpass 1/2.
- - st,default-rate=: set the default rate
- - st,axis-{x,y,z}=: set the axis to map to the three coordinates.
- Negative values can be used for inverted axis.
- - st,{min,max}-limit-{x,y,z} set the min/max limits for x/y/z axis
- (used by self-test)
-
-
-Example for a SPI device node:
-
- accelerometer@0 {
- compatible = "st,lis302dl-spi";
- reg = <0>;
- spi-max-frequency = <1000000>;
- interrupt-parent = <&gpio>;
- interrupts = <104 0>;
-
- st,click-single-x;
- st,click-single-y;
- st,click-single-z;
- st,click-thresh-x = <10>;
- st,click-thresh-y = <10>;
- st,click-thresh-z = <10>;
- st,irq1-click;
- st,irq2-click;
- st,wakeup-x-lo;
- st,wakeup-x-hi;
- st,wakeup-y-lo;
- st,wakeup-y-hi;
- st,wakeup-z-lo;
- st,wakeup-z-hi;
- };
-
-Example for a I2C device node:
-
- lis331dlh: accelerometer@18 {
- compatible = "st,lis331dlh", "st,lis3lv02d";
- reg = <0x18>;
- Vdd-supply = <&lis3_reg>;
- Vdd_IO-supply = <&lis3_reg>;
-
- st,click-single-x;
- st,click-single-y;
- st,click-single-z;
- st,click-thresh-x = <10>;
- st,click-thresh-y = <10>;
- st,click-thresh-z = <10>;
- st,irq1-click;
- st,irq2-click;
- st,wakeup-x-lo;
- st,wakeup-x-hi;
- st,wakeup-y-lo;
- st,wakeup-y-hi;
- st,wakeup-z-lo;
- st,wakeup-z-hi;
- st,min-limit-x = <120>;
- st,min-limit-y = <120>;
- st,min-limit-z = <140>;
- st,max-limit-x = <550>;
- st,max-limit-y = <550>;
- st,max-limit-z = <750>;
- };
-
diff --git a/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml b/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
new file mode 100644
index 000000000000..c73371b754a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
@@ -0,0 +1,400 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/st,lis3lv02d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics LIS3LV02D and similar accelerometers (misc driver)
+
+maintainers:
+ - Eric Piel <eric.piel@tremplin-utc.net>
+
+description:
+ This binding describes the STMicroelectronics accelerometers supported by
+ the misc/lis3lv02d driver. This driver provides input (joystick) and
+ hardware monitoring support, in contrast to the IIO st-accel driver which
+ also supports some of these devices.
+ Refer to Documentation/devicetree/bindings/iio/st,st-sensors.yaml for the
+ IIO binding.
+
+select:
+ anyOf:
+ - properties:
+ compatible:
+ contains:
+ const: st,lis302dl-spi
+ - properties:
+ compatible:
+ contains:
+ const: st,lis331dlh
+ - properties:
+ compatible:
+ contains:
+ const: st,lis33de
+ - properties:
+ compatible:
+ contains:
+ const: st,lis3lv02d
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - st,lis331dlh
+ - st,lis33de
+ - const: st,lis3lv02d
+ - const: st,lis331dlh
+ - const: st,lis3lv02d
+ - const: st,lis302dl-spi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ spi-max-frequency:
+ description: SPI bus frequency; should be set to 1000000 unless
+ constrained by external circuitry.
+ maximum: 1000000
+
+ Vdd-supply:
+ description: The input supply for Vdd.
+
+ Vdd_IO-supply:
+ description: The input supply for Vdd_IO.
+
+ st,click-single-x:
+ description: Issue an interrupt on single click events on the X axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-double-x:
+ description: Issue an interrupt on double click events on the X axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-single-y:
+ description: Issue an interrupt on single click events on the Y axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-double-y:
+ description: Issue an interrupt on double click events on the Y axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-single-z:
+ description: Issue an interrupt on single click events on the Z axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-double-z:
+ description: Issue an interrupt on double click events on the Z axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-thresh-x:
+ description: X axis click threshold (deprecated spelling, use st,click-threshold-x).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
+
+ st,click-thresh-y:
+ description: Y axis click threshold (deprecated spelling, use st,click-threshold-y).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
+
+ st,click-thresh-z:
+ description: Z axis click threshold (deprecated spelling, use st,click-threshold-z).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
+
+ st,click-threshold-x:
+ description: X axis click threshold.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,click-threshold-y:
+ description: Y axis click threshold.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,click-threshold-z:
+ description: Z axis click threshold.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,click-click-time-limit:
+ description: Click time limit (deprecated spelling, use st,click-time-limit).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+ deprecated: true
+
+ st,click-time-limit:
+ description: Click time limit, from 0 to 127.5 msec with step of 0.5 msec.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,click-latency:
+ description: Click latency, from 0 to 255 msec with step of 1 msec.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,click-window:
+ description: Click window, from 0 to 255 msec with step of 1 msec.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,irq1-disable:
+ description: Disable IRQ 1.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq1-ff-wu-1:
+ description: Raise IRQ 1 on FF_WU_1 condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq1-ff-wu-2:
+ description: Raise IRQ 1 on FF_WU_2 condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq1-data-ready:
+ description: Raise IRQ 1 on data ready condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq1-click:
+ description: Raise IRQ 1 on click condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-disable:
+ description: Disable IRQ 2.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-ff-wu-1:
+ description: Raise IRQ 2 on FF_WU_1 condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-ff-wu-2:
+ description: Raise IRQ 2 on FF_WU_2 condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-data-ready:
+ description: Raise IRQ 2 on data ready condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-click:
+ description: Raise IRQ 2 on click condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq-open-drain:
+ description: Consider IRQ lines open-drain.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq-active-low:
+ description: Make IRQ lines active low.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wu-duration-1:
+ description: Duration register for Free-Fall/Wake-Up interrupt 1.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,wu-duration-2:
+ description: Duration register for Free-Fall/Wake-Up interrupt 2.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,wakeup-x-lo:
+ description: Set wakeup condition on X axis for lower limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-x-hi:
+ description: Set wakeup condition on X axis for upper limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-y-lo:
+ description: Set wakeup condition on Y axis for lower limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-y-hi:
+ description: Set wakeup condition on Y axis for upper limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-z-lo:
+ description: Set wakeup condition on Z axis for lower limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-z-hi:
+ description: Set wakeup condition on Z axis for upper limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-threshold:
+ description: Set wakeup threshold.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,wakeup2-x-lo:
+ description: Set wakeup condition on X axis for lower limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-x-hi:
+ description: Set wakeup condition on X axis for upper limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-y-lo:
+ description: Set wakeup condition on Y axis for lower limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-y-hi:
+ description: Set wakeup condition on Y axis for upper limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-z-lo:
+ description: Set wakeup condition on Z axis for lower limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-z-hi:
+ description: Set wakeup condition on Z axis for upper limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-threshold:
+ description: Set wakeup threshold for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,highpass-cutoff-hz:
+ description: Highpass cut-off frequency. Valid values are 1, 2, 4 or 8.
+ enum: [1, 2, 4, 8]
+
+ st,hipass1-disable:
+ description: Disable highpass filter 1.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,hipass2-disable:
+ description: Disable highpass filter 2.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,default-rate:
+ description: Set the default output data rate.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,axis-x:
+ description: Set the X axis mapping. Negative values can be used for inverted axis.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,axis-y:
+ description: Set the Y axis mapping. Negative values can be used for inverted axis.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,axis-z:
+ description: Set the Z axis mapping. Negative values can be used for inverted axis.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,min-limit-x:
+ description: Minimum limit for X axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,min-limit-y:
+ description: Minimum limit for Y axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,min-limit-z:
+ description: Minimum limit for Z axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,max-limit-x:
+ description: Maximum limit for X axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,max-limit-y:
+ description: Maximum limit for Y axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,max-limit-z:
+ description: Maximum limit for Z axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: st,lis302dl-spi
+ then:
+ required:
+ - Vdd-supply
+ - Vdd_IO-supply
+ else:
+ properties:
+ Vdd-supply: false
+ Vdd_IO-supply: false
+ required:
+ - spi-max-frequency
+ - interrupts
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@18 {
+ compatible = "st,lis331dlh", "st,lis3lv02d";
+ reg = <0x18>;
+ Vdd-supply = <&lis3_reg>;
+ Vdd_IO-supply = <&lis3_reg>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <18 0>;
+
+ st,click-single-x;
+ st,click-single-y;
+ st,click-single-z;
+ st,click-threshold-x = <10>;
+ st,click-threshold-y = <10>;
+ st,click-threshold-z = <10>;
+ st,irq1-click;
+ st,irq2-click;
+ st,wakeup-x-lo;
+ st,wakeup-x-hi;
+ st,wakeup-y-lo;
+ st,wakeup-y-hi;
+ st,wakeup-z-lo;
+ st,wakeup-z-hi;
+ st,min-limit-x = <120>;
+ st,min-limit-y = <120>;
+ st,min-limit-z = <140>;
+ st,max-limit-x = <550>;
+ st,max-limit-y = <550>;
+ st,max-limit-z = <750>;
+ };
+ };
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@0 {
+ compatible = "st,lis302dl-spi";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <104 0>;
+
+ st,click-single-x;
+ st,click-single-y;
+ st,click-single-z;
+ st,click-threshold-x = <10>;
+ st,click-threshold-y = <10>;
+ st,click-threshold-z = <10>;
+ st,irq1-click;
+ st,irq2-click;
+ st,wakeup-x-lo;
+ st,wakeup-x-hi;
+ st,wakeup-y-lo;
+ st,wakeup-y-hi;
+ st,wakeup-z-lo;
+ st,wakeup-z-hi;
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 9ec290e38b44..4cffabbabf0e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14858,6 +14858,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/
LIS3LV02D ACCELEROMETER DRIVER
M: Eric Piel <eric.piel@tremplin-utc.net>
S: Maintained
+F: Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
F: Documentation/misc-devices/lis3lv02d.rst
F: drivers/misc/lis3lv02d/
F: drivers/platform/x86/hp/hp_accel.c
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v3 1/8] dt-bindings: remoteproc: qcom,pas: add thermal mitigation properties
From: Daniel Lezcano @ 2026-06-19 12:16 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Gaurav Kohli, Krzysztof Kozlowski, Bjorn Andersson,
Mathieu Poirier, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Amit Kucheria, Manivannan Sadhasivam, Konrad Dybcio, Kees Cook,
Gustavo A. R. Silva, cros-qcom-dts-watchers, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, linux-pm,
linux-hardening, Manaf Meethalavalappu Pallikunhi
In-Reply-To: <4gs664zboaqgpok33x7bgorfmhh3f2fahjkt4jjl6fbzpwixnm@hxzz2xeogd4k>
On 6/16/26 00:15, Dmitry Baryshkov wrote:
> On Mon, Jun 15, 2026 at 05:33:15PM +0200, Daniel Lezcano wrote:
>>
>>
>> Le 15/06/2026 à 17:14, Dmitry Baryshkov a écrit :
>>> On Mon, Jun 15, 2026 at 04:33:38PM +0200, Daniel Lezcano wrote:
>>>>
>>>>
>>>> Le 15/06/2026 à 16:11, Dmitry Baryshkov a écrit :
>>>>> On Mon, Jun 15, 2026 at 02:30:49PM +0200, Daniel Lezcano wrote:
>>>>>> Hi Gaurav,
>>>>>>
>>>>>> Le 15/06/2026 à 14:12, Gaurav Kohli a écrit :
>>>>>>>
>>>>>>>
>>>>>>> On 6/15/2026 4:04 PM, Daniel Lezcano wrote:
>>>>>>>> On 6/13/26 13:05, Gaurav Kohli wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On 6/13/2026 1:11 PM, Krzysztof Kozlowski wrote:
>>>>>>>>>> On 12/06/2026 15:52, Gaurav Kohli wrote:
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> On 6/11/2026 5:53 PM, Krzysztof Kozlowski wrote:
>>>>>>>>>>>> On 11/06/2026 13:12, Gaurav Kohli wrote:
>>>>>>>>>>>>>> Why? And where is this generic property defined? You cannot just
>>>>>>>>>>>>>> sprinkle generic properties in random bindings.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> Ack, will add why part.
>>>>>>>>>>>>> These names are matched with the thermal
>>>>>>>>>>>>> mitigation device identifiers
>>>>>>>>>>>>> populated by remote firmware over QMI and define
>>>>>>>>>>>>> mitigation devices are
>>>>>>>>>>>>> exposed as cooling devices.
>>>>>>>>>>>>
>>>>>>>>>>>> No, -names correspond to values passed via DT, not
>>>>>>>>>>>> some remote firmware.
>>>>>>>>>>>> The remote firmware should give you interface which
>>>>>>>>>>>> is explicit and does
>>>>>>>>>>>> not need such properties.
>>>>>>>>>>>
>>>>>>>>>>> thanks Krzysztof for review, We need tmd-names because
>>>>>>>>>>> of following reasons:
>>>>>>>>>>>
>>>>>>>>>>> Following Daniel's series [1], the thermal framework supports
>>>>>>>>>>> mapping multiple cooling devices per remoteproc/device via indexed
>>>>>>>>>>> cooling-cells.
>>>>>>>>>>>
>>>>>>>>>>> 1) The thermal framework's cooling-maps reference
>>>>>>>>>>> cooling devices by index (for #cooling-cells = <3>).
>>>>>>>>>>> Without tmd- names,
>>>>>>>>>>> there's no way to know which index corresponds to which
>>>>>>>>>>> TMD, as firmware
>>>>>>>>>>> may return tmd-names in any order.
>>>>>>>>>>>
>>>>>>>>>>> below are the changes post new thermal mapping changes:
>>>>>>>>>>> DT: tmd-names = "cdsp_sw", "xyz";
>>>>>>>>>>> Firmware: ["cdsp_sw", "xyz1", "xyz2",]
>>>>>>>>>>> Driver registers: Only "cdsp_sw" (index 0) and "xyz" (index 1)
>>>>>>>>>>
>>>>>>>>>> names property are not to instruct drivers to register or not to
>>>>>>>>>> register something.
>>>>>>>>>>
>>>>>>>>>> I don't understand the problem and explanation in the binding is
>>>>>>>>>> basically non-existing.
>>>>>>>>>>
>>>>>>>>>> Remember that all lists and indices ARE FIXED, so driver knows exactly
>>>>>>>>>> which index means what.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> thanks for review, shall i use driver data, which is basically
>>>>>>>>> pas data structure like below:
>>>>>>>>>
>>>>>>>>> static const struct qcom_pas_data {
>>>>>>>>> .crash_reason_smem = 601,
>>>>>>>>> .firmware_name = "cdsp.mdt",
>>>>>>>>> .tmd_names = (const char *[]){"xyz", NULL},
>>>>>>>>> .num_tmds = 1,
>>>>>>>>>
>>>>>>>>> Is something like above acceptable? and this will also help to
>>>>>>>>> filter tmd names as well?
>>>>>>>>
>>>>>>>>
>>>>>>>> How the thermal framework will bind the thermal zone with the TMD ?
>>>>>>>> (node pointer, id) ?
>>>>>>>>
>>>>>>>
>>>>>>> Hi Daniel,
>>>>>>>
>>>>>>> thanks for review.
>>>>>>>
>>>>>>> With id only, in this case instead of taking tmd names from device tree,
>>>>>>> qmi_tmd will take tmd name from pas_data(driver) and register with the
>>>>>>> cooling framework with id only. Please let us know if this looks fine.
>>>>>> May be I'm missing something but:
>>>>>>
>>>>>> - The QMI TMD returns a list of names, not ids
>>>>>> - The QMI TMD may return the list in different order than assumed
>>>>>> - The cooling map index points to the name of the TMD in the DT
>>>>>> - This name is used to match the name in the aformentionned list
>>>>>> - The index in the list and the id in the DT can differ
>>>>>
>>>>> Would it be better if we define standard indices for the standard names?
>>>>> This way we decouple the actual firmware strings from the DT.
>>>>
>>>> I don't think so, it seems to me too fragile and prone to error.
>>>>
>>>> It is a remote proc, an external subsystem. The contract between the client
>>>> and the server is the protocol. The protocol specifies the identifier as
>>>> named strings, the TMD names, not numerical identifiers.
>>>>
>>>> When asking for the list of TMDs, we get a list of strings. But as it is an
>>>> external subsystems, may be tomorrow someone decide to send list ordered
>>>> alphabetically, or per number of states, or whatever.
>>>>
>>>> With hardcoded id the QMI TMD clients break
>>>
>>> I was thinking about something like:
>>>
>>> #define QCOM_TMD_DSP 0
>>> #define QCOM_TMD_PA 1
>>
>> Ah ok, it is correct if:
>>
>> tmd-names = "dsp", "pa"
>>
>> Or
>>
>> #define QCOM_TMD_PA 0
>> #define QCOM_TMD_DSP 1
>>
>> tmd-names = "pa", "dsp"
>
> I was more inclined about having the standard indices for the standard
> mitigations.
>
> BTW, I checked, which mitigations are being returned by the DSPs. Few
> examples, just to provide some context.
I don't know if you are missing my point or if I'm missing yours :)
The QMI TMD protocol identifies the TMD with strings. There is no
guarantee the ordering is kept if there is a firmware upgrade.
The ID is to connect the cooling map with the remote proc node index.
Its only a thermal description not related to the TMD itself.
> SC8280XP, X13s:
>
> TMD service: instance=0x01 (adsp) node=5 port=9
> 1 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
>
> TMD service: instance=0x53 (slpi) node=9 port=9
> 1 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
>
> TMD service: instance=0x43 (cdsp) node=10 port=8
> 3 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
> [ 1] cdsp_hw max_mitigation_level=1
> [ 2] cdsp_sw max_mitigation_level=7
>
> SM6115, RB2:
>
> TMD service: instance=0x00 (modem) node=0 port=20
> 9 mitigation device(s):
> [ 0] pa max_mitigation_level=3
> [ 1] modem max_mitigation_level=3
> [ 2] cpuv_restriction_cold max_mitigation_level=1
> [ 3] modem_current max_mitigation_level=3
> [ 4] vbatt_low max_mitigation_level=3
> [ 5] modem_skin max_mitigation_level=3
> [ 6] modem_bw max_mitigation_level=5
> [ 7] wlan max_mitigation_level=1
> [ 8] wlan_bw max_mitigation_level=1
>
> TMD service: instance=0x01 (adsp) node=5 port=8
> 1 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
>
> TMD service: instance=0x43 (cdsp) node=10 port=8
> 3 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
> [ 1] cdsp_hw max_mitigation_level=1
> [ 2] cdsp_sw max_mitigation_level=5
>
>
> SM8350, HDK:
>
> TMD service: instance=0x00 (modem) node=0 port=22
> 28 mitigation device(s):
> [ 0] pa max_mitigation_level=3
> [ 1] pa_fr1 max_mitigation_level=3
> [ 2] modem max_mitigation_level=3
> [ 3] cpuv_restriction_cold max_mitigation_level=1
> [ 4] modem_current max_mitigation_level=3
> [ 5] vbatt_low max_mitigation_level=3
> [ 6] charge_state max_mitigation_level=3
> [ 7] modem_skin max_mitigation_level=3
> [ 8] modem_bw max_mitigation_level=5
> [ 9] mmw0 max_mitigation_level=3
> [10] mmw1 max_mitigation_level=3
> [11] mmw2 max_mitigation_level=3
> [12] mmw3 max_mitigation_level=3
> [13] mmw_skin0 max_mitigation_level=3
> [14] mmw_skin1 max_mitigation_level=3
> [15] mmw_skin2 max_mitigation_level=3
> [16] mmw_skin3 max_mitigation_level=3
> [17] mmw_skin0_dsc max_mitigation_level=15
> [18] mmw_skin1_dsc max_mitigation_level=15
> [19] mmw_skin2_dsc max_mitigation_level=15
> [20] mmw_skin3_dsc max_mitigation_level=15
> [21] wlan max_mitigation_level=4
> [22] wlan_bw max_mitigation_level=1
> [23] modem_skin_lte_dsc max_mitigation_level=255
> [24] modem_skin_nr_dsc max_mitigation_level=255
> [25] pa_dsc max_mitigation_level=255
> [26] pa_fr1_dsc max_mitigation_level=255
> [27] cpr_cold max_mitigation_level=3
>
> TMD service: instance=0x01 (adsp) node=5 port=9
> 1 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
>
> TMD service: instance=0x43 (cdsp) node=10 port=9
> 3 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
> [ 1] cdsp_hw max_mitigation_level=1
> [ 2] cdsp_sw max_mitigation_level=7
>
> SM8150, HDK:
>
> TMD service: instance=0x00 (modem) node=0 port=21
> 6 mitigation device(s):
> [ 0] pa max_mitigation_level=3
> [ 1] modem max_mitigation_level=3
> [ 2] cpuv_restriction_cold max_mitigation_level=1
> [ 3] modem_current max_mitigation_level=3
> [ 4] vbatt_low max_mitigation_level=3
> [ 5] modem_skin max_mitigation_level=3
>
> TMD service: instance=0x01 node=5 port=8
> 1 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
>
> TMD service: instance=0x53 node=9 port=8
> 1 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
>
> TMD service: instance=0x43 (cdsp) node=10 port=8
> 1 mitigation device(s):
> [ 0] cpuv_restriction_cold max_mitigation_level=1
>
>
^ permalink raw reply
* Re: [PATCH 2/2] thermal: qcom: Add support for Qualcomm MBG thermal monitoring
From: Konrad Dybcio @ 2026-06-19 12:14 UTC (permalink / raw)
To: Sachin Gupta, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Stephen Boyd, Jishnu Prakash, Kamal Wadhwa,
Amit Kucheria, Thara Gopinath
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pm,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik, Taniya Das,
Jagadeesh Kona
In-Reply-To: <487f0ed1-dfc2-4f7b-94ce-60045017a663@oss.qualcomm.com>
On 6/19/26 8:45 AM, Sachin Gupta wrote:
>
>
> On 6/16/2026 3:40 PM, Konrad Dybcio wrote:
>> On 6/1/26 1:01 PM, Sachin Gupta wrote:
>>> From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>>>
>>> Add driver for the Qualcomm MBG thermal monitoring device. It monitors
>>> the die temperature, and when there is a level 1 upper threshold
>>> violation, it receives an interrupt over spmi. The driver reads
>>> the fault status register and notifies thermal accordingly.
>>>
>>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>>> Co-developed-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com>
>>> Signed-off-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com>
>>> ---
[...]
>>> + /*
>>> + * Configure the last_temp one degree higher, to ensure the
>>> + * violated temp is returned to thermal framework when it reads
>>> + * temperature for the first time after the violation happens.
>>> + * This is needed to account for the inaccuracy in the conversion
>>> + * formula used which leads to the thermal framework setting back
>>> + * the same thresholds in case the temperature it reads does not
>>> + * show violation.
>>> + */
>>> + chip->last_temp = temp + MBG_TEMP_CONSTANT;
>>
>> Will this work fine if the user tries to set the max temp supported
>> by the hardware (i.e. is there headroom for max+1)?
>>
>
> In the current implementation, temp == MBG_MAX_SUPPORTED_TEMP is not accepted (temp < MBG_MAX_SUPPORTED_TEMP), so the last_temp = temp + MBG_TEMP_CONSTANT path is never taken at absolute max. For accepted trips (strictly below max), there is headroom for the +1C adjustment.
You check for `temp < MBG_MAX_SUPPORTED_TEMP` and there's:
#define MBG_MAX_SUPPORTED_TEMP 160000,
so passing temp=159999 is "valid" and after the addition it becomes 160999,
which in my understanding is outside the range
Konrad
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: misc: convert lis302.txt to YAML
From: sashiko-bot @ 2026-06-19 12:09 UTC (permalink / raw)
To: Jad Keskes; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260619115649.840676-1-inasj268@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `select` block incorrectly excludes standalone `st,lis3lv02d` nodes, breaking schema validation for in-tree boards and creating dead code.
--
commit 4d572cc896007c912787ebc5396d56f2920edb3d
Author: Jad Keskes <inasj268@gmail.com>
dt-bindings: misc: convert lis302.txt to YAML
This patch replaces the legacy lis302.txt binding with a YAML schema for the
LIS3LV02D family of accelerometers. It introduces a select block intended to
restrict the schema to misc-driver-exclusive compatibles, under the assumption
that standalone st,lis3lv02d nodes belong to the IIO subsystem.
> diff --git a/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml b/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
> new file mode 100644
> index 0000000000000..85eb74c264bc0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
> @@ -0,0 +1,396 @@
[ ... ]
> +select:
> + anyOf:
> + - properties:
> + compatible:
> + contains:
> + const: st,lis302dl-spi
> + - properties:
> + compatible:
> + contains:
> + const: st,lis331dlh
> + - properties:
> + compatible:
> + contains:
> + const: st,lis33de
> + required:
> + - compatible
[Severity: Medium]
The commit message claims standalone st,lis3lv02d nodes only go to the
IIO driver, but could this select block incorrectly exclude valid standalone
st,lis3lv02d nodes used by the misc driver?
For example, arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi uses a standalone
st,lis3lv02d compatible while relying heavily on misc-driver-specific
properties like st,click-threshold-x and Vdd-supply.
Because this block explicitly omits st,lis3lv02d, that valid DT node bypasses
the misc schema entirely. It instead falls back to the IIO schema
(st,st-sensors.yaml), which specifies additionalProperties: false and does
not recognize misc properties, leading to validation errors.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - st,lis331dlh
> + - st,lis33de
> + - const: st,lis3lv02d
> + - const: st,lis331dlh
> + - const: st,lis3lv02d
[Severity: Medium]
Is the standalone const: st,lis3lv02d option rendered unreachable dead code,
since any node matching just st,lis3lv02d is excluded by the select block
above?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260619115649.840676-1-inasj268@gmail.com?part=1
^ permalink raw reply
* Re: [PATCH 2/2] dt-bindings: iio: st-sensors: drop lis302dl-spi from deprecated list
From: sashiko-bot @ 2026-06-19 12:06 UTC (permalink / raw)
To: Jad Keskes; +Cc: devicetree, conor+dt, robh
In-Reply-To: <20260619115649.840676-2-inasj268@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect Schema Removal / Broken Validation for st,lis302dl-spi
--
commit 23c740836661eab02e0a98566f673ed373f8b4d3
Author: Jad Keskes <inasj268@gmail.com>
dt-bindings: iio: st-sensors: drop lis302dl-spi from deprecated list
This commit removes the st,lis302dl-spi compatible string from the deprecated
list in the IIO st-sensors binding. It claims the compatible string is only
used by the misc driver.
> st,lis302dl-spi is only used by the misc/lis3lv02d driver. Its
> binding is now in Documentation/devicetree/bindings/misc/.
[Severity: Medium]
Is this statement accurate? Looking at drivers/iio/accel/st_accel_spi.c, the
IIO SPI driver still explicitly matches st,lis302dl-spi:
drivers/iio/accel/st_accel_spi.c:st_accel_of_match[] = {
{
/* An older compatible */
.compatible = "st,lis302dl-spi",
.data = LIS3LV02DL_ACCEL_DEV_NAME,
},
> diff --git a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml
> index a1a958215cdb7..2a5451589fabf 100644
> --- a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml
> +++ b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml
> @@ -90,10 +90,8 @@ properties:
> - st,lsm9ds0-imu
> - description: Deprecated bindings
> enum:
> - - st,lis302dl-spi
[Severity: Medium]
If st,lis302dl-spi is removed from the IIO binding, won't dtbs_check fail for
any valid device tree that pairs this compatible string with standard IIO
properties (such as vdd-supply or mount-matrix)?
Since the misc binding (st,lis3lv02d.yaml) enforces additionalProperties: false,
it would reject these IIO properties. It appears st,lis3lv02d was kept in the
schema for the exact same reason that st,lis302dl-spi should be kept.
> - st,lis3lv02d
> deprecated: true
> -
> reg:
> maxItems: 1
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260619115649.840676-1-inasj268@gmail.com?part=2
^ permalink raw reply
* [PATCH 2/2] dt-bindings: iio: st-sensors: drop lis302dl-spi from deprecated list
From: Jad Keskes @ 2026-06-19 11:56 UTC (permalink / raw)
To: Jonathan Cameron, Eric Piel
Cc: Rob Herring, Krzysztof Kozlowski, linux-iio, devicetree,
linux-kernel, Jad Keskes
In-Reply-To: <20260619115649.840676-1-inasj268@gmail.com>
st,lis302dl-spi is only used by the misc/lis3lv02d driver. Its
binding is now in Documentation/devicetree/bindings/misc/.
Keep st,lis3lv02d in the deprecated list — the IIO i2c driver
still matches it for LIS3LV02DL support.
Tested: dt_binding_check, dtbs_check.
Signed-off-by: Jad Keskes <inasj268@gmail.com>
---
Documentation/devicetree/bindings/iio/st,st-sensors.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml
index a1a958215cdb..2a5451589fab 100644
--- a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml
+++ b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml
@@ -90,10 +90,8 @@ properties:
- st,lsm9ds0-imu
- description: Deprecated bindings
enum:
- - st,lis302dl-spi
- st,lis3lv02d
deprecated: true
-
reg:
maxItems: 1
--
2.54.0
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: misc: convert lis302.txt to YAML
From: Jad Keskes @ 2026-06-19 11:56 UTC (permalink / raw)
To: Jonathan Cameron, Eric Piel
Cc: Rob Herring, Krzysztof Kozlowski, linux-iio, devicetree,
linux-kernel, Jad Keskes
Replace the old lis302.txt with a YAML binding covering all four
compatibles (st,lis3lv02d, st,lis302dl-spi, st,lis331dlh,
st,lis33de) and their ~35 DT properties.
The old txt documented st,click-thresh-* and st,click-click-time-limit
but the code reads st,click-threshold-* and st,click-time-limit.
Keep the old names as deprecated so existing DTBs don't break.
Add a select: so the misc schema only applies to nodes with
misc-exclusive compatibles. Standalone st,lis3lv02d nodes that go
to the IIO driver validate against the IIO schema instead.
Tested: dt_binding_check, dtbs_check against 7 omap/am335x DTBs
(am335x-evm, am335x-evmsk, am335x-pepper, am437x-sk-evm, omap3-n900,
omap3-n950, omap3-gta04a3). All clean.
Signed-off-by: Jad Keskes <inasj268@gmail.com>
---
.../devicetree/bindings/iio/accel/lis302.txt | 119 ------
.../bindings/misc/st,lis3lv02d.yaml | 396 ++++++++++++++++++
MAINTAINERS | 1 +
3 files changed, 397 insertions(+), 119 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/accel/lis302.txt
create mode 100644 Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
diff --git a/Documentation/devicetree/bindings/iio/accel/lis302.txt b/Documentation/devicetree/bindings/iio/accel/lis302.txt
deleted file mode 100644
index 457539647f36..000000000000
--- a/Documentation/devicetree/bindings/iio/accel/lis302.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-LIS302 accelerometer devicetree bindings
-
-This device is matched via its bus drivers, and has a number of properties
-that apply in on the generic device (independent from the bus).
-
-
-Required properties for the SPI bindings:
- - compatible: should be set to "st,lis3lv02d-spi"
- - reg: the chipselect index
- - spi-max-frequency: maximal bus speed, should be set to 1000000 unless
- constrained by external circuitry
- - interrupts: the interrupt generated by the device
-
-Required properties for the I2C bindings:
- - compatible: should be set to "st,lis3lv02d"
- - reg: i2c slave address
- - Vdd-supply: The input supply for Vdd
- - Vdd_IO-supply: The input supply for Vdd_IO
-
-
-Optional properties for all bus drivers:
-
- - st,click-single-{x,y,z}: if present, tells the device to issue an
- interrupt on single click events on the
- x/y/z axis.
- - st,click-double-{x,y,z}: if present, tells the device to issue an
- interrupt on double click events on the
- x/y/z axis.
- - st,click-thresh-{x,y,z}: set the x/y/z axis threshold
- - st,click-click-time-limit: click time limit, from 0 to 127.5msec
- with step of 0.5 msec
- - st,click-latency: click latency, from 0 to 255 msec with
- step of 1 msec.
- - st,click-window: click window, from 0 to 255 msec with
- step of 1 msec.
- - st,irq{1,2}-disable: disable IRQ 1/2
- - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition
- - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition
- - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready condition
- - st,irq{1,2}-click: raise IRQ 1/2 on click condition
- - st,irq-open-drain: consider IRQ lines open-drain
- - st,irq-active-low: make IRQ lines active low
- - st,wu-duration-1: duration register for Free-Fall/Wake-Up
- interrupt 1
- - st,wu-duration-2: duration register for Free-Fall/Wake-Up
- interrupt 2
- - st,wakeup-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for
- upper/lower limit
- - st,wakeup-threshold: set wakeup threshold
- - st,wakeup2-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for
- upper/lower limit for second wakeup
- engine.
- - st,wakeup2-threshold: set wakeup threshold for second wakeup
- engine.
- - st,highpass-cutoff-hz=: 1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of
- highpass cut-off frequency
- - st,hipass{1,2}-disable: disable highpass 1/2.
- - st,default-rate=: set the default rate
- - st,axis-{x,y,z}=: set the axis to map to the three coordinates.
- Negative values can be used for inverted axis.
- - st,{min,max}-limit-{x,y,z} set the min/max limits for x/y/z axis
- (used by self-test)
-
-
-Example for a SPI device node:
-
- accelerometer@0 {
- compatible = "st,lis302dl-spi";
- reg = <0>;
- spi-max-frequency = <1000000>;
- interrupt-parent = <&gpio>;
- interrupts = <104 0>;
-
- st,click-single-x;
- st,click-single-y;
- st,click-single-z;
- st,click-thresh-x = <10>;
- st,click-thresh-y = <10>;
- st,click-thresh-z = <10>;
- st,irq1-click;
- st,irq2-click;
- st,wakeup-x-lo;
- st,wakeup-x-hi;
- st,wakeup-y-lo;
- st,wakeup-y-hi;
- st,wakeup-z-lo;
- st,wakeup-z-hi;
- };
-
-Example for a I2C device node:
-
- lis331dlh: accelerometer@18 {
- compatible = "st,lis331dlh", "st,lis3lv02d";
- reg = <0x18>;
- Vdd-supply = <&lis3_reg>;
- Vdd_IO-supply = <&lis3_reg>;
-
- st,click-single-x;
- st,click-single-y;
- st,click-single-z;
- st,click-thresh-x = <10>;
- st,click-thresh-y = <10>;
- st,click-thresh-z = <10>;
- st,irq1-click;
- st,irq2-click;
- st,wakeup-x-lo;
- st,wakeup-x-hi;
- st,wakeup-y-lo;
- st,wakeup-y-hi;
- st,wakeup-z-lo;
- st,wakeup-z-hi;
- st,min-limit-x = <120>;
- st,min-limit-y = <120>;
- st,min-limit-z = <140>;
- st,max-limit-x = <550>;
- st,max-limit-y = <550>;
- st,max-limit-z = <750>;
- };
-
diff --git a/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml b/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
new file mode 100644
index 000000000000..85eb74c264bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
@@ -0,0 +1,396 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/st,lis3lv02d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics LIS3LV02D and similar accelerometers (misc driver)
+
+maintainers:
+ - Eric Piel <eric.piel@tremplin-utc.net>
+
+description:
+ This binding describes the STMicroelectronics accelerometers supported by
+ the misc/lis3lv02d driver. This driver provides input (joystick) and
+ hardware monitoring support, in contrast to the IIO st-accel driver which
+ also supports some of these devices.
+ Refer to Documentation/devicetree/bindings/iio/st,st-sensors.yaml for the
+ IIO binding.
+
+select:
+ anyOf:
+ - properties:
+ compatible:
+ contains:
+ const: st,lis302dl-spi
+ - properties:
+ compatible:
+ contains:
+ const: st,lis331dlh
+ - properties:
+ compatible:
+ contains:
+ const: st,lis33de
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - st,lis331dlh
+ - st,lis33de
+ - const: st,lis3lv02d
+ - const: st,lis331dlh
+ - const: st,lis3lv02d
+ - const: st,lis302dl-spi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ spi-max-frequency:
+ description: SPI bus frequency; should be set to 1000000 unless
+ constrained by external circuitry.
+ maximum: 1000000
+
+ Vdd-supply:
+ description: The input supply for Vdd.
+
+ Vdd_IO-supply:
+ description: The input supply for Vdd_IO.
+
+ st,click-single-x:
+ description: Issue an interrupt on single click events on the X axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-double-x:
+ description: Issue an interrupt on double click events on the X axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-single-y:
+ description: Issue an interrupt on single click events on the Y axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-double-y:
+ description: Issue an interrupt on double click events on the Y axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-single-z:
+ description: Issue an interrupt on single click events on the Z axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-double-z:
+ description: Issue an interrupt on double click events on the Z axis.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,click-thresh-x:
+ description: X axis click threshold (deprecated spelling, use st,click-threshold-x).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
+
+ st,click-thresh-y:
+ description: Y axis click threshold (deprecated spelling, use st,click-threshold-y).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
+
+ st,click-thresh-z:
+ description: Z axis click threshold (deprecated spelling, use st,click-threshold-z).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
+
+ st,click-threshold-x:
+ description: X axis click threshold.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,click-threshold-y:
+ description: Y axis click threshold.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,click-threshold-z:
+ description: Z axis click threshold.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,click-click-time-limit:
+ description: Click time limit (deprecated spelling, use st,click-time-limit).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+ deprecated: true
+
+ st,click-time-limit:
+ description: Click time limit, from 0 to 127.5 msec with step of 0.5 msec.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,click-latency:
+ description: Click latency, from 0 to 255 msec with step of 1 msec.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,click-window:
+ description: Click window, from 0 to 255 msec with step of 1 msec.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,irq1-disable:
+ description: Disable IRQ 1.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq1-ff-wu-1:
+ description: Raise IRQ 1 on FF_WU_1 condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq1-ff-wu-2:
+ description: Raise IRQ 1 on FF_WU_2 condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq1-data-ready:
+ description: Raise IRQ 1 on data ready condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq1-click:
+ description: Raise IRQ 1 on click condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-disable:
+ description: Disable IRQ 2.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-ff-wu-1:
+ description: Raise IRQ 2 on FF_WU_1 condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-ff-wu-2:
+ description: Raise IRQ 2 on FF_WU_2 condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-data-ready:
+ description: Raise IRQ 2 on data ready condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq2-click:
+ description: Raise IRQ 2 on click condition.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq-open-drain:
+ description: Consider IRQ lines open-drain.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,irq-active-low:
+ description: Make IRQ lines active low.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wu-duration-1:
+ description: Duration register for Free-Fall/Wake-Up interrupt 1.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,wu-duration-2:
+ description: Duration register for Free-Fall/Wake-Up interrupt 2.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,wakeup-x-lo:
+ description: Set wakeup condition on X axis for lower limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-x-hi:
+ description: Set wakeup condition on X axis for upper limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-y-lo:
+ description: Set wakeup condition on Y axis for lower limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-y-hi:
+ description: Set wakeup condition on Y axis for upper limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-z-lo:
+ description: Set wakeup condition on Z axis for lower limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-z-hi:
+ description: Set wakeup condition on Z axis for upper limit.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup-threshold:
+ description: Set wakeup threshold.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,wakeup2-x-lo:
+ description: Set wakeup condition on X axis for lower limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-x-hi:
+ description: Set wakeup condition on X axis for upper limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-y-lo:
+ description: Set wakeup condition on Y axis for lower limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-y-hi:
+ description: Set wakeup condition on Y axis for upper limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-z-lo:
+ description: Set wakeup condition on Z axis for lower limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-z-hi:
+ description: Set wakeup condition on Z axis for upper limit for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,wakeup2-threshold:
+ description: Set wakeup threshold for second wakeup engine.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+
+ st,highpass-cutoff-hz:
+ description: Highpass cut-off frequency. Valid values are 1, 2, 4 or 8.
+ enum: [1, 2, 4, 8]
+
+ st,hipass1-disable:
+ description: Disable highpass filter 1.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,hipass2-disable:
+ description: Disable highpass filter 2.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,default-rate:
+ description: Set the default output data rate.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,axis-x:
+ description: Set the X axis mapping. Negative values can be used for inverted axis.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,axis-y:
+ description: Set the Y axis mapping. Negative values can be used for inverted axis.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,axis-z:
+ description: Set the Z axis mapping. Negative values can be used for inverted axis.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,min-limit-x:
+ description: Minimum limit for X axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,min-limit-y:
+ description: Minimum limit for Y axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,min-limit-z:
+ description: Minimum limit for Z axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,max-limit-x:
+ description: Maximum limit for X axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,max-limit-y:
+ description: Maximum limit for Y axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ st,max-limit-z:
+ description: Maximum limit for Z axis (used by self-test).
+ $ref: /schemas/types.yaml#/definitions/int32
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: st,lis302dl-spi
+ then:
+ required:
+ - Vdd-supply
+ - Vdd_IO-supply
+ else:
+ properties:
+ Vdd-supply: false
+ Vdd_IO-supply: false
+ required:
+ - spi-max-frequency
+ - interrupts
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@18 {
+ compatible = "st,lis331dlh", "st,lis3lv02d";
+ reg = <0x18>;
+ Vdd-supply = <&lis3_reg>;
+ Vdd_IO-supply = <&lis3_reg>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <18 0>;
+
+ st,click-single-x;
+ st,click-single-y;
+ st,click-single-z;
+ st,click-threshold-x = <10>;
+ st,click-threshold-y = <10>;
+ st,click-threshold-z = <10>;
+ st,irq1-click;
+ st,irq2-click;
+ st,wakeup-x-lo;
+ st,wakeup-x-hi;
+ st,wakeup-y-lo;
+ st,wakeup-y-hi;
+ st,wakeup-z-lo;
+ st,wakeup-z-hi;
+ st,min-limit-x = <120>;
+ st,min-limit-y = <120>;
+ st,min-limit-z = <140>;
+ st,max-limit-x = <550>;
+ st,max-limit-y = <550>;
+ st,max-limit-z = <750>;
+ };
+ };
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@0 {
+ compatible = "st,lis302dl-spi";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <104 0>;
+
+ st,click-single-x;
+ st,click-single-y;
+ st,click-single-z;
+ st,click-threshold-x = <10>;
+ st,click-threshold-y = <10>;
+ st,click-threshold-z = <10>;
+ st,irq1-click;
+ st,irq2-click;
+ st,wakeup-x-lo;
+ st,wakeup-x-hi;
+ st,wakeup-y-lo;
+ st,wakeup-y-hi;
+ st,wakeup-z-lo;
+ st,wakeup-z-hi;
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 9ec290e38b44..4cffabbabf0e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14858,6 +14858,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/
LIS3LV02D ACCELEROMETER DRIVER
M: Eric Piel <eric.piel@tremplin-utc.net>
S: Maintained
+F: Documentation/devicetree/bindings/misc/st,lis3lv02d.yaml
F: Documentation/misc-devices/lis3lv02d.rst
F: drivers/misc/lis3lv02d/
F: drivers/platform/x86/hp/hp_accel.c
--
2.54.0
^ permalink raw reply related
* Re: [PATCH 4/5] hwmon: add Stratix 10 SoC FPGA hardware monitor driver
From: sashiko-bot @ 2026-06-19 11:55 UTC (permalink / raw)
To: tze.yee.ng; +Cc: robh, devicetree, linux-hwmon, conor+dt
In-Reply-To: <081650bc4d92e9497b7a5a926e79a067cca3519f.1781861409.git.tze.yee.ng@altera.com>
Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] Use-After-Free due to improper devm lifecycle management during module removal.
- [High] Negative temperatures are miscalculated as massive positive values due to an implicit unsigned arithmetic promotion.
- [High] Synchronous read timeouts abandon requests in the FIFO, permanently desynchronizing responses.
- [Medium] Synchronous reads silently mask hardware failures and return stale sensor data instead of errors.
- [Low] Improper initialization of a stack-allocated completion variable.
- [Low] Incorrect error code returned for hardware failure.
--
commit 6b98d9d7f6f87d18500b9518e6aa77d54c53dc50
Author: Tze Yee Ng <tze.yee.ng@altera.com>
Subject: hwmon: add Stratix 10 SoC FPGA hardware monitor driver
This commit adds a hardware monitoring driver for Altera Stratix 10 SoC FPGA
devices. It supports reading temperature and voltage sensors via the Stratix
10 service layer. The driver defaults to asynchronous interfaces but falls
back to synchronous reads if necessary.
> diff --git a/drivers/hwmon/stratix10-hwmon.c b/drivers/hwmon/stratix10-hwmon.c
> new file mode 100644
> index 0000000000000..7ed1116e57b87
> --- /dev/null
> +++ b/drivers/hwmon/stratix10-hwmon.c
> @@ -0,0 +1,575 @@
[ ... ]
> +#define STRATIX10_HWMON_ATTR_VISIBLE 0444
> +/* Temperature from SDM is signed Q8.8 millidegrees Celsius (8 fractional bits). */
> +#define STRATIX10_HWMON_TEMP_FRAC_BITS 8
> +#define STRATIX10_HWMON_TEMP_FRAC_DIV BIT(STRATIX10_HWMON_TEMP_FRAC_BITS)
> +/* Voltage from SDM is unsigned Q16 (millivolts, 16 fractional bits). */
[ ... ]
> +static int stratix10_hwmon_parse_temp(long *val, u32 temperature)
> +{
> + switch (temperature) {
> + case ETEMP_INACTIVE:
> + case ETEMP_NOT_PRESENT:
> + case ETEMP_CORRUPT:
> + case ETEMP_NOT_INITIALIZED:
> + return -EOPNOTSUPP;
> + case ETEMP_TIMEOUT:
> + case ETEMP_BUSY:
> + case ETEMP_TOO_OLD:
> + return -EAGAIN;
> + default:
> + /* Convert Q8.8 millidegrees Celsius to millidegrees for hwmon. */
> + *val = (long)(s32)temperature / STRATIX10_HWMON_TEMP_FRAC_DIV;
[Severity: High]
Will negative temperatures be miscalculated as massive positive values here?
The macro STRATIX10_HWMON_TEMP_FRAC_DIV is defined using BIT(), which expands
to an unsigned long literal.
When dividing a signed long by an unsigned long, C promotion rules convert
the signed operand to unsigned. This means a negative temperature is converted
into a huge positive integer prior to division, entirely corrupting the
resulting sensor reading.
[ ... ]
> +static int stratix10_hwmon_async_read(struct device *dev,
> + enum hwmon_sensor_types type,
> + struct stratix10_svc_client_msg *msg)
> +{
> + struct stratix10_hwmon_priv *priv = dev_get_drvdata(dev);
> + struct stratix10_svc_cb_data data = {};
> + struct completion completion;
> + unsigned long wait_ret;
> + void *handle = NULL;
> + int status, index, ret;
> +
> + init_completion(&completion);
[Severity: Low]
Should this use init_completion_onstack() instead?
Initializing a stack-allocated completion with init_completion() can trigger
false positive circular locking dependency warnings from lockdep.
[ ... ]
> + if (ret) {
> + dev_err(dev, "Failed to get async response\n");
> + goto done;
> + }
> +
> + if (data.status) {
> + dev_err(dev, "%s returned 0x%x from SDM\n", __func__,
> + data.status);
> + ret = -EFAULT;
[Severity: Low]
Is -EFAULT the correct error code here?
In the kernel, -EFAULT typically denotes a bad user-space memory address.
Returning it for a hardware or firmware failure incorrectly implies that
user-space passed a bad pointer to a syscall. A more standard error code
such as -EIO or -ENODATA might be more appropriate.
> + goto done;
> + }
[ ... ]
> +static int stratix10_hwmon_sync_read(struct device *dev,
> + enum hwmon_sensor_types type,
> + struct stratix10_svc_client_msg *msg)
> +{
> + struct stratix10_hwmon_priv *priv = dev_get_drvdata(dev);
> + int ret;
> +
> + reinit_completion(&priv->completion);
> +
> + if (type == hwmon_temp)
> + priv->client.receive_cb = stratix10_hwmon_readtemp_cb;
> + else
> + priv->client.receive_cb = stratix10_hwmon_readvolt_cb;
> +
> + ret = stratix10_svc_send(priv->chan, msg);
> + if (ret < 0)
> + goto status_done;
> +
> + ret = wait_for_completion_interruptible_timeout(&priv->completion,
> + HWMON_TIMEOUT);
> + if (!ret) {
> + dev_err(priv->client.dev, "timeout waiting for SMC call\n");
> + ret = -ETIMEDOUT;
> + goto status_done;
> + }
[Severity: High]
Does a timeout here permanently desynchronize responses?
The timeout path abandons the unread request in chan->svc_fifo without
flushing it.
When a subsequent sysfs read triggers a new request, a new kthread is spawned
and immediately pops the abandoned request off the queue. When the response
arrives, the driver signals the new read's completion with the old read's
data, permanently shifting all subsequent reads.
> + if (ret < 0) {
> + dev_err(priv->client.dev, "error %d waiting for SMC call\n", ret);
> + goto status_done;
> + }
> +
> + ret = 0;
> +
> +status_done:
> + stratix10_svc_done(priv->chan);
> + return ret;
> +}
[Severity: Medium]
Could this silently mask hardware failures?
If the transaction completes but the hardware rejects the command,
stratix10_hwmon_readtemp_cb() logs an error without modifying the cached
temperature or storing an error state.
This function then unconditionally returns 0 (success), causing the driver
to return the previously cached stale sensor value to user-space instead
of returning an error code.
[ ... ]
> +static void stratix10_hwmon_remove(struct platform_device *pdev)
> +{
> + struct stratix10_hwmon_priv *priv = platform_get_drvdata(pdev);
> +
> + if (priv->async)
> + stratix10_svc_remove_async_client(priv->chan);
> + stratix10_svc_free_channel(priv->chan);
> +}
[Severity: High]
Can this result in a use-after-free crash during module unbind?
The sysfs attributes are registered using
devm_hwmon_device_register_with_info(), so they are removed by devres only
after this remove function returns.
Freeing the SVC channel manually here creates a race condition window where
the sysfs files are still active and readable, but the backend channel has
been destroyed. A concurrent sysfs read during driver unbinding will access
the freed channel.
Should the channel teardown be deferred using devm_add_action_or_reset()?
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1781861409.git.tze.yee.ng@altera.com?part=4
^ permalink raw reply
* [PATCH v5 0/3] regulator: Add support for Unisoc SC2730 PMIC regulators
From: Otto Pflüger @ 2026-06-19 11:41 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang, Lee Jones
Cc: linux-kernel, devicetree, Otto Pflüger, Krzysztof Kozlowski,
Zhongfa Wang
Add device tree bindings and a driver for the regulators found in the
Spreadtrum/Unisoc SC2730 PMIC.
Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
---
Changes in v5:
- Drop conditional binding patch, will be sent separately
- Rebase on next-20260618
- Link to v4: https://lore.kernel.org/r/20260521-sc2730-regulators-v4-0-1ac8a3b5ed82@abscue.de
Changes in v4:
- Add missing patch for MFD cell registration
- Use conditional binding for referencing the regulators now that the
child node cannot be distinguished by its compatible for validation
purposes.
- Drop requirement for removed compatible property (sorry, should have
double-checked this before sending v3)
- Link to v3: https://lore.kernel.org/r/20260519-sc2730-regulators-v3-0-5bf0e02507e3@abscue.de
Changes in v3:
- Drop compatible property
- Drop unused VDDSIM0 and VDDSIM1 IDs
- Link to v2: https://lore.kernel.org/r/20260518-sc2730-regulators-v2-0-9a5b3a7b1e49@abscue.de
Changes in v2:
- Use lowercase names without underscores for device tree nodes
- Use oneOf for binding reference instead of making it conditional
- Remove some excess line breaks
- Fix author name in driver and add original Signed-off-by
- Link to v1: https://lore.kernel.org/r/20260220-sc2730-regulators-v1-0-3f2bbc9ecf14@abscue.de
---
Otto Pflüger (3):
regulator: dt-bindings: Add Unisoc SC2730 PMIC
mfd: sprd-sc27xx: Add SC2730 regulator cell
regulator: Add regulator driver for Unisoc SC2730 PMIC
.../bindings/regulator/sprd,sc2730-regulator.yaml | 44 +++
drivers/mfd/sprd-sc27xx-spi.c | 1 +
drivers/regulator/Kconfig | 7 +
drivers/regulator/Makefile | 1 +
drivers/regulator/sc2730-regulator.c | 411 +++++++++++++++++++++
5 files changed, 464 insertions(+)
---
base-commit: 598c7067dd8b65b93f3ccada47e9014a13137f1b
change-id: 20260216-sc2730-regulators-13ba789641a4
Best regards,
--
Otto Pflüger <otto.pflueger@abscue.de>
^ permalink raw reply
* [PATCH v5 1/3] regulator: dt-bindings: Add Unisoc SC2730 PMIC
From: Otto Pflüger @ 2026-06-19 11:41 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang, Lee Jones
Cc: linux-kernel, devicetree, Otto Pflüger, Krzysztof Kozlowski
In-Reply-To: <20260619-sc2730-regulators-v5-0-0a24c7ed7a97@abscue.de>
Add bindings for the regulators found in the Spreadtrum/Unisoc SC2730
PMIC, used e.g. with the UMS512 and UMS9230 SoCs.
Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../bindings/regulator/sprd,sc2730-regulator.yaml | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml b/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml
new file mode 100644
index 000000000000..ab945c46b08e
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/sprd,sc2730-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc SC2730 Power Management IC regulators
+
+maintainers:
+ - Otto Pflüger <otto.pflueger@abscue.de>
+
+patternProperties:
+ "^dcdc-(core|cpu|gen[0-1]|gpu|mem|memq|modem|sram)$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ "^ldo-avdd(12|18)$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ "^ldo-vdd(18-dcxo|28)$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ "^ldo-vdd(emmccore|kpled|ldo[0-2]|sd(core|io)|sim[0-2]|usb33|wcn|wifipa)$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ "^ldo-vddcam(a0|a1|d0|d1|io|mot)$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ "^ldo-vddrf(1v25|18)$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+additionalProperties: false
+...
--
2.51.0
^ permalink raw reply related
* [PATCH v5 3/3] regulator: Add regulator driver for Unisoc SC2730 PMIC
From: Otto Pflüger @ 2026-06-19 11:41 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang, Lee Jones
Cc: linux-kernel, devicetree, Otto Pflüger, Zhongfa Wang
In-Reply-To: <20260619-sc2730-regulators-v5-0-0a24c7ed7a97@abscue.de>
Add a regulator driver for the Spreadtrum/Unisoc SC2730 PMIC, used
e.g. with the UMS512 and UMS9230 SoCs. This version of the driver is
based on a downstream driver provided by Unisoc [1][2] and the existing
SC2731 driver.
[1]: https://github.com/MotorolaMobilityLLC/kernel-sprd/commit/30be0ddfe6b9a877fc9c328fbd2bae84e645eb31
[2]: https://github.com/MotorolaMobilityLLC/kernel-sprd/blob/android-13-release-tla33/drivers/regulator/sc2730-regulator.c
Signed-off-by: Zhongfa Wang <zhongfa.wang@unisoc.com>
[cleanup, adapt to new device tree requirements]
Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
---
Note regarding the AI bot comment:
According to a different register table, the register at offset 0x28 is
called ANA_GLB_RESERVED_REG0. While I do not have access to any
documentation to confirm the functionality of that register, it seems
that it is being used here intentionally.
---
drivers/regulator/Kconfig | 7 +
drivers/regulator/Makefile | 1 +
drivers/regulator/sc2730-regulator.c | 411 +++++++++++++++++++++++++++++++++++
3 files changed, 419 insertions(+)
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index a54a549196fe..89789ac7a786 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -1477,6 +1477,13 @@ config REGULATOR_S5M8767
via I2C bus. S5M8767A have 9 Bucks and 28 LDOs output and
supports DVS mode with 8bits of output voltage control.
+config REGULATOR_SC2730
+ tristate "Spreadtrum SC2730 power regulator driver"
+ depends on MFD_SC27XX_PMIC || COMPILE_TEST
+ help
+ This driver provides support for the voltage regulators on the
+ SC2730 PMIC.
+
config REGULATOR_SC2731
tristate "Spreadtrum SC2731 power regulator driver"
depends on MFD_SC27XX_PMIC || COMPILE_TEST
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 134eee274dbf..5a764cec8df8 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -170,6 +170,7 @@ obj-$(CONFIG_REGULATOR_S2DOS05) += s2dos05-regulator.o
obj-$(CONFIG_REGULATOR_S2MPA01) += s2mpa01.o
obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
+obj-$(CONFIG_REGULATOR_SC2730) += sc2730-regulator.o
obj-$(CONFIG_REGULATOR_SC2731) += sc2731-regulator.o
obj-$(CONFIG_REGULATOR_SGM3804) += sgm3804-regulator.o
obj-$(CONFIG_REGULATOR_SKY81452) += sky81452-regulator.o
diff --git a/drivers/regulator/sc2730-regulator.c b/drivers/regulator/sc2730-regulator.c
new file mode 100644
index 000000000000..9e40c6eae494
--- /dev/null
+++ b/drivers/regulator/sc2730-regulator.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2021 Unisoc Inc.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+/*
+ * SC2730 regulator base address
+ */
+#define SC2730_REGULATOR_BASE 0x1800
+
+/*
+ * SC2730 regulator lock register
+ */
+#define SC2730_WR_UNLOCK_VALUE 0x6e7f
+#define SC2730_PWR_WR_PROT (SC2730_REGULATOR_BASE + 0x3d0)
+
+/*
+ * SC2730 enable register
+ */
+#define SC2730_POWER_PD_SW (SC2730_REGULATOR_BASE + 0x01c)
+#define SC2730_LDO_VDDRF18_PD (SC2730_REGULATOR_BASE + 0x10c)
+#define SC2730_LDO_VDDCAMIO_PD (SC2730_REGULATOR_BASE + 0x118)
+#define SC2730_LDO_VDDWCN_PD (SC2730_REGULATOR_BASE + 0x11c)
+#define SC2730_LDO_VDDCAMD1_PD (SC2730_REGULATOR_BASE + 0x128)
+#define SC2730_LDO_VDDCAMD0_PD (SC2730_REGULATOR_BASE + 0x134)
+#define SC2730_LDO_VDDRF1V25_PD (SC2730_REGULATOR_BASE + 0x140)
+#define SC2730_LDO_AVDD12_PD (SC2730_REGULATOR_BASE + 0x14c)
+#define SC2730_LDO_VDDCAMA0_PD (SC2730_REGULATOR_BASE + 0x158)
+#define SC2730_LDO_VDDCAMA1_PD (SC2730_REGULATOR_BASE + 0x164)
+#define SC2730_LDO_VDDCAMMOT_PD (SC2730_REGULATOR_BASE + 0x170)
+#define SC2730_LDO_VDDSIM2_PD (SC2730_REGULATOR_BASE + 0x194)
+#define SC2730_LDO_VDDEMMCCORE_PD (SC2730_REGULATOR_BASE + 0x1a0)
+#define SC2730_LDO_VDDSDCORE_PD (SC2730_REGULATOR_BASE + 0x1ac)
+#define SC2730_LDO_VDDSDIO_PD (SC2730_REGULATOR_BASE + 0x1b8)
+#define SC2730_LDO_VDDWIFIPA_PD (SC2730_REGULATOR_BASE + 0x1d0)
+#define SC2730_LDO_VDDUSB33_PD (SC2730_REGULATOR_BASE + 0x1e8)
+#define SC2730_LDO_VDDLDO0_PD (SC2730_REGULATOR_BASE + 0x1f4)
+#define SC2730_LDO_VDDLDO1_PD (SC2730_REGULATOR_BASE + 0x200)
+#define SC2730_LDO_VDDLDO2_PD (SC2730_REGULATOR_BASE + 0x20c)
+#define SC2730_LDO_VDDKPLED_PD (SC2730_REGULATOR_BASE + 0x38c)
+
+/*
+ * SC2730 enable mask
+ */
+#define SC2730_DCDC_CPU_PD_MASK BIT(4)
+#define SC2730_DCDC_GPU_PD_MASK BIT(3)
+#define SC2730_DCDC_CORE_PD_MASK BIT(5)
+#define SC2730_DCDC_MODEM_PD_MASK BIT(11)
+#define SC2730_DCDC_MEM_PD_MASK BIT(6)
+#define SC2730_DCDC_MEMQ_PD_MASK BIT(12)
+#define SC2730_DCDC_GEN0_PD_MASK BIT(8)
+#define SC2730_DCDC_GEN1_PD_MASK BIT(7)
+#define SC2730_DCDC_SRAM_PD_MASK BIT(13)
+#define SC2730_LDO_AVDD18_PD_MASK BIT(2)
+#define SC2730_LDO_VDDRF18_PD_MASK BIT(0)
+#define SC2730_LDO_VDDCAMIO_PD_MASK BIT(0)
+#define SC2730_LDO_VDDWCN_PD_MASK BIT(0)
+#define SC2730_LDO_VDDCAMD1_PD_MASK BIT(0)
+#define SC2730_LDO_VDDCAMD0_PD_MASK BIT(0)
+#define SC2730_LDO_VDDRF1V25_PD_MASK BIT(0)
+#define SC2730_LDO_AVDD12_PD_MASK BIT(0)
+#define SC2730_LDO_VDDCAMA0_PD_MASK BIT(0)
+#define SC2730_LDO_VDDCAMA1_PD_MASK BIT(0)
+#define SC2730_LDO_VDDCAMMOT_PD_MASK BIT(0)
+#define SC2730_LDO_VDDSIM2_PD_MASK BIT(0)
+#define SC2730_LDO_VDDEMMCCORE_PD_MASK BIT(0)
+#define SC2730_LDO_VDDSDCORE_PD_MASK BIT(0)
+#define SC2730_LDO_VDDSDIO_PD_MASK BIT(0)
+#define SC2730_LDO_VDD28_PD_MASK BIT(1)
+#define SC2730_LDO_VDDWIFIPA_PD_MASK BIT(0)
+#define SC2730_LDO_VDD18_DCXO_PD_MASK BIT(10)
+#define SC2730_LDO_VDDUSB33_PD_MASK BIT(0)
+#define SC2730_LDO_VDDLDO0_PD_MASK BIT(0)
+#define SC2730_LDO_VDDLDO1_PD_MASK BIT(0)
+#define SC2730_LDO_VDDLDO2_PD_MASK BIT(0)
+#define SC2730_LDO_VDDKPLED_PD_MASK BIT(15)
+
+/*
+ * SC2730 vsel register
+ */
+#define SC2730_DCDC_CPU_VOL (SC2730_REGULATOR_BASE + 0x44)
+#define SC2730_DCDC_GPU_VOL (SC2730_REGULATOR_BASE + 0x54)
+#define SC2730_DCDC_CORE_VOL (SC2730_REGULATOR_BASE + 0x64)
+#define SC2730_DCDC_MODEM_VOL (SC2730_REGULATOR_BASE + 0x74)
+#define SC2730_DCDC_MEM_VOL (SC2730_REGULATOR_BASE + 0x84)
+#define SC2730_DCDC_MEMQ_VOL (SC2730_REGULATOR_BASE + 0x94)
+#define SC2730_DCDC_GEN0_VOL (SC2730_REGULATOR_BASE + 0xa4)
+#define SC2730_DCDC_GEN1_VOL (SC2730_REGULATOR_BASE + 0xb4)
+#define SC2730_DCDC_SRAM_VOL (SC2730_REGULATOR_BASE + 0xdc)
+#define SC2730_LDO_AVDD18_VOL (SC2730_REGULATOR_BASE + 0x104)
+#define SC2730_LDO_VDDRF18_VOL (SC2730_REGULATOR_BASE + 0x110)
+#define SC2730_LDO_VDDCAMIO_VOL (SC2730_REGULATOR_BASE + 0x28)
+#define SC2730_LDO_VDDWCN_VOL (SC2730_REGULATOR_BASE + 0x120)
+#define SC2730_LDO_VDDCAMD1_VOL (SC2730_REGULATOR_BASE + 0x12c)
+#define SC2730_LDO_VDDCAMD0_VOL (SC2730_REGULATOR_BASE + 0x138)
+#define SC2730_LDO_VDDRF1V25_VOL (SC2730_REGULATOR_BASE + 0x144)
+#define SC2730_LDO_AVDD12_VOL (SC2730_REGULATOR_BASE + 0x150)
+#define SC2730_LDO_VDDCAMA0_VOL (SC2730_REGULATOR_BASE + 0x15c)
+#define SC2730_LDO_VDDCAMA1_VOL (SC2730_REGULATOR_BASE + 0x168)
+#define SC2730_LDO_VDDCAMMOT_VOL (SC2730_REGULATOR_BASE + 0x174)
+#define SC2730_LDO_VDDSIM2_VOL (SC2730_REGULATOR_BASE + 0x198)
+#define SC2730_LDO_VDDEMMCCORE_VOL (SC2730_REGULATOR_BASE + 0x1a4)
+#define SC2730_LDO_VDDSDCORE_VOL (SC2730_REGULATOR_BASE + 0x1b0)
+#define SC2730_LDO_VDDSDIO_VOL (SC2730_REGULATOR_BASE + 0x1bc)
+#define SC2730_LDO_VDD28_VOL (SC2730_REGULATOR_BASE + 0x1c8)
+#define SC2730_LDO_VDDWIFIPA_VOL (SC2730_REGULATOR_BASE + 0x1d4)
+#define SC2730_LDO_VDD18_DCXO_VOL (SC2730_REGULATOR_BASE + 0x1e0)
+#define SC2730_LDO_VDDUSB33_VOL (SC2730_REGULATOR_BASE + 0x1ec)
+#define SC2730_LDO_VDDLDO0_VOL (SC2730_REGULATOR_BASE + 0x1f8)
+#define SC2730_LDO_VDDLDO1_VOL (SC2730_REGULATOR_BASE + 0x204)
+#define SC2730_LDO_VDDLDO2_VOL (SC2730_REGULATOR_BASE + 0x210)
+#define SC2730_LDO_VDDKPLED_VOL (SC2730_REGULATOR_BASE + 0x38c)
+
+/*
+ * SC2730 vsel register mask
+ */
+#define SC2730_DCDC_CPU_VOL_MASK GENMASK(8, 0)
+#define SC2730_DCDC_GPU_VOL_MASK GENMASK(8, 0)
+#define SC2730_DCDC_CORE_VOL_MASK GENMASK(8, 0)
+#define SC2730_DCDC_MODEM_VOL_MASK GENMASK(8, 0)
+#define SC2730_DCDC_MEM_VOL_MASK GENMASK(7, 0)
+#define SC2730_DCDC_MEMQ_VOL_MASK GENMASK(8, 0)
+#define SC2730_DCDC_GEN0_VOL_MASK GENMASK(7, 0)
+#define SC2730_DCDC_GEN1_VOL_MASK GENMASK(7, 0)
+#define SC2730_DCDC_SRAM_VOL_MASK GENMASK(8, 0)
+#define SC2730_LDO_AVDD18_VOL_MASK GENMASK(5, 0)
+#define SC2730_LDO_VDDRF18_VOL_MASK GENMASK(5, 0)
+#define SC2730_LDO_VDDCAMIO_VOL_MASK GENMASK(5, 0)
+#define SC2730_LDO_VDDWCN_VOL_MASK GENMASK(5, 0)
+#define SC2730_LDO_VDDCAMD1_VOL_MASK GENMASK(4, 0)
+#define SC2730_LDO_VDDCAMD0_VOL_MASK GENMASK(4, 0)
+#define SC2730_LDO_VDDRF1V25_VOL_MASK GENMASK(4, 0)
+#define SC2730_LDO_AVDD12_VOL_MASK GENMASK(4, 0)
+#define SC2730_LDO_VDDCAMA0_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDCAMA1_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDCAMMOT_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDSIM2_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDEMMCCORE_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDSDCORE_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDSDIO_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDD28_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDWIFIPA_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDD18_DCXO_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDUSB33_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDLDO0_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDLDO1_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDLDO2_VOL_MASK GENMASK(7, 0)
+#define SC2730_LDO_VDDKPLED_VOL_MASK GENMASK(14, 7)
+
+enum sc2730_regulator_id {
+ SC2730_DCDC_CPU,
+ SC2730_DCDC_GPU,
+ SC2730_DCDC_CORE,
+ SC2730_DCDC_MODEM,
+ SC2730_DCDC_MEM,
+ SC2730_DCDC_MEMQ,
+ SC2730_DCDC_GEN0,
+ SC2730_DCDC_GEN1,
+ SC2730_DCDC_SRAM,
+ SC2730_LDO_AVDD18,
+ SC2730_LDO_VDDRF18,
+ SC2730_LDO_VDDCAMIO,
+ SC2730_LDO_VDDWCN,
+ SC2730_LDO_VDDCAMD1,
+ SC2730_LDO_VDDCAMD0,
+ SC2730_LDO_VDDRF1V25,
+ SC2730_LDO_AVDD12,
+ SC2730_LDO_VDDCAMA0,
+ SC2730_LDO_VDDCAMA1,
+ SC2730_LDO_VDDCAMMOT,
+ SC2730_LDO_VDDSIM2,
+ SC2730_LDO_VDDEMMCCORE,
+ SC2730_LDO_VDDSDCORE,
+ SC2730_LDO_VDDSDIO,
+ SC2730_LDO_VDD28,
+ SC2730_LDO_VDDWIFIPA,
+ SC2730_LDO_VDD18_DCXO,
+ SC2730_LDO_VDDUSB33,
+ SC2730_LDO_VDDLDO0,
+ SC2730_LDO_VDDLDO1,
+ SC2730_LDO_VDDLDO2,
+ SC2730_LDO_VDDKPLED,
+};
+
+static const struct regulator_ops sc2730_regu_linear_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .list_voltage = regulator_list_voltage_linear,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+};
+
+#define SC2730_REGU_LINEAR(_id, of_name, en_reg, en_mask, vreg, vmask, \
+ vstep, vmin, vmax, min_sel) { \
+ .name = #_id, \
+ .of_match = of_name, \
+ .regulators_node = "regulators", \
+ .ops = &sc2730_regu_linear_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = SC2730_##_id, \
+ .owner = THIS_MODULE, \
+ .min_uV = vmin, \
+ .n_voltages = ((vmax) - (vmin)) / (vstep) + 1, \
+ .uV_step = vstep, \
+ .enable_is_inverted = true, \
+ .enable_val = 0, \
+ .enable_reg = en_reg, \
+ .enable_mask = en_mask, \
+ .vsel_reg = vreg, \
+ .vsel_mask = vmask, \
+ .linear_min_sel = min_sel, \
+}
+
+static const struct regulator_desc regulators[] = {
+ SC2730_REGU_LINEAR(DCDC_CPU, "dcdc-cpu", SC2730_POWER_PD_SW,
+ SC2730_DCDC_CPU_PD_MASK, SC2730_DCDC_CPU_VOL,
+ SC2730_DCDC_CPU_VOL_MASK, 3125, 0, 1596875,
+ 0),
+ SC2730_REGU_LINEAR(DCDC_GPU, "dcdc-gpu", SC2730_POWER_PD_SW,
+ SC2730_DCDC_GPU_PD_MASK, SC2730_DCDC_GPU_VOL,
+ SC2730_DCDC_GPU_VOL_MASK, 3125, 0, 1596875,
+ 0),
+ SC2730_REGU_LINEAR(DCDC_CORE, "dcdc-core", SC2730_POWER_PD_SW,
+ SC2730_DCDC_CORE_PD_MASK, SC2730_DCDC_CORE_VOL,
+ SC2730_DCDC_CORE_VOL_MASK, 3125, 0, 1596875,
+ 0),
+ SC2730_REGU_LINEAR(DCDC_MODEM, "dcdc-modem", SC2730_POWER_PD_SW,
+ SC2730_DCDC_MODEM_PD_MASK, SC2730_DCDC_MODEM_VOL,
+ SC2730_DCDC_MODEM_VOL_MASK, 3125, 0, 1596875,
+ 0),
+ SC2730_REGU_LINEAR(DCDC_MEM, "dcdc-mem", SC2730_POWER_PD_SW,
+ SC2730_DCDC_MEM_PD_MASK, SC2730_DCDC_MEM_VOL,
+ SC2730_DCDC_MEM_VOL_MASK, 6250, 0, 1593750,
+ 0),
+ SC2730_REGU_LINEAR(DCDC_MEMQ, "dcdc-memq", SC2730_POWER_PD_SW,
+ SC2730_DCDC_MEMQ_PD_MASK, SC2730_DCDC_MEMQ_VOL,
+ SC2730_DCDC_MEMQ_VOL_MASK, 3125, 0, 1596875,
+ 0),
+ SC2730_REGU_LINEAR(DCDC_GEN0, "dcdc-gen0", SC2730_POWER_PD_SW,
+ SC2730_DCDC_GEN0_PD_MASK, SC2730_DCDC_GEN0_VOL,
+ SC2730_DCDC_GEN0_VOL_MASK, 9375, 20000, 2410625,
+ 0),
+ SC2730_REGU_LINEAR(DCDC_GEN1, "dcdc-gen1", SC2730_POWER_PD_SW,
+ SC2730_DCDC_GEN1_PD_MASK, SC2730_DCDC_GEN1_VOL,
+ SC2730_DCDC_GEN1_VOL_MASK, 6250, 50000, 1643750,
+ 0),
+ SC2730_REGU_LINEAR(DCDC_SRAM, "dcdc-sram", SC2730_POWER_PD_SW,
+ SC2730_DCDC_SRAM_PD_MASK, SC2730_DCDC_SRAM_VOL,
+ SC2730_DCDC_SRAM_VOL_MASK, 3125, 0, 1596875,
+ 0),
+ SC2730_REGU_LINEAR(LDO_AVDD18, "ldo-avdd18", SC2730_POWER_PD_SW,
+ SC2730_LDO_AVDD18_PD_MASK, SC2730_LDO_AVDD18_VOL,
+ SC2730_LDO_AVDD18_VOL_MASK, 10000, 1175000, 1805000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDRF18, "ldo-vddrf18", SC2730_LDO_VDDRF18_PD,
+ SC2730_LDO_VDDRF18_PD_MASK, SC2730_LDO_VDDRF18_VOL,
+ SC2730_LDO_VDDRF18_VOL_MASK, 10000, 1175000, 1805000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDCAMIO, "ldo-vddcamio", SC2730_LDO_VDDCAMIO_PD,
+ SC2730_LDO_VDDCAMIO_PD_MASK, SC2730_LDO_VDDCAMIO_VOL,
+ SC2730_LDO_VDDCAMIO_VOL_MASK, 10000, 1200000, 1830000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDWCN, "ldo-vddwcn", SC2730_LDO_VDDWCN_PD,
+ SC2730_LDO_VDDWCN_PD_MASK, SC2730_LDO_VDDWCN_VOL,
+ SC2730_LDO_VDDWCN_VOL_MASK, 15000, 900000, 1845000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDCAMD1, "ldo-vddcamd1", SC2730_LDO_VDDCAMD1_PD,
+ SC2730_LDO_VDDCAMD1_PD_MASK, SC2730_LDO_VDDCAMD1_VOL,
+ SC2730_LDO_VDDCAMD1_VOL_MASK, 15000, 900000, 1365000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDCAMD0, "ldo-vddcamd0", SC2730_LDO_VDDCAMD0_PD,
+ SC2730_LDO_VDDCAMD0_PD_MASK, SC2730_LDO_VDDCAMD0_VOL,
+ SC2730_LDO_VDDCAMD0_VOL_MASK, 15000, 900000, 1365000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDRF1V25, "ldo-vddrf1v25", SC2730_LDO_VDDRF1V25_PD,
+ SC2730_LDO_VDDRF1V25_PD_MASK, SC2730_LDO_VDDRF1V25_VOL,
+ SC2730_LDO_VDDRF1V25_VOL_MASK, 15000, 900000, 1365000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_AVDD12, "ldo-avdd12", SC2730_LDO_AVDD12_PD,
+ SC2730_LDO_AVDD12_PD_MASK, SC2730_LDO_AVDD12_VOL,
+ SC2730_LDO_AVDD12_VOL_MASK, 15000, 900000, 1365000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDCAMA0, "ldo-vddcama0", SC2730_LDO_VDDCAMA0_PD,
+ SC2730_LDO_VDDCAMA0_PD_MASK, SC2730_LDO_VDDCAMA0_VOL,
+ SC2730_LDO_VDDCAMA0_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDCAMA1, "ldo-vddcama1", SC2730_LDO_VDDCAMA1_PD,
+ SC2730_LDO_VDDCAMA1_PD_MASK, SC2730_LDO_VDDCAMA1_VOL,
+ SC2730_LDO_VDDCAMA1_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDCAMMOT, "ldo-vddcammot", SC2730_LDO_VDDCAMMOT_PD,
+ SC2730_LDO_VDDCAMMOT_PD_MASK, SC2730_LDO_VDDCAMMOT_VOL,
+ SC2730_LDO_VDDCAMMOT_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDSIM2, "ldo-vddsim2", SC2730_LDO_VDDSIM2_PD,
+ SC2730_LDO_VDDSIM2_PD_MASK, SC2730_LDO_VDDSIM2_VOL,
+ SC2730_LDO_VDDSIM2_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDEMMCCORE, "ldo-vddemmccore", SC2730_LDO_VDDEMMCCORE_PD,
+ SC2730_LDO_VDDEMMCCORE_PD_MASK, SC2730_LDO_VDDEMMCCORE_VOL,
+ SC2730_LDO_VDDEMMCCORE_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDSDCORE, "ldo-vddsdcore", SC2730_LDO_VDDSDCORE_PD,
+ SC2730_LDO_VDDSDCORE_PD_MASK, SC2730_LDO_VDDSDCORE_VOL,
+ SC2730_LDO_VDDSDCORE_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDSDIO, "ldo-vddsdio", SC2730_LDO_VDDSDIO_PD,
+ SC2730_LDO_VDDSDIO_PD_MASK, SC2730_LDO_VDDSDIO_VOL,
+ SC2730_LDO_VDDSDIO_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDD28, "ldo-vdd28", SC2730_POWER_PD_SW,
+ SC2730_LDO_VDD28_PD_MASK, SC2730_LDO_VDD28_VOL,
+ SC2730_LDO_VDD28_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDWIFIPA, "ldo-vddwifipa", SC2730_LDO_VDDWIFIPA_PD,
+ SC2730_LDO_VDDWIFIPA_PD_MASK, SC2730_LDO_VDDWIFIPA_VOL,
+ SC2730_LDO_VDDWIFIPA_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDD18_DCXO, "ldo-vdd18-dcxo", SC2730_POWER_PD_SW,
+ SC2730_LDO_VDD18_DCXO_PD_MASK, SC2730_LDO_VDD18_DCXO_VOL,
+ SC2730_LDO_VDD18_DCXO_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDUSB33, "ldo-vddusb33", SC2730_LDO_VDDUSB33_PD,
+ SC2730_LDO_VDDUSB33_PD_MASK, SC2730_LDO_VDDUSB33_VOL,
+ SC2730_LDO_VDDUSB33_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDLDO0, "ldo-vddldo0", SC2730_LDO_VDDLDO0_PD,
+ SC2730_LDO_VDDLDO0_PD_MASK, SC2730_LDO_VDDLDO0_VOL,
+ SC2730_LDO_VDDLDO0_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDLDO1, "ldo-vddldo1", SC2730_LDO_VDDLDO1_PD,
+ SC2730_LDO_VDDLDO1_PD_MASK, SC2730_LDO_VDDLDO1_VOL,
+ SC2730_LDO_VDDLDO1_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDLDO2, "ldo-vddldo2", SC2730_LDO_VDDLDO2_PD,
+ SC2730_LDO_VDDLDO2_PD_MASK, SC2730_LDO_VDDLDO2_VOL,
+ SC2730_LDO_VDDLDO2_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+ SC2730_REGU_LINEAR(LDO_VDDKPLED, "ldo-vddkpled", SC2730_LDO_VDDKPLED_PD,
+ SC2730_LDO_VDDKPLED_PD_MASK, SC2730_LDO_VDDKPLED_VOL,
+ SC2730_LDO_VDDKPLED_VOL_MASK, 10000, 1200000, 3750000,
+ 0),
+};
+
+static int sc2730_regulator_unlock(struct regmap *regmap)
+{
+ return regmap_write(regmap, SC2730_PWR_WR_PROT, SC2730_WR_UNLOCK_VALUE);
+}
+
+static int sc2730_regulator_probe(struct platform_device *pdev)
+{
+ int i, ret;
+ struct regmap *regmap;
+ struct regulator_config config = { };
+ struct regulator_dev *rdev;
+
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!regmap) {
+ dev_err(&pdev->dev, "failed to get regmap.\n");
+ return -ENODEV;
+ }
+
+ ret = sc2730_regulator_unlock(regmap);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to release regulator lock\n");
+ return ret;
+ }
+
+ config.dev = pdev->dev.parent;
+ config.regmap = regmap;
+
+ for (i = 0; i < ARRAY_SIZE(regulators); i++) {
+ rdev = devm_regulator_register(&pdev->dev, ®ulators[i], &config);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "failed to register regulator %s\n",
+ regulators[i].name);
+ return PTR_ERR(rdev);
+ }
+ }
+
+ return 0;
+}
+
+static const struct platform_device_id sc2730_regulator_id_table[] = {
+ { "sc2730-regulator" },
+ { }
+};
+MODULE_DEVICE_TABLE(platform, sc2730_regulator_id_table);
+
+static struct platform_driver sc2730_regulator_driver = {
+ .driver = {
+ .name = "sc2730-regulator",
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+ .probe = sc2730_regulator_probe,
+ .id_table = sc2730_regulator_id_table,
+};
+
+module_platform_driver(sc2730_regulator_driver);
+
+MODULE_AUTHOR("Zhongfa Wang <zhongfa.wang@unisoc.com>");
+MODULE_DESCRIPTION("Spreadtrum SC2730 regulator driver");
+MODULE_LICENSE("GPL");
--
2.51.0
^ permalink raw reply related
* [PATCH v5 2/3] mfd: sprd-sc27xx: Add SC2730 regulator cell
From: Otto Pflüger @ 2026-06-19 11:41 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang, Lee Jones
Cc: linux-kernel, devicetree, Otto Pflüger
In-Reply-To: <20260619-sc2730-regulators-v5-0-0a24c7ed7a97@abscue.de>
Add an MFD cell to register the SC2730 PMIC's regulators.
Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
---
drivers/mfd/sprd-sc27xx-spi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c
index aa052f646623..214bcbef0c27 100644
--- a/drivers/mfd/sprd-sc27xx-spi.c
+++ b/drivers/mfd/sprd-sc27xx-spi.c
@@ -61,6 +61,7 @@ static const struct mfd_cell sc2730_devices[] = {
MFD_CELL_OF("sc2730-efuse", NULL, NULL, 0, 0, "sprd,sc2730-efuse"),
MFD_CELL_OF("sc2730-eic", NULL, NULL, 0, 0, "sprd,sc2730-eic"),
MFD_CELL_OF("sc2730-fgu", NULL, NULL, 0, 0, "sprd,sc2730-fgu"),
+ MFD_CELL_NAME("sc2730-regulator"),
MFD_CELL_OF("sc2730-rtc", NULL, NULL, 0, 0, "sprd,sc2730-rtc"),
MFD_CELL_OF("sc2730-vibrator", NULL, NULL, 0, 0, "sprd,sc2730-vibrator"),
};
--
2.51.0
^ permalink raw reply related
* [PATCH v5 1/1] arm64: dts: add tqma9596la-mba95xxca
From: Alexander Stein @ 2026-06-19 11:24 UTC (permalink / raw)
To: Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: Markus Niebel, imx, linux-arm-kernel, devicetree, linux-kernel,
linux, linux-renesas-soc, Alexander Stein
From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
This adds support for TQMa95xxLA modules, designed to be soldered
on a carrier board. MBa95xxCA is a carrier reference board / starter kit
design.
There is a common device tree for all variants with e.g. reduced
CPU core / feature count.
Enable the external accessible PCIe controllers as host,
add clocking and reset GPIO. While at it, add hogs for GPIO
lines from the M.2 slots until M.2 connector driver is available.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
Changes in v5:
* Limit LPSPI4 max frequency
* Replace PCIe M2 Key-E GPIO hogs with dedicated connector node
* Fix PCIe clock configuration
Changes in v4:
* Fix LPSPI4 pad muxing and control
Changes in v3:
* Moved reserved-memory to board-lebel
* Remove VPU reserved memory (unused for now)
* Fix typo in connector comment
Changes in v2:
* removed useless regulator
* added USB PD source configuration
* Removed unused uart-has-rtscts properties (unused by LPUART)
* Fixed RTS/CTS pullups in pinctrl
* Added thermalzone on module
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../freescale/imx95-tqma9596la-mba95xxca.dts | 963 ++++++++++++++++++
.../boot/dts/freescale/imx95-tqma9596la.dtsi | 278 +++++
3 files changed, 1242 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 8ddaab127ab9c..43e1dc51b11d7 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -649,6 +649,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596la-mba95xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts
new file mode 100644
index 0000000000000..4b49f6cf731da
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts
@@ -0,0 +1,963 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ * Author: Markus Niebel
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "imx95-tqma9596la.dtsi"
+
+/ {
+ model = "TQ-Systems i.MX95 TQMa95xxLA on MBa95xxCA";
+ compatible = "tq,imx95-tqma9596la-mba95xxca", "tq,imx95-tqma9596la", "fsl,imx95";
+ chassis-type = "embedded";
+
+ aliases {
+ ethernet0 = &enetc_port0;
+ ethernet1 = &enetc_port1;
+ ethernet2 = &enetc_port2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ i2c3 = &lpi2c4;
+ i2c4 = &lpi2c5;
+ i2c5 = &lpi2c6;
+ i2c6 = &lpi2c7;
+ i2c7 = &lpi2c8;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ rtc0 = &pcf85063;
+ rtc1 = &scmi_bbm;
+ serial0 = &lpuart1;
+ serial1 = &lpuart2;
+ serial2 = &lpuart3;
+ serial3 = &lpuart4;
+ serial4 = &lpuart5;
+ serial5 = &lpuart6;
+ serial6 = &lpuart7;
+ serial7 = &lpuart8;
+ spi0 = &flexspi1;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ backlight_lvds: backlight-lvds {
+ compatible = "pwm-backlight";
+ pwms = <&tpm5 2 100000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ enable-gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_12v0>;
+ status = "disabled";
+ };
+
+ clk_eth: clk-eth {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+
+ /*
+ * TODO: gate is disabled for now and GPIO are hogged
+ * ENETC driver switches the clock far too late for ENETC2 + SFP
+ */
+ clk_eth_gate: clk-eth-gate {
+ compatible = "gpio-gate-clock";
+ enable-gpios = <&expander2 0 GPIO_ACTIVE_HIGH>;
+ clocks = <&clk_eth>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ clk_xtal25: clk-xtal25 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ button-b {
+ label = "BUTTON_B#";
+ linux,code = <BTN_1>;
+ gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&expander2 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&expander2 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
+ <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
+ };
+
+ reg_v1v8_mb: regulator-v1v8-mb {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V8_MB";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_v3v3_mb: regulator-v3v3-mb {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_MB";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_3v3a_10g: regulator-3v3a-10g {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3A_10G";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander2 15 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <2000>;
+ enable-active-high;
+ };
+
+ reg_12v0: regulator-12v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "12V0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_pwm_fan: regulator-pwm-fan {
+ compatible = "regulator-fixed";
+ regulator-name = "FAN_PWR";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&expander3 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_12v0>;
+ };
+
+ reg_lvds: regulator-lvds {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD_PWR_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander2 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* USB NC limitations, RM 162.1.2 VBUS limitations */
+ reg_vbus_usb3: regulator-vbus-usb3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "USB3_VBUS";
+ gpio = <&gpio4 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x28000000>;
+ alloc-ranges = <0 0x80000000 0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
+ sfp_xfi: sfp-xfi {
+ compatible = "sff,sfp";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sfp>;
+ i2c-bus = <&lpi2c7>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander1 3 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-tlv320aic32x4";
+ model = "tqm-tlv320aic32";
+ audio-codec = <&tlv320aic3x04>;
+ audio-cpu = <&sai3>;
+ audio-routing =
+ "IN3_L", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR",
+ "IN1_L", "Line In Jack",
+ "IN1_R", "Line In Jack",
+ "Line Out Jack", "LOL",
+ "Line Out Jack", "LOR";
+ };
+
+ wifi-connector {
+ compatible = "pcie-m2-e-connector";
+ vpcie3v3-supply = <®_v3v3_mb>;
+ vpcie1v8-supply = <®_v1v8_mb>;
+ i2c-parent = <&lpi2c2>;
+ w-disable1-gpios = <&expander2 9 GPIO_ACTIVE_LOW>;
+ w-disable2-gpios = <&expander2 10 GPIO_ACTIVE_LOW>;
+ /* UART_WAKE is connected to SM */
+ /* SDIO_WAKE is connected to SM */
+ sdio-reset-gpios = <&expander3 2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&enetc_port0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enetc0>;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&enetc_port1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enetc1>;
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+/* No support for XFI yet */
+&enetc_port2 {
+ sfp = <&sfp_xfi>;
+ phy-mode = "10gbase-r";
+ clocks = <&clk_eth>;
+ clock-names = "enet_ref_clk";
+ managed = "in-band-status";
+ status = "disabled";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&lpi2c2 {
+ tlv320aic3x04: audio-codec@18 {
+ compatible = "ti,tlv320aic32x4";
+ reg = <0x18>;
+ clocks = <&scmi_clk IMX95_CLK_SAI3>;
+ clock-names = "mclk";
+ reset-gpios = <&expander1 14 GPIO_ACTIVE_LOW>;
+ iov-supply = <®_v3v3_mb>;
+ ldoin-supply = <®_v3v3_mb>;
+ };
+
+ fan_controller: fan-controller@2f {
+ compatible = "microchip,emc2301", "microchip,emc2305";
+ reg = <0x2f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pwm-cells = <3>;
+ status = "okay";
+
+ fan: fan@0 {
+ reg = <0x0>;
+ pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED 1>;
+ #cooling-cells = <2>;
+ fan-supply = <®_pwm_fan>;
+ };
+ };
+
+ ptn5110: usb-typec@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ label = "X9";
+ power-role = "source";
+ data-role = "dual";
+ source-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>;
+ self-powered;
+
+ port {
+ typec_con_hs: endpoint {
+ remote-endpoint = <&typec_hs>;
+ };
+ };
+ };
+ };
+
+ sensor_mb: temperature-sensor@1e {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x1e>;
+ };
+
+ eeprom_mb: eeprom@56 {
+ compatible = "nxp,se97b", "atmel,24c02";
+ reg = <0x56>;
+ pagesize = <16>;
+ vcc-supply = <®_v3v3_mb>;
+ };
+
+ pcieclk: clock-generator@68 {
+ compatible = "renesas,9fgv0441";
+ reg = <0x68>;
+ clocks = <&clk_xtal25>;
+ #clock-cells = <1>;
+ };
+
+ /* D39 IN/OUT 3V3 */
+ expander1: gpio@74 {
+ compatible = "ti,tca9539";
+ reg = <0x74>;
+ vcc-supply = <®_v3v3_mb>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_expander1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-line-names =
+ /* 00 */ "BUTTON_B#", "CAM0_SYNC_3V3",
+ /* 02 */ "CAM1_SYNC_3V3", "SFP_MOD_ABS",
+ /* 04 */ "DIG_IN1", "DIG_IN2",
+ /* 06 */ "DIG_IN3", "DIG_IN4",
+ /* 08 */ "DIG_OUT_1_2_STATE", "DIG_OUT_3_4_STATE",
+ /* 10 */ "DIG_OUT_1_EN", "DIG_OUT_2_EN",
+ /* 12 */ "DIG_OUT_3_EN", "DIG_OUT_4_EN",
+ /* 14 */ "AUDIO_RST#", "12V_EN";
+ };
+
+ /* D40 OUT 3V3 */
+ expander2: gpio@75 {
+ compatible = "ti,tca9539";
+ reg = <0x75>;
+ vcc-supply = <®_3v3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ /* 00 */ "ETH10G_REFCLK_EN", "ETH10G_REFCLK_RST#",
+ /* 02 */ "SFP_TX_DIS", "USB3_RESET#",
+ /* 04 */ "USB2_RESET#", "LCD_RESET#",
+ /* 06 */ "LCD_BLT_EN", "LCD_PWR_EN",
+ /* 08 */ "M2_KEYE_PERST#", "M2_KEYE_WDISABLE1#",
+ /* 10 */ "M2_KEYE_WDISABLE2#", "M2_KEYB_PERST#",
+ /* 12 */ "M2_KEYB_WDISABLE1#", "USER_LED1",
+ /* 14 */ "USER_LED2", "3V3A_10G_EN";
+
+ eth10g-refclk-en-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "ETH10G_REFCLK_EN";
+ };
+
+ eth10g-refclk-rst-hog {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "ETH10G_REFCLK_RST#";
+ };
+
+ m2-keyb-wdisable1-hog {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "M2_KEYB_WDISABLE1#";
+ };
+ };
+
+ /* D41 OUT 1V8 */
+ expander3: gpio@76 {
+ compatible = "ti,tca9539";
+ reg = <0x76>;
+ vcc-supply = <®_v1v8_mb>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ /* 00 */ "ENET1_RESET#", "ENET2_RESET#",
+ /* 02 */ "M2_KEYE_SDIO_RST#", "M2_KEYE_DEV_WLAN_WAKE#",
+ /* 04 */ "M2_KEYE_DEV_BT_WAKE", "M2_KEYB_W_DISABLE2#",
+ /* 06 */ "M2_KEYB_RST#", "M2_KEYB_FULL_CARD_PWR_OFF#",
+ /* 08 */ "M2_KEYB_DPR", "CAM0_PWR#",
+ /* 10 */ "CAM1_PWR#", "CAM0_RST#",
+ /* 12 */ "CAM1_RST#", "CAM0_TRIGGER",
+ /* 14 */ "CAM1_TRIGGER", "FAN_PWR_EN";
+
+ m2-keye-sdio-rst-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "M2_KEYE_SDIO_RST#";
+ };
+
+ m2-keye-dev_wlan-wake-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "M2_KEYE_DEV_WLAN_WAKE#";
+ };
+
+ m2-keye-dev_bt-wake-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "M2_KEYE_DEV_BT_WAKE#";
+ };
+
+ m2-keyb-wdisable2-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "M2_KEYB_WDISABLE1#";
+ };
+
+ m2-keyb-rst-hog {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "M2_KEYB_RST#";
+ };
+
+ m2-keyb-full-card-pwr-off-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "M2_KEYB_FULL_CARD_PWR_OFF#";
+ };
+ };
+};
+
+/* X4 + SFP */
+&lpi2c7 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c7>;
+ pinctrl-1 = <&pinctrl_lpi2c7_recovery>;
+ scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ /* TODO: 0x19: retimer */
+
+ /* 0x50 / 0x51: SFP EEPROM */
+};
+
+/* X4 */
+&lpspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi4>;
+ cs-gpios = <&gpio5 14 GPIO_ACTIVE_LOW>, <&gpio5 13 GPIO_ACTIVE_LOW>;
+ /* per datasheet, without SCK loopback via pad (LPSPI_CFGR1[SAMPLE]) */
+ spi-max-frequency = <30000000>;
+ status = "okay";
+};
+
+&lpuart1 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&lpuart2 {
+ /* SM */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+ status = "reserved";
+};
+
+&lpuart5 {
+ /* X16 M.2 KEY E */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart5>;
+ status = "okay";
+};
+
+&lpuart7 {
+ /* X5 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart7>;
+ status = "okay";
+};
+
+&lpuart8 {
+ /* X15 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart8>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&netc_blk_ctrl {
+ status = "okay";
+};
+
+&netc_emdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emdio>;
+ status = "okay";
+
+ /* IRQ pin is AON GPIO, not usable */
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&expander3 0 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ethphy1>;
+ reset-gpios = <&expander3 1 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+};
+
+&netc_timer {
+ status = "okay";
+};
+
+&netcmix_blk_ctrl {
+ status = "okay";
+};
+
+/* X16 M2 / E-Key mPCIe */
+&pcie0 {
+ pinctrl-0 = <&pinctrl_pcie0>;
+ pinctrl-names = "default";
+ clocks = <&scmi_clk IMX95_CLK_HSIO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
+ <&hsio_blk_ctl 0>,
+ <&pcieclk 1>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref";
+ reset-gpios = <&expander2 8 GPIO_ACTIVE_LOW>;
+ /* Not supported on REV.0100 */
+ /* supports-clkreq; */
+ status = "okay";
+};
+
+/* X17 M2 / B-Key PCIe */
+&pcie1 {
+ pinctrl-0 = <&pinctrl_pcie1>;
+ pinctrl-names = "default";
+ clocks = <&scmi_clk IMX95_CLK_HSIO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
+ <&hsio_blk_ctl 0>,
+ <&pcieclk 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref";
+ reset-gpios = <&expander2 11 GPIO_ACTIVE_LOW>;
+ /* Not supported on REV.0100 */
+ /* supports-clkreq; */
+ status = "okay";
+};
+
+®_sdvmmc {
+ status = "okay";
+};
+
+&sai3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_SAI3>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+ assigned-clock-rates = <3932160000>,
+ <3612672000>, <393216000>,
+ <361267200>, <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&scmi_bbm {
+ linux,code = <KEY_POWER>;
+};
+
+&thermal_zones {
+ a55-thermal {
+ trips {
+ cpu_active0: trip-active0 {
+ temperature = <40000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ cpu_active1: trip-active1 {
+ temperature = <48000>;
+ hysteresis = <3000>;
+ type = "active";
+ };
+
+ cpu_active2: trip-active2 {
+ temperature = <60000>;
+ hysteresis = <10000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&cpu_active0>;
+ cooling-device = <&fan 0 2>;
+ };
+
+ map2 {
+ trip = <&cpu_active1>;
+ cooling-device = <&fan 3 5>;
+ };
+
+ map3 {
+ trip = <&cpu_active2>;
+ cooling-device = <&fan 6 10>;
+ };
+ };
+ };
+};
+
+&tpm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm3>;
+ status = "okay";
+};
+
+&tpm5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm5>;
+};
+
+&usb2 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ typec_hs: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb451,8142";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_v3v3_mb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub_2_1: hub@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+ reset-gpios = <&expander2 4 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_v3v3_mb>;
+ vdda-supply = <®_v3v3_mb>;
+ };
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb451,8140";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_v3v3_mb>;
+ };
+};
+
+&usb3_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ vbus-supply = <®_vbus_usb3>;
+ status = "okay";
+};
+
+/* X7 µSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <®_sdvmmc>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_enetc0: enetc0grp {
+ fsl,pins = <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x1100>,
+ <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x1100>,
+ <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x1100>,
+ <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x1100>,
+ <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x1100>,
+ <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x1100>,
+ <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x11e>,
+ <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x11e>,
+ <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x11e>,
+ <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x11e>,
+ <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x11e>,
+ <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x11e>;
+ };
+
+ pinctrl_enetc1: enetc1grp {
+ fsl,pins = <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x1100>,
+ <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x1100>,
+ <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x1100>,
+ <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x1100>,
+ <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x1100>,
+ <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x1100>,
+ <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x11e>,
+ <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x11e>,
+ <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x11e>,
+ <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x11e>,
+ <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x11e>,
+ <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x11e>;
+ };
+
+ pinctrl_ethphy0: ethphy0grp {
+ fsl,pins = <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x1100>;
+ };
+
+ pinctrl_ethphy1: ethphy1grp {
+ fsl,pins = <IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x1100>;
+ };
+
+ pinctrl_expander1: expander1grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x1100>;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x1300>,
+ <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x31e>;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x31e>,
+ <IMX95_PAD_GPIO_IO27__CAN2_RX 0x1300>;
+ };
+
+ pinctrl_lpi2c7: lpi2c7grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x40001b1e>,
+ <IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x40001b1e>;
+ };
+
+ pinctrl_lpi2c7_recovery: lpi2c7recoverygrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x40001b1e>,
+ <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x40001b1e>;
+ };
+
+ pinctrl_lpspi4: lpspi4grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x11e>,
+ <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x111e>,
+ <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x11e>,
+ <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x11e>,
+ <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x11e>;
+ };
+
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>,
+ <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x1300>;
+ };
+
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>,
+ <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x1300>;
+ };
+
+ pinctrl_lpuart5: lpuart5grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e>,
+ <IMX95_PAD_GPIO_IO01__LPUART5_RX 0x1300>,
+ <IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x1300>,
+ <IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e>;
+ };
+
+ pinctrl_lpuart7: lpuart7grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX 0x31e>,
+ <IMX95_PAD_GPIO_IO09__LPUART7_RX 0x1300>,
+ <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x1300>,
+ <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>;
+ };
+
+ pinctrl_lpuart8: lpuart8grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>,
+ <IMX95_PAD_GPIO_IO13__LPUART8_RX 0x1300>,
+ <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x31e>;
+ };
+
+ pinctrl_emdio: emdiogrp {
+ fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x51e>,
+ <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x51e>;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x111e>;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x111e>;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x51e>,
+ <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x51e>,
+ <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x1300>,
+ <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x51e>,
+ <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x51e>;
+ };
+
+ pinctrl_retimer: retirmergrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x1100>;
+ };
+
+ pinctrl_sfp: sfpgrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x1100>,
+ <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x1100>;
+ };
+
+ pinctrl_tpm3: tpm3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO24__TPM3_CH3 0x51e>;
+ };
+
+ pinctrl_tpm5: tpm5grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO18__TPM5_CH2 0x51e>;
+ };
+
+ pinctrl_typec: typcegrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x1100>;
+ };
+
+ pinctrl_usb3: usb3grp {
+ fsl,pins = <IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x31e>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
+ <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x51e>,
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x31e>,
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x131e>,
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x131e>,
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x131e>,
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x131e>,
+ <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
+ <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x58e>,
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x38e>,
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>,
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>,
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>,
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>,
+ <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
+ <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x5fe>,
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x3fe>,
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>,
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>,
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>,
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>,
+ <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi
new file mode 100644
index 0000000000000..aa2756c14e461
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ * Author: Markus Niebel
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx95.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /*
+ * DRAM base addr, size : 2048 MiB DRAM
+ * should be corrected by bootloader
+ */
+ reg = <0 0x80000000 0 0x80000000>;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_sdvmmc: regulator-sdvmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdvmmc>;
+ regulator-name = "SD_PWR_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <12000>;
+ enable-active-high;
+ /* can be enabled by mainboard with SD-Card support */
+ status = "disabled";
+ };
+};
+
+&adc1 {
+ vref-supply = <®_1v8>;
+};
+
+&flexspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi1>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <66000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ vcc-supply = <®_1v8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
+
+/* System Manager */
+&gpio1 {
+ status = "reserved";
+};
+
+/* System Manager */
+&lpi2c1 {
+ status = "reserved";
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063a";
+ reg = <0x51>;
+ quartz-load-femtofarads = <7000>;
+ };
+
+ m24c64: eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ pagesize = <32>;
+ vcc-supply = <®_3v3>;
+ };
+
+ /* protectable identification memory (part of M24C64-D @54) */
+ eeprom@5c {
+ compatible = "atmel,24c64d-wl";
+ reg = <0x5c>;
+ pagesize = <32>;
+ vcc-supply = <®_3v3>;
+ };
+
+ imu@6b {
+ compatible = "st,ism330dhcx";
+ reg = <0x6b>;
+ vdd-supply = <®_3v3>;
+ vddio-supply = <®_3v3>;
+ };
+};
+
+&thermal_zones {
+ pf09-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 2>;
+
+ trips {
+ pf09_alert: trip0 {
+ hysteresis = <2000>;
+ temperature = <140000>;
+ type = "passive";
+ };
+
+ pf09_crit: trip1 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pf53arm-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 4>;
+
+ cooling-maps {
+ map0 {
+ trip = <&pf5301_alert>;
+ cooling-device =
+ <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ pf5301_alert: trip0 {
+ hysteresis = <2000>;
+ temperature = <140000>;
+ type = "passive";
+ };
+
+ pf5301_crit: trip1 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pf53soc-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 3>;
+
+ trips {
+ pf5302_alert: trip0 {
+ hysteresis = <2000>;
+ temperature = <140000>;
+ type = "passive";
+ };
+
+ pf5302_crit: trip1 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&wdog3 {
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_flexspi1: flexspi1grp {
+ fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x19e>,
+ <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x19e>,
+ <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x19e>,
+ <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x19e>,
+ <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x19e>,
+ /* SION to allow clock loopback from pad */
+ <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x4000019e>,
+ <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x4000019e>;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x4000191e>,
+ <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x4000191e>;
+ };
+
+ pinctrl_sdvmmc: sdvmmcgrp {
+ fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>,
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>,
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>,
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>,
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>,
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>,
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>,
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>,
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>,
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>,
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>,
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>,
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>,
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>,
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>,
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>,
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>,
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>,
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>,
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>,
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>,
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>,
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>,
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>,
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>,
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>,
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>,
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>,
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>,
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>,
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>;
+ };
+};
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v3 1/2] dt-bindings: iio: dac: Add AD5529R
From: Conor Dooley @ 2026-06-19 11:40 UTC (permalink / raw)
To: Janani Sunil
Cc: Jonathan Cameron, Rodrigo Alencar, Janani Sunil,
Lars-Peter Clausen, Michael Hennerich, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Jonathan Corbet, Shuah Khan,
linux-iio, devicetree, linux-kernel, linux-doc, Mark Brown
In-Reply-To: <20260619-obstinate-polo-a230bef97fda@spud>
[-- Attachment #1: Type: text/plain, Size: 10234 bytes --]
On Fri, Jun 19, 2026 at 12:36:55PM +0100, Conor Dooley wrote:
> On Fri, Jun 19, 2026 at 12:33:11PM +0200, Janani Sunil wrote:
> >
> > On 6/14/26 21:44, Jonathan Cameron wrote:
> > > On Tue, 9 Jun 2026 16:47:23 +0200
> > > Janani Sunil <jan.sun97@gmail.com> wrote:
> > >
> > > > On 5/26/26 15:11, Rodrigo Alencar wrote:
> > > > > On 26/05/19 05:42PM, Janani Sunil wrote:
> > > > > > Devicetree bindings for AD5529R 16 channel 12/16 bit high voltage,
> > > > > > buffered voltage output digital-to-analog converter (DAC) with an
> > > > > > integrated precision reference.
> > > > > ...
> > > > > Probably others may comment on that, but...
> > > > >
> > > > > This parent node may support device addressing for multi-device support through
> > > > > those ID pins. I suppose that each device may have its own power supplies or
> > > > > other resources like the toggle pins or reset and enable.
> > > > >
> > > > > That way I suppose that an example would look like...
> > > > > > +
> > > > > > +patternProperties:
> > > > > > + "^channel@([0-9]|1[0-5])$":
> > > > > > + type: object
> > > > > > + description: Child nodes for individual channel configuration
> > > > > > +
> > > > > > + properties:
> > > > > > + reg:
> > > > > > + description: Channel number.
> > > > > > + minimum: 0
> > > > > > + maximum: 15
> > > > > > +
> > > > > > + adi,output-range-microvolt:
> > > > > > + description: |
> > > > > > + Output voltage range for this channel as [min, max] in microvolts.
> > > > > > + If not specified, defaults to 0V to 5V range.
> > > > > > + oneOf:
> > > > > > + - items:
> > > > > > + - const: 0
> > > > > > + - enum: [5000000, 10000000, 20000000, 40000000]
> > > > > > + - items:
> > > > > > + - const: -5000000
> > > > > > + - const: 5000000
> > > > > > + - items:
> > > > > > + - const: -10000000
> > > > > > + - const: 10000000
> > > > > > + - items:
> > > > > > + - const: -15000000
> > > > > > + - const: 15000000
> > > > > > + - items:
> > > > > > + - const: -20000000
> > > > > > + - const: 20000000
> > > > > > +
> > > > > > + required:
> > > > > > + - reg
> > > > > > +
> > > > > > + additionalProperties: false
> > > > > > +
> > > > > > +required:
> > > > > > + - compatible
> > > > > > + - reg
> > > > > > + - vdd-supply
> > > > > > + - avdd-supply
> > > > > > + - hvdd-supply
> > > > > > +
> > > > > > +dependencies:
> > > > > > + spi-cpha: [ spi-cpol ]
> > > > > > + spi-cpol: [ spi-cpha ]
> > > > > > +
> > > > > > +allOf:
> > > > > > + - $ref: /schemas/spi/spi-peripheral-props.yaml#
> > > > > > +
> > > > > > +unevaluatedProperties: false
> > > > > > +
> > > > > > +examples:
> > > > > > + - |
> > > > > > + #include <dt-bindings/gpio/gpio.h>
> > > > > > +
> > > > > > + spi {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > +
> > > > > > + dac@0 {
> > > > > > + compatible = "adi,ad5529r-16";
> > > > > > + reg = <0>;
> > > > > > + spi-max-frequency = <25000000>;
> > > > > > +
> > > > > > + vdd-supply = <&vdd_regulator>;
> > > > > > + avdd-supply = <&avdd_regulator>;
> > > > > > + hvdd-supply = <&hvdd_regulator>;
> > > > > > + hvss-supply = <&hvss_regulator>;
> > > > > > +
> > > > > > + reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> > > > > > +
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > +
> > > > > > + channel@0 {
> > > > > > + reg = <0>;
> > > > > > + adi,output-range-microvolt = <0 5000000>;
> > > > > > + };
> > > > > > +
> > > > > > + channel@1 {
> > > > > > + reg = <1>;
> > > > > > + adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > > > + };
> > > > > > +
> > > > > > + channel@2 {
> > > > > > + reg = <2>;
> > > > > > + adi,output-range-microvolt = <0 40000000>;
> > > > > > + };
> > > > > > + };
> > > > > > + };
> > > > > ...
> > > > >
> > > > > spi {
> > > > > #address-cells = <1>;
> > > > > #size-cells = <0>;
> > > > >
> > > > > multi-dac@0 {
> > > > > compatible = "adi,ad5529r-16";
> > > > > reg = <0>;
> > > > > spi-max-frequency = <25000000>;
> > > > >
> > > > > #address-cells = <1>;
> > > > > #size-cells = <0>;
> > > > >
> > > > > dac@0 {
> > > > > reg = <0>;
> > > > > vdd-supply = <&vdd_regulator>;
> > > > > avdd-supply = <&avdd_regulator>;
> > > > > hvdd-supply = <&hvdd_regulator>;
> > > > > hvss-supply = <&hvss_regulator>;
> > > > >
> > > > > reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> > > > >
> > > > > #address-cells = <1>;
> > > > > #size-cells = <0>;
> > > > >
> > > > > channel@0 {
> > > > > reg = <0>;
> > > > > adi,output-range-microvolt = <0 5000000>;
> > > > > };
> > > > >
> > > > > channel@1 {
> > > > > reg = <1>;
> > > > > adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > > };
> > > > >
> > > > > channel@2 {
> > > > > reg = <2>;
> > > > > adi,output-range-microvolt = <0 40000000>;
> > > > > };
> > > > > }
> > > > >
> > > > > dac@1 {
> > > > > reg = <1>;
> > > > > vdd-supply = <&vdd_regulator>;
> > > > > avdd-supply = <&avdd_regulator>;
> > > > > hvdd-supply = <&hvdd_regulator>;
> > > > > hvss-supply = <&hvss_regulator>;
> > > > >
> > > > > reset-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
> > > > >
> > > > > #address-cells = <1>;
> > > > > #size-cells = <0>;
> > > > >
> > > > > channel@0 {
> > > > > reg = <0>;
> > > > > adi,output-range-microvolt = <0 5000000>;
> > > > > };
> > > > >
> > > > > channel@1 {
> > > > > reg = <1>;
> > > > > adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > > };
> > > > > }
> > > > > };
> > > > > };
> > > > >
> > > > > then you might need something like:
> > > > >
> > > > > patternProperties:
> > > > > "^dac@[0-3]$":
> > > > >
> > > > > and put most of the things under this node pattern.
> > > > >
> > > > > So the main driver that you're putting together might need to handle up to four instances.
> > > > > Even if your current driver cannot handle this, the dt-bindings might need cover that.
> > > > >
> > > > > Need to double check if each dac node needs a separate compatible, so you would maybe populate
> > > > > a platform data to be shared with the child nodes, which would be a separate driver.
> > > > > (not sure if it would make sense to mix and match ad5529r-16 and ad5529r-12).
> > > > Hi Rodrigo,
> > > >
> > > > Thank you for looking at this.
> > > >
> > > > For now, I would prefer to keep the binding scoped to a single AD5529R device instance. The current
> > > > hardware/use case we have only needs one device node and the driver is written around that model as well.
> > > > While the device addressing pins could allow multi-device topology, we do not have an actual platform using
> > > > that configuration at the moment, so I would prefer not to introduce an extra parent/child binding structure
> > > > speculatively without a validating use case.
> > > Interesting feature - kind of similar to address control on a typical i2c bus device, or
> > > looking at it another way a kind of distributed SPI mux.
> > >
> > > Challenge of a binding is we need to anticipate the future. So I think we do need something
> > > like Rodrigo is suggesting even if we only (for now) support a single instance in the driver.
> > > That would leave the path open to supporting the addressing at a later date.
> > > An alternative might be to look at it like a chained device setup. In those we pretend there
> > > is just one device with a lot of channels etc. The snag is that here things are more loosely
> > > coupled whereas for those devices it tends to be you have to read / write the same register
> > > in all devices in the chain as one big SPI message.
> > >
> > > +CC Mark Brown as he may know of some precedence for this feature. For his reference..
> > > - Each of these device has 2 ID pins. The SPI transfers have to contain the 2 bit
> > > value that matches that or they are ignored. Thus a single bus + 1 chip select can
> > > be used to talk to 4 devices. Question is what that looks like in device tree + I guess
> > > longer term how to support it cleanly in SPI.
>
> I'd swear I have seen this before, from some Microchip devices. Let me
> see if I can find what I am thinking of...
microchip,mcp3911 and microchip,mcp3564 both seem to do this with
slightly different properties.
microchip,device-addr:
description: Device address when multiple MCP3911 chips are present on the same SPI bus.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
and
microchip,hw-device-address:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
description:
The address is set on a per-device basis by fuses in the factory,
configured on request. If not requested, the fuses are set for 0x1.
The device address is part of the device markings to avoid
potential confusion. This address is coded on two bits, so four possible
addresses are available when multiple devices are present on the same
SPI bus with only one Chip Select line for all devices.
Each device communication starts by a CS falling edge, followed by the
clocking of the device address (BITS[7:6] - top two bits of COMMAND BYTE
which is first one on the wire).
This sounds exactly like the sort of feature that you're dealing with
here?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v5 1/1] arm64: dts: add tqma9596la-mba95xxca
From: sashiko-bot @ 2026-06-19 11:37 UTC (permalink / raw)
To: Alexander Stein; +Cc: wsa+renesas, imx, conor+dt, devicetree, robh, Frank.Li
In-Reply-To: <20260619112434.1121610-1-alexander.stein@ew.tq-group.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] Duplicate and incorrect GPIO hog line name `M2_KEYB_WDISABLE1#` in `expander3`.
- [Low] Incorrect regulator referenced for `expander2` `vcc-supply`.
- [Low] Typos in pinctrl node names for retimer and typec groups.
--
commit fb001fddc405cd85f401d1d2351baf577241c535
Author: Markus Niebel <Markus.Niebel@ew.tq-group.com>
arm64: dts: add tqma9596la-mba95xxca
This commit adds device tree support for the TQMa95xxLA modules on the
MBa95xxCA carrier board. It configures PCIe, clocks, reset GPIOs, and adds
GPIO hogs for the M.2 slots.
> diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts
> new file mode 100644
> index 0000000000000..4b49f6cf731da
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts
[ ... ]
> + /* D40 OUT 3V3 */
> + expander2: gpio@75 {
> + compatible = "ti,tca9539";
> + reg = <0x75>;
> + vcc-supply = <®_3v3>;
[Severity: Low]
Does this point to the SoM regulator instead of the intended mainboard
regulator? Since expander2 is a mainboard component, shouldn't this reference
<®_v3v3_mb>?
> + gpio-controller;
> + #gpio-cells = <2>;
[ ... ]
> + /* D41 OUT 1V8 */
> + expander3: gpio@76 {
> + compatible = "ti,tca9539";
> + reg = <0x76>;
[ ... ]
> + m2-keyb-wdisable2-hog {
> + gpio-hog;
> + gpios = <5 GPIO_ACTIVE_LOW>;
> + output-low;
> + line-name = "M2_KEYB_WDISABLE1#";
[Severity: Medium]
Does this duplicate the line-name used in expander2 for
m2-keyb-wdisable1-hog? This could cause a naming collision in gpiolib. Should
this be named "M2_KEYB_WDISABLE2#" instead?
> + };
[ ... ]
> + pinctrl_retimer: retirmergrp {
[Severity: Low]
This isn't a bug, but there's a typo in the node name (retirmergrp instead
of retimergrp).
> + fsl,pins = <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x1100>;
> + };
[ ... ]
> + pinctrl_typec: typcegrp {
[Severity: Low]
This isn't a bug, but there's a typo in the node name (typcegrp instead
of typecgrp).
> + fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x1100>;
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260619112434.1121610-1-alexander.stein@ew.tq-group.com?part=1
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: iio: dac: Add AD5529R
From: Conor Dooley @ 2026-06-19 11:36 UTC (permalink / raw)
To: Janani Sunil
Cc: Jonathan Cameron, Rodrigo Alencar, Janani Sunil,
Lars-Peter Clausen, Michael Hennerich, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Jonathan Corbet, Shuah Khan,
linux-iio, devicetree, linux-kernel, linux-doc, Mark Brown
In-Reply-To: <076d7d2d-81a0-49c2-af94-bd65ead66c09@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 8557 bytes --]
On Fri, Jun 19, 2026 at 12:33:11PM +0200, Janani Sunil wrote:
>
> On 6/14/26 21:44, Jonathan Cameron wrote:
> > On Tue, 9 Jun 2026 16:47:23 +0200
> > Janani Sunil <jan.sun97@gmail.com> wrote:
> >
> > > On 5/26/26 15:11, Rodrigo Alencar wrote:
> > > > On 26/05/19 05:42PM, Janani Sunil wrote:
> > > > > Devicetree bindings for AD5529R 16 channel 12/16 bit high voltage,
> > > > > buffered voltage output digital-to-analog converter (DAC) with an
> > > > > integrated precision reference.
> > > > ...
> > > > Probably others may comment on that, but...
> > > >
> > > > This parent node may support device addressing for multi-device support through
> > > > those ID pins. I suppose that each device may have its own power supplies or
> > > > other resources like the toggle pins or reset and enable.
> > > >
> > > > That way I suppose that an example would look like...
> > > > > +
> > > > > +patternProperties:
> > > > > + "^channel@([0-9]|1[0-5])$":
> > > > > + type: object
> > > > > + description: Child nodes for individual channel configuration
> > > > > +
> > > > > + properties:
> > > > > + reg:
> > > > > + description: Channel number.
> > > > > + minimum: 0
> > > > > + maximum: 15
> > > > > +
> > > > > + adi,output-range-microvolt:
> > > > > + description: |
> > > > > + Output voltage range for this channel as [min, max] in microvolts.
> > > > > + If not specified, defaults to 0V to 5V range.
> > > > > + oneOf:
> > > > > + - items:
> > > > > + - const: 0
> > > > > + - enum: [5000000, 10000000, 20000000, 40000000]
> > > > > + - items:
> > > > > + - const: -5000000
> > > > > + - const: 5000000
> > > > > + - items:
> > > > > + - const: -10000000
> > > > > + - const: 10000000
> > > > > + - items:
> > > > > + - const: -15000000
> > > > > + - const: 15000000
> > > > > + - items:
> > > > > + - const: -20000000
> > > > > + - const: 20000000
> > > > > +
> > > > > + required:
> > > > > + - reg
> > > > > +
> > > > > + additionalProperties: false
> > > > > +
> > > > > +required:
> > > > > + - compatible
> > > > > + - reg
> > > > > + - vdd-supply
> > > > > + - avdd-supply
> > > > > + - hvdd-supply
> > > > > +
> > > > > +dependencies:
> > > > > + spi-cpha: [ spi-cpol ]
> > > > > + spi-cpol: [ spi-cpha ]
> > > > > +
> > > > > +allOf:
> > > > > + - $ref: /schemas/spi/spi-peripheral-props.yaml#
> > > > > +
> > > > > +unevaluatedProperties: false
> > > > > +
> > > > > +examples:
> > > > > + - |
> > > > > + #include <dt-bindings/gpio/gpio.h>
> > > > > +
> > > > > + spi {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + dac@0 {
> > > > > + compatible = "adi,ad5529r-16";
> > > > > + reg = <0>;
> > > > > + spi-max-frequency = <25000000>;
> > > > > +
> > > > > + vdd-supply = <&vdd_regulator>;
> > > > > + avdd-supply = <&avdd_regulator>;
> > > > > + hvdd-supply = <&hvdd_regulator>;
> > > > > + hvss-supply = <&hvss_regulator>;
> > > > > +
> > > > > + reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> > > > > +
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + channel@0 {
> > > > > + reg = <0>;
> > > > > + adi,output-range-microvolt = <0 5000000>;
> > > > > + };
> > > > > +
> > > > > + channel@1 {
> > > > > + reg = <1>;
> > > > > + adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > > + };
> > > > > +
> > > > > + channel@2 {
> > > > > + reg = <2>;
> > > > > + adi,output-range-microvolt = <0 40000000>;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > ...
> > > >
> > > > spi {
> > > > #address-cells = <1>;
> > > > #size-cells = <0>;
> > > >
> > > > multi-dac@0 {
> > > > compatible = "adi,ad5529r-16";
> > > > reg = <0>;
> > > > spi-max-frequency = <25000000>;
> > > >
> > > > #address-cells = <1>;
> > > > #size-cells = <0>;
> > > >
> > > > dac@0 {
> > > > reg = <0>;
> > > > vdd-supply = <&vdd_regulator>;
> > > > avdd-supply = <&avdd_regulator>;
> > > > hvdd-supply = <&hvdd_regulator>;
> > > > hvss-supply = <&hvss_regulator>;
> > > >
> > > > reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> > > >
> > > > #address-cells = <1>;
> > > > #size-cells = <0>;
> > > >
> > > > channel@0 {
> > > > reg = <0>;
> > > > adi,output-range-microvolt = <0 5000000>;
> > > > };
> > > >
> > > > channel@1 {
> > > > reg = <1>;
> > > > adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > };
> > > >
> > > > channel@2 {
> > > > reg = <2>;
> > > > adi,output-range-microvolt = <0 40000000>;
> > > > };
> > > > }
> > > >
> > > > dac@1 {
> > > > reg = <1>;
> > > > vdd-supply = <&vdd_regulator>;
> > > > avdd-supply = <&avdd_regulator>;
> > > > hvdd-supply = <&hvdd_regulator>;
> > > > hvss-supply = <&hvss_regulator>;
> > > >
> > > > reset-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
> > > >
> > > > #address-cells = <1>;
> > > > #size-cells = <0>;
> > > >
> > > > channel@0 {
> > > > reg = <0>;
> > > > adi,output-range-microvolt = <0 5000000>;
> > > > };
> > > >
> > > > channel@1 {
> > > > reg = <1>;
> > > > adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > };
> > > > }
> > > > };
> > > > };
> > > >
> > > > then you might need something like:
> > > >
> > > > patternProperties:
> > > > "^dac@[0-3]$":
> > > >
> > > > and put most of the things under this node pattern.
> > > >
> > > > So the main driver that you're putting together might need to handle up to four instances.
> > > > Even if your current driver cannot handle this, the dt-bindings might need cover that.
> > > >
> > > > Need to double check if each dac node needs a separate compatible, so you would maybe populate
> > > > a platform data to be shared with the child nodes, which would be a separate driver.
> > > > (not sure if it would make sense to mix and match ad5529r-16 and ad5529r-12).
> > > Hi Rodrigo,
> > >
> > > Thank you for looking at this.
> > >
> > > For now, I would prefer to keep the binding scoped to a single AD5529R device instance. The current
> > > hardware/use case we have only needs one device node and the driver is written around that model as well.
> > > While the device addressing pins could allow multi-device topology, we do not have an actual platform using
> > > that configuration at the moment, so I would prefer not to introduce an extra parent/child binding structure
> > > speculatively without a validating use case.
> > Interesting feature - kind of similar to address control on a typical i2c bus device, or
> > looking at it another way a kind of distributed SPI mux.
> >
> > Challenge of a binding is we need to anticipate the future. So I think we do need something
> > like Rodrigo is suggesting even if we only (for now) support a single instance in the driver.
> > That would leave the path open to supporting the addressing at a later date.
> > An alternative might be to look at it like a chained device setup. In those we pretend there
> > is just one device with a lot of channels etc. The snag is that here things are more loosely
> > coupled whereas for those devices it tends to be you have to read / write the same register
> > in all devices in the chain as one big SPI message.
> >
> > +CC Mark Brown as he may know of some precedence for this feature. For his reference..
> > - Each of these device has 2 ID pins. The SPI transfers have to contain the 2 bit
> > value that matches that or they are ignored. Thus a single bus + 1 chip select can
> > be used to talk to 4 devices. Question is what that looks like in device tree + I guess
> > longer term how to support it cleanly in SPI.
I'd swear I have seen this before, from some Microchip devices. Let me
see if I can find what I am thinking of...
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: iio: dac: Add AD5529R
From: Nuno Sá @ 2026-06-19 11:31 UTC (permalink / raw)
To: Janani Sunil
Cc: Jonathan Cameron, Rodrigo Alencar, Janani Sunil,
Lars-Peter Clausen, Michael Hennerich, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Jonathan Corbet, Shuah Khan,
linux-iio, devicetree, linux-kernel, linux-doc, Mark Brown
In-Reply-To: <076d7d2d-81a0-49c2-af94-bd65ead66c09@gmail.com>
On Fri, Jun 19, 2026 at 12:33:11PM +0200, Janani Sunil wrote:
>
> On 6/14/26 21:44, Jonathan Cameron wrote:
> > On Tue, 9 Jun 2026 16:47:23 +0200
> > Janani Sunil <jan.sun97@gmail.com> wrote:
> >
>
> Hi Jonathan, Rob, Krzysztof, Conor,
>
> One possible model that would also allow mixing the 12-bit and 16-bit variants would be to treat the parent node
> as the shared SPI transport only, and let each dac@N child carry its own compatible.
>
> Rob, Krzysztof, Conor — wanted to get your input on whether this is an acceptable binding pattern.
>
> properties:
> compatible:
> const: adi,ad5529r-bus
>
> patternProperties:
> "^dac@[0-3]$":
> type: object
> properties:
> compatible:
> enum:
> - adi,ad5529r-16
> - adi,ad5529r-12
> reg:
> minimum: 0
> maximum: 3
>
> With a DT example such as:
>
> ad5529r@0 {
> compatible = "adi,ad5529r-bus";
> reg = <0>;
>
> dac@0 {
> compatible = "adi,ad5529r-16";
> reg = <0>;
> };
>
> dac@1 {
> compatible = "adi,ad5529r-12";
> reg = <1>;
> };
> };
>
> The downside is that it introduces adi,ad5529r-bus as a compatible that does not correspond to an actual
> standalone device variant - it would require a parent driver to manage the shared SPI transport and enumerate the
> child devices. The actual DAC functionality is handled by the matching per-child compatibles(12 or 16 bit).
> Is this an acceptable pattern, or is there a preferred way to model this type of addressing scheme?
>
At some point, I wondered if we can't just have this at spi level? Like
(in the simplest terms) a new spi-peripheral property that would allow
devices to share the same CS. Then we would need an adi,pin-id kind of
property for this device but the bindings would be pretty much as if we
only supported one device.
I see Mark is already in the loop, maybe he has seen this kind of things
before.
- Nuno Sá
^ permalink raw reply
* Re: [RFC PATCH 3/3] dt-bindings: sifive: Add WorldGuard Checker
From: sashiko-bot @ 2026-06-19 10:59 UTC (permalink / raw)
To: Yu-Chien Peter Lin; +Cc: conor+dt, robh, devicetree
In-Reply-To: <20260619105834.1277302-4-peter.lin@sifive.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] The `#access-controller-cells` specifier inappropriately encodes 64-bit absolute physical addresses and sizes, bypassing Devicetree's native address translation.
- [Low] The schema examples reference an undefined label `&aplic_m`, causing a `dt_binding_check` compilation failure.
- [Low] The `sifive,trustedwid` property is not explicitly disallowed in `riscv/cpus.yaml`, allowing it to bypass schema validation if erroneously placed in a `cpu@*` node.
- [Low] The examples in `sifive,wgchecker2.yaml` omit the required `interrupt-controller` child node in their `cpu@0` definitions, leading to a schema validation error.
--
commit 26cbbd0f7310c04b5d6fe920375466bc89dd2479
Author: Yu-Chien Peter Lin <peter.lin@sifive.com>
dt-bindings: sifive: Add WorldGuard Checker
This commit adds a Device Tree binding for the SiFive wgChecker2, a
hardware firewall enforcing World ID (WID) based access control. It enables
spatial partitioning of memory and memory-mapped devices by providing checker
slots to program per-WID permissions.
Link: https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf
> diff --git a/Documentation/devicetree/bindings/riscv/worlds.yaml b/Documentation/devicetree/bindings/riscv/worlds.yaml
> index cc8b3747591eb..c39a06c2dd8d3 100644
> --- a/Documentation/devicetree/bindings/riscv/worlds.yaml
> +++ b/Documentation/devicetree/bindings/riscv/worlds.yaml
> @@ -34,6 +34,14 @@ properties:
> minimum: 2
> maximum: 64
>
> + sifive,trustedwid:
> + $ref: /schemas/types.yaml#/definitions/uint32
[Severity: Low]
Because riscv/cpus.yaml includes worlds.yaml via $ref, does this
allow the property to be erroneously placed on individual cpu@* nodes
without failing validation?
To enforce correct usage, should sifive,trustedwid: false be explicitly
added to riscv/cpus.yaml, similar to riscv,nworlds: false?
[ ... ]
> diff --git a/Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml b/Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml
> new file mode 100644
> index 0000000000000..043c748385ed4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml
[ ... ]
> + '#access-controller-cells':
> + const: 7
> + description: |
> + Specifier for one access-control rule, encoded as seven u32 cells:
> + <addr-hi addr-lo size-hi size-lo perm-hi perm-lo config>
[Severity: High]
Does encoding absolute physical addresses and sizes directly into the
access-controllers array bypass Devicetree's native address translation?
If the protected device is behind a bus with a translation mapping, or if
a bootloader dynamically patches reg sizes, the hardcoded addresses in the
firewall configuration might be incorrect since they are opaque to DT
address translation APIs.
[ ... ]
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <1000000>;
> + riscv,nworlds = <4>;
> + sifive,trustedwid = <3>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + reg = <0>;
> + compatible = "riscv";
> + riscv,isa = "rv64imac";
> + };
[Severity: Low]
Will this omission cause a dt_binding_check failure?
When validated against riscv/cpus.yaml, the schema strictly mandates an
interrupt-controller child node for cpu@0 nodes with compatible = "riscv".
[ ... ]
> + wgchecker0: wgchecker@1c2000 {
> + compatible = "sifive,wgchecker2";
> + reg = <0x0 0x001c2000 0x0 0x1000>;
> + #access-controller-cells = <7>;
> + interrupts = <80 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&aplic_m>;
[Severity: Low]
Is the aplic_m label defined anywhere in these examples?
It appears missing, which might cause make dt_binding_check to fail with a
"Reference to non-existent node or label" error.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260619105834.1277302-1-peter.lin@sifive.com?part=3
^ permalink raw reply
* Re: [RFC PATCH 2/3] dt-bindings: riscv: Add Worlds per-hart properties
From: sashiko-bot @ 2026-06-19 10:59 UTC (permalink / raw)
To: Yu-Chien Peter Lin; +Cc: robh, devicetree, conor+dt
In-Reply-To: <20260619105834.1277302-3-peter.lin@sifive.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect and unnecessary schema reference: `cpus.yaml` (which validates child `/cpus/cpu@*` nodes) improperly includes a `$ref` to `worlds.yaml` (which validates the parent `/cpus` container node). This erroneously bleeds parent constraints into the child schema.
--
commit 2b4a193c4b5716c3f96b6ae87becc46dcf104835
Author: Yu-Chien Peter Lin <peter.lin@sifive.com>
dt-bindings: riscv: Add Worlds per-hart properties
This commit adds per-hart device tree properties for the RISC-V Worlds
architecture, such as riscv,pmwid and riscv,pmwidlist. These platform-defined
values are used by M-mode firmware to configure World ID CSRs and restrict
usage across privilege levels.
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 5feeb2203050a..4b5778b6d3e70 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -26,6 +26,7 @@ description: |
> allOf:
> - $ref: /schemas/cpu.yaml#
> - $ref: extensions.yaml
> + - $ref: worlds.yaml
[Severity: Medium]
Does this reference unintentionally bleed the parent container properties into
the child hart nodes?
The schema worlds.yaml is designed to validate the system-wide /cpus node
via its select: pattern: "^cpus$", while cpus.yaml validates the individual
/cpus/cpu@* nodes. By referencing worlds.yaml here, properties meant for
the parent container leak into the child schema. Any future properties added
to worlds.yaml would implicitly bypass unevaluatedProperties strict
evaluation on the cpu@* nodes.
> - if:
> not:
[ ... ]
> @@ -120,11 +121,31 @@ properties:
> thead systems where the vector register length is not identical on all harts, or
> the vlenb CSR is not available.
[ ... ]
> # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
> timebase-frequency: false
> + # RISC-V requires 'riscv,nworlds' in /cpus, so disallow it here
> + riscv,nworlds: false
[Severity: Medium]
Is this explicit disallowance a workaround for pulling in the parent schema
via the reference above?
If the reference to worlds.yaml is removed from the allOf block, this manual
workaround shouldn't be necessary. Removing the reference would also prevent
future parent properties from silently sneaking into the child node schemas.
>
> interrupt-controller:
> type: object
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260619105834.1277302-1-peter.lin@sifive.com?part=2
^ permalink raw reply
* Re: [RFC PATCH 1/3] dt-bindings: riscv: Add Worlds ISA extensions
From: sashiko-bot @ 2026-06-19 10:57 UTC (permalink / raw)
To: Yu-Chien Peter Lin; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260619105834.1277302-2-peter.lin@sifive.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The descriptions for the newly added RISC-V Worlds ISA extensions use placeholder 'TBD' text instead of a valid specification commit hash.
- [Low] The newly added multi-letter ISA extensions `smlwid` and `smlwidlist` are not sorted alphanumerically.
--
commit 16fbfa5650f850f6481cd820aa9d7deb379f7452
Author: Yu-Chien Peter Lin <peter.lin@sifive.com>
dt-bindings: riscv: Add Worlds ISA extensions
This commit adds device tree bindings for the RISC-V Worlds ISA extensions.
These extensions are used to tag transactions with World IDs that hardware
uses to enforce isolation across execution contexts.
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 2b0a8a93bb214..1bc8b1aa67c06 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -193,12 +193,35 @@ properties:
> ratified at commit d70011dde6c2 ("Update to ratified state")
> of riscv-j-extension.
>
> + - const: smlwid
[Severity: Low]
This isn't a bug, but are these extensions placed in the correct alphabetical
order? Multi-letter extensions are typically required to be sorted
alphanumerically, and "smlwid" appears to be inserted out of order relative
to other "sm" extensions.
> + description: |
> + The standard Smlwid extension for M-mode control of lower
> + privilege World ID via the mlwid CSR as ratified at commit
> + TBD ("TBD") of riscv-worlds.
[Severity: Medium]
Is the "TBD" placeholder intended to be kept in the final binding? Device tree
bindings usually require a specific commit hash to reference a frozen or
ratified specification.
> +
> + - const: smlwidlist
> + description: |
> + The standard Smlwidlist extension for M-mode control of lower
> + privilege World IDs via the mlwidlist CSR as ratified at commit
> + TBD ("TBD") of riscv-worlds.
[Severity: Medium]
Does this also need to be updated with the actual ratification commit hash
instead of the placeholder?
> +
> - const: smstateen
> description: |
> The standard Smstateen extension for controlling access to CSRs
> added by other RISC-V extensions in H/S/VS/U/VU modes and as
> ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
>
> + - const: smwdeleg
> + description: |
> + The standard Smwdeleg extension for M-mode delegation of lower
> + privilege World ID control to S-mode via the mwiddeleg CSR, as
> + ratified at commit TBD ("TBD") of riscv-worlds.
[Severity: Medium]
Is the exact specification commit hash available to replace the placeholder
text here?
> +
> + - const: smwid
> + description: |
> + The standard Smwid extension for M-mode World ID control via the
> + mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds.
[Severity: Medium]
Can we include the specific commit hash of riscv-worlds here instead of
using the temporary text?
[ ... ]
> @@ -262,6 +285,12 @@ properties:
> ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
> ("Updated to ratified state.")
>
> + - const: sswid
> + description: |
> + The standard Sswid extension for S-mode control of lower
> + privilege World IDs via the slwid CSR as ratified at commit
> + TBD ("TBD") of riscv-worlds.
[Severity: Medium]
Is the placeholder expected to be replaced with the actual ratification
commit before this is merged?
> +
> - const: supm
> description: |
> The standard Supm extension for pointer masking support in user
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260619105834.1277302-1-peter.lin@sifive.com?part=1
^ permalink raw reply
* Re: [PATCH v2 2/6] iommu/arm-smmu: Add interconnect bandwidth voting support
From: Bibek Kumar Patro @ 2026-06-19 10:54 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Baryshkov
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
linux-arm-kernel, iommu, devicetree, linux-kernel, linux-arm-msm
In-Reply-To: <299d54c5-fb93-47ee-9495-fbf48a3204fd@oss.qualcomm.com>
On 6/18/2026 2:58 PM, Konrad Dybcio wrote:
> On 6/17/26 4:26 PM, Bibek Kumar Patro wrote:
>>
>>
>> On 6/16/2026 5:51 AM, Dmitry Baryshkov wrote:
>>> On Mon, Jun 15, 2026 at 06:36:51PM +0530, Bibek Kumar Patro wrote:
>>>>
>>>>
>>>> On 6/8/2026 7:25 PM, Dmitry Baryshkov wrote:
>>>>> On Tue, May 26, 2026 at 08:12:03PM +0530, Bibek Kumar Patro wrote:
>>>>>> On some SoCs the SMMU registers require an active interconnect
>>>>>> bandwidth vote to be accessible. While other clients typically
>>>>>> satisfy this requirement implicitly, certain corner cases (e.g.
>>>>>> during sleep/wakeup transitions) can leave the SMMU without a
>>>>>> vote, causing intermittent register access failures.
>>>>>>
>>>>>> Add support for an optional interconnect path to the arm-smmu
>>>>>> driver and vote for bandwidth while the SMMU is active. The path
>>>>>> is acquired from DT if present and ignored otherwise.
>>>>>>
>>>>>> The bandwidth vote is enabled before accessing SMMU registers
>>>>>> during probe and runtime resume, and released during runtime
>>>>>> suspend and on error paths.
>>>>>>
>>>>>> Generally, from an architectural perspective, GEM_NOC and DDR are
>>>>>> expected to have an active vote whenever the adreno_smmu block is
>>>>>> powered on. In most common use cases, this requirement is implicitly
>>>>>> satisfied because other GPU-related clients (for example, the GMU
>>>>>> device) already hold a GEM_NOC vote when adreno_smmu is enabled.
>>>>>>
>>>>>> However, there are certain corner cases, such as during sleep/wakeup
>>>>>> transitions, where the GEM_NOC vote can be removed before adreno_smmu
>>>>>> is powered down. If adreno_smmu is then accessed while the interconnect
>>>>>> vote is missing, it can lead to the observed failures. Because of the
>>>>>> precise ordering involved, this scenario is difficult to reproduce
>>>>>> consistently.
>>>>>> (also GDSC is involved in adreno usecases can have an independent vote)
>>>>>>
>>>>>> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>>>>>> ---
>>>>>> drivers/iommu/arm/arm-smmu/arm-smmu.c | 57 +++++++++++++++++++++++++++++++++--
>>>>>> drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++
>>>>>> 2 files changed, 57 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
>>>>>> index 0bd21d206eb3e75c3b9fb1364cdc92e82c5aa499..07c7e44ec6a5bd1488f00f87d859a20495e46601 100644
>>>>>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
>>>>>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
>>>>>> @@ -53,6 +53,11 @@
>>>>>> #define MSI_IOVA_BASE 0x8000000
>>>>>> #define MSI_IOVA_LENGTH 0x100000
>>>>>> +/* Interconnect bandwidth vote values for the SMMU register access path */
>>>>>> +#define ARM_SMMU_ICC_AVG_BW 0
>>>>>> +#define ARM_SMMU_ICC_PEAK_BW_HIGH 1000
>>>>>
>>>>> totally random numbers, which might be different for non-Qualcomm platform.
>>>>>
>>>>
>>>> Ideally, any non-zero value would be enough to keep the path active.
>>>
>>> This is true for Qualcomm devices. However, you are adding this to a
>>> generic code.
>>>
>>>> Here 1 Would be enough to keep the path active, but might be too small to
>>>> reliably keep the bus active.
>>>> Other is UINT_MAX, which will reliably keep the bus active but might cause a
>>>> power penalty.
>>>>
>>>> #define ARM_SMMU_ICC_PEAK_BW_HIGH UINT_MAX
>>>>
>>>> seems to be suitable here to reliably keep the bus active by BCM
>>>> for both Qualcomm and non-Qualcomm platforms (with some power penalty).
>>>>
>>>> LMK, if you feel otherwise.
>>>
>>> Shift it to the qcom instance or provide platform-specific values? (My
>>> preference would be towards the first solution).
>>>
>>
>>
>> To support platform-specific values, we may need to introduce a LUT-based approach in the driver. (Bandwidth voting values cannot be placed in device-tree property IIRC ?)
>>
>> Currently, all Qualcomm platforms use 0x1000 for SMMU ICC voting. I
>
> (you used decimal 1000)
>
It's my bad, i meant 1000 only
(I'll check on the icc_bw calculation to get clarity on the values)
>> can evaluate if this could be moved to a Qualcomm-specific
>> implementation.
>
> Add a vendor hook to arm_smmu_runtime_suspend/resume and handle it within
> the QC driver
>
Just curious, wouldn't this apply for all the arm-smmu users in addition
to Qualcomm devices as i mentioned here [1].
Vendor hook would make it Qualcomm specific.
[1]:
https://lore.kernel.org/all/984ff9c7-3eef-463c-a330-bf7acd063667@oss.qualcomm.com/
Thanks & regards,
Bibek
> Konrad
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox