[PATCH 1/6] arm64: dts: qcom: sm8250-hdk: Enable the sdhc_2 port

[PATCH 1/6] arm64: dts: qcom: sm8250-hdk: Enable the sdhc_2 port

[ShiTou Hong]

From: redstonee <1516235445@qq.com>

Signed-off-by: ShiTou Hong <dc_redstone@outlook.com>
---
 arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 19 +++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8250.dtsi    | 20 ++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index c1c673086..5975878ea 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -398,6 +398,12 @@ &qupv3_id_1 {
 
 &tlmm {
 	gpio-reserved-ranges = <28 4>, <40 4>;
+
+	sd_ufs_cd_pins: sd-ufs-cd-pins {
+		pins = "gpio77";
+		function = "gpio";
+		bias-pull-up;
+	};
 };
 
 &uart12 {
@@ -467,3 +473,16 @@ &usb_2_dwc3 {
 &venus {
 	status = "okay";
 };
+
+&sdhc_2 {
+	status = "okay";
+
+	cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+	vmmc-supply = <&vreg_l9c_2p96>;
+	vqmmc-supply = <&vreg_l6c_2p96>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_default_state>, <&sd_ufs_cd_pins>;
+	pinctrl-1 = <&sdc2_sleep_state>, <&sd_ufs_cd_pins>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 90f8b0916..c2500e5db 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -5809,6 +5809,26 @@ ws-pins {
 				};
 			};
 
+			sdc2_default_state: sdc2-default-state {
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+			};
+
 			sdc2_sleep_state: sdc2-sleep-state {
 				clk-pins {
 					pins = "sdc2_clk";
-- 
2.47.3

[PATCH 2/6] arm64: dts: qcom: sm8250-hdk: Add LT9611UXC HDMI bridge

[ShiTou Hong]

From: redstonee <1516235445@qq.com>

The sm8250-hdk has a video bridge chip LT9611UXC convertng MIPI DSI to HDMI.

Enable the i2c port of the chip, the display controller and DSI port.
Add the pinctrl of LT9611UXC's rst&irq pins.

Signed-off-by: ShiTou Hong <dc_redstone@outlook.com>
---
 arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 123 ++++++++++++++++++++++++
 1 file changed, 123 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index 5975878ea..d92e569d8 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -44,6 +44,18 @@ vreg_s4a_1p8: pm8150-s4 {
 		vin-supply = <&vph_pwr>;
 	};
 
+	lt9611_1v2: lt9611-vdd12-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "LT9611_1V2";
+
+		regulator-always-on;
+		regulator-boot-on;
+
+		vin-supply = <&vph_pwr>;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+	};
+
 	vreg_s6c_0p88: smpc6-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vreg_s6c_0p88";
@@ -63,6 +75,17 @@ key-vol-up {
 			gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
 		};
 	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&lt9611_out>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -396,6 +419,10 @@ &qupv3_id_1 {
 	status = "okay";
 };
 
+&qupv3_id_0 {
+	status = "okay";
+};
+
 &tlmm {
 	gpio-reserved-ranges = <28 4>, <40 4>;
 
@@ -404,6 +431,20 @@ sd_ufs_cd_pins: sd-ufs-cd-pins {
 		function = "gpio";
 		bias-pull-up;
 	};
+
+	lt9611_pins: lt9611-pins {
+		irq-pins {
+			pins = "gpio1";
+			function = "gpio";
+			bias-disable;
+		};
+
+		rst-pins {
+			pins = "gpio2";
+			function = "gpio";
+			output-high;
+		};
+	};
 };
 
 &uart12 {
@@ -486,3 +527,85 @@ &sdhc_2 {
 	pinctrl-0 = <&sdc2_default_state>, <&sd_ufs_cd_pins>;
 	pinctrl-1 = <&sdc2_sleep_state>, <&sd_ufs_cd_pins>;
 };
+
+&adsp {
+	status = "okay";
+	firmware-name = "qcom/sm8250/adsp.mbn";
+};
+
+&cdsp {
+	status = "okay";
+	firmware-name = "qcom/sm8250/cdsp.mbn";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	lt9611_codec: hdmi-bridge@2b {
+		compatible = "lontium,lt9611uxc";
+		reg = <0x2b>;
+		#sound-dai-cells = <1>;
+
+		interrupts-extended = <&tlmm 1 IRQ_TYPE_EDGE_FALLING>;
+		reset-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+
+		vdd-supply = <&lt9611_1v2>;
+		vcc-supply = <&vreg_bob>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&lt9611_pins>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				lt9611_a: endpoint {
+					remote-endpoint = <&mdss_dsi0_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				lt9611_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+};
+
+&gpi_dma0 {
+	status = "okay";
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp {
+	status = "okay";
+};
+
+&mdss_dp_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dsi0 {
+	status = "okay";
+	vdda-supply = <&vreg_l9a_1p2>;
+};
+
+&mdss_dsi0_out {
+	remote-endpoint = <&lt9611_a>;
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+	status = "okay";
+	vdds-supply = <&vreg_l5a_0p88>;
+};
-- 
2.47.3

[PATCH 3/6] arm64: dts: qcom: sm8250-hdk: Add FSA4480 USB-C protocol chip

[ShiTou Hong]

From: redstonee <1516235445@qq.com>

The sm8250-hdk has a USB-C port, which support role-switch and DP altmode.
The USB-C protocol is implemented by the FSA4480 chip.

Enable the i2c port of the chip, add the FSA4480 node,
and set the USB controller to OTG mode.

Signed-off-by: ShiTou Hong <dc_redstone@outlook.com>
---
 arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 105 +++++++++++++++++++++++-
 1 file changed, 104 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index d92e569d8..9ff15d9d7 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/usb/pd.h>
 #include "sm8250.dtsi"
 #include "pm8150.dtsi"
 #include "pm8150b.dtsi"
@@ -415,6 +416,10 @@ &pon_resin {
 	linux,code = <KEY_VOLUMEDOWN>;
 };
 
+&qupv3_id_2 {
+	status = "okay";
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };
@@ -489,6 +494,10 @@ &usb_1_qmpphy {
 	vdda-pll-supply = <&vreg_l9a_1p2>;
 };
 
+&usb_1_qmpphy_out {
+	remote-endpoint = <&pm8150b_typec_mux_in>;
+};
+
 &usb_2_qmpphy {
 	status = "okay";
 	vdda-phy-supply = <&vreg_l18a_0p92>;
@@ -504,13 +513,18 @@ &usb_2 {
 };
 
 &usb_1_dwc3 {
-	dr_mode = "peripheral";
+	dr_mode = "otg";
+	usb-role-switch;
 };
 
 &usb_2_dwc3 {
 	dr_mode = "host";
 };
 
+&usb_1_dwc3_hs_out {
+	remote-endpoint = <&pm8150b_hs_in>;
+};
+
 &venus {
 	status = "okay";
 };
@@ -579,6 +593,28 @@ lt9611_out: endpoint {
 	};
 };
 
+&i2c15 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	fsa4480@43 {
+		compatible = "fcs,fsa4480";
+		reg = <0x43>;
+
+		interrupts-extended = <&tlmm 63 IRQ_TYPE_LEVEL_LOW>;
+
+		vcc-supply = <&vreg_bob>;
+		mode-switch;
+		orientation-switch;
+
+		port {
+			fsa4480_sbu_mux: endpoint {
+				remote-endpoint = <&pm8150b_typec_sbu_out>;
+			};
+		};
+	};
+};
+
 &gpi_dma0 {
 	status = "okay";
 };
@@ -593,6 +629,7 @@ &mdss_dp {
 
 &mdss_dp_out {
 	data-lanes = <0 1>;
+	remote-endpoint = <&usb_1_qmpphy_dp_in>;
 };
 
 &mdss_dsi0 {
@@ -609,3 +646,69 @@ &mdss_dsi0_phy {
 	status = "okay";
 	vdds-supply = <&vreg_l5a_0p88>;
 };
+
+&pm8150b_vbus {
+	regulator-min-microamp = <500000>;
+	regulator-max-microamp = <3000000>;
+	status = "okay";
+};
+
+&pm8150b_typec {
+	status = "okay";
+
+	vdd-pdphy-supply = <&vreg_l2a_3p1>;
+
+	connector {
+		compatible = "usb-c-connector";
+
+		power-role = "source";
+		data-role = "dual";
+		self-powered;
+
+		vbus-supply = <&pm8150b_vbus>;
+
+		source-pdos = <PDO_FIXED(5000, 3000,PDO_FIXED_DUAL_ROLE |
+					 PDO_FIXED_USB_COMM |
+					 PDO_FIXED_DATA_SWAP)>;
+
+		altmodes {
+			displayport {
+				svid = /bits/ 16 <0xff01>;
+				vdo = <0x00001c46>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				pm8150b_hs_in: endpoint {
+					remote-endpoint = <&usb_1_dwc3_hs_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				pm8150b_typec_mux_in: endpoint {
+					remote-endpoint = <&usb_1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				pm8150b_typec_sbu_out: endpoint {
+					remote-endpoint = <&fsa4480_sbu_mux>;
+				};
+			};
+		};
+	};
+};
+
+&usb_1_qmpphy_dp_in {
+	remote-endpoint = <&mdss_dp_out>;
+};
-- 
2.47.3

[PATCH 4/6] arm64: dts: qcom: sm8250-hdk: Enable the PCIe ports

[ShiTou Hong]

From: redstonee <1516235445@qq.com>

Enable the 2 PCIe ports on sm8250-hdk. The pcie0 is for the on-board
ath11k WiFi; the pcie2 is for the M.2 connector.

Signed-off-by: ShiTou Hong <dc_redstone@outlook.com>
---
 arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index 9ff15d9d7..77273b6c2 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -712,3 +712,24 @@ pm8150b_typec_sbu_out: endpoint {
 &usb_1_qmpphy_dp_in {
 	remote-endpoint = <&mdss_dp_out>;
 };
+
+&pcie0 {
+	status = "okay";
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l5a_0p88>;
+	vdda-pll-supply = <&vreg_l9a_1p2>;
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
+	vddpe-3v3-supply = <&vreg_3p3>;
+};
+
+&pcie2_phy {
+	vdda-phy-supply = <&vreg_l5a_0p88>;
+	vdda-pll-supply = <&vreg_l9a_1p2>;
+	status = "okay";
+};
-- 
2.47.3

[PATCH 5/6] arm64: dts: qcom: sm8250-hdk: Add the QCA6390 NIC

[ShiTou Hong]

From: redstonee <1516235445@qq.com>

The sm8250-hdk has a QCA6390 WiFi/BT module.

This commit enables the UART port of BT; adds the QCA6390 PMU node,
the wifi node of pcieport0, the missing regulator of PM8009
which is used by QCA6390, the pinctrl of QCA6390 enable pins.

Signed-off-by: ShiTou Hong <dc_redstone@outlook.com>
---
 arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 125 ++++++++++++++++++++++++
 1 file changed, 125 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index 77273b6c2..eb899c92f 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -32,6 +32,13 @@ vph_pwr: vph-pwr-regulator {
 		regulator-max-microvolt = <3700000>;
 	};
 
+	vreg_3p3: vreg-3p3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_3p3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
 	vreg_s4a_1p8: pm8150-s4 {
 		compatible = "regulator-fixed";
 		regulator-name = "vreg_s4a_1p8";
@@ -87,6 +94,67 @@ hdmi_con: endpoint {
 			};
 		};
 	};
+
+	qca6390-pmu {
+		compatible = "qcom,qca6390-pmu";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&qca6390_pins>;
+
+		vddaon-supply = <&vreg_s6a_0p95>;
+		vddpmu-supply = <&vreg_s2f_0p95>;
+		vddrfa0p95-supply = <&vreg_s2f_0p95>;
+		vddrfa1p3-supply = <&vreg_s8c_1p3>;
+		vddrfa1p9-supply = <&vreg_s5a_1p9>;
+		vddpcie1p3-supply = <&vreg_s8c_1p3>;
+		vddpcie1p9-supply = <&vreg_s5a_1p9>;
+		vddio-supply = <&vreg_s4a_1p8>;
+
+		wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -345,6 +413,13 @@ regulators-2 {
 		vdd-l5-l6-supply = <&vreg_bob>;
 		vdd-l7-supply = <&vreg_s4a_1p8>;
 
+		vreg_s2f_0p95: smps2 {
+			regulator-name = "vreg_s2f_0p95";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <952000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+		};
+
 		vreg_l1f_cam_dvdd1_1p1: ldo1 {
 			regulator-name = "vreg_l1f_cam_dvdd1_1p1";
 			regulator-min-microvolt = <1104000>;
@@ -450,6 +525,39 @@ rst-pins {
 			output-high;
 		};
 	};
+
+	qca6390_pins: qca6390-pins {
+		wlan-enable-pins {
+			pins = "gpio20";
+			function = "gpio";
+			drive-strength = <16>;
+			output-low;
+			bias-pull-up;
+		};
+
+		bt-enable-pins {
+			pins = "gpio21";
+			function = "gpio";
+			drive-strength = <16>;
+			output-low;
+			bias-pull-up;
+		};
+	};
+};
+
+&uart6 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,qca6390-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+	};
 };
 
 &uart12 {
@@ -723,6 +831,23 @@ &pcie0_phy {
 	status = "okay";
 };
 
+&pcieport0 {
+	wifi@0 {
+		compatible = "pci17cb,1101";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+	};
+};
+
 &pcie2 {
 	status = "okay";
 	vddpe-3v3-supply = <&vreg_3p3>;
-- 
2.47.3

[PATCH 6/6] arm64: dts: qcom: sm8250-hdk: Add the 2 LEDs of PM8150b

[ShiTou Hong]

From: redstonee <1516235445@qq.com>

Enable the LED controller of PM8150b, add the LED nodes into it.

Signed-off-by: ShiTou Hong <dc_redstone@outlook.com>
---
 arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index eb899c92f..d15e75a4a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include <dt-bindings/usb/pd.h>
+#include <dt-bindings/leds/common.h>
 #include "sm8250.dtsi"
 #include "pm8150.dtsi"
 #include "pm8150b.dtsi"
@@ -157,6 +158,25 @@ vreg_pmu_pcie_1p8: ldo9 {
 	};
 };
 
+&pm8150b_lpg {
+	status = "okay";
+
+	led@1 {
+		reg = <1>;
+		label = "led-heartbeat";
+		linux,default-trigger = "heartbeat";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@2 {
+		reg = <2>;
+		label = "led-wlan";
+		linux,default-trigger = "none";
+		default-state = "off";
+		color = <LED_COLOR_ID_RED>;
+	};
+};
+
 &apps_rsc {
 	regulators-0 {
 		compatible = "qcom,pm8150-rpmh-regulators";
-- 
2.47.3

Re: [PATCH 6/6] arm64: dts: qcom: sm8250-hdk: Add the 2 LEDs of PM8150b

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: sm8250-hdk: deprecated LED label overrides color in sysfs
--

commit 8610d8172ae62463a8325cbe16b011b5f8fa6fc1
Author: redstonee <1516235445@qq.com>

arm64: dts: qcom: sm8250-hdk: Add the 2 LEDs of PM8150b

This commit enables the pm8150b lpg controller on sm8250-hdk and adds two
child nodes for the green heartbeat and red wlan indicator leds.

> diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> index eb899c92fcfb7..d15e75a4ace5c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> @@ -7,6 +7,7 @@
>  
>  #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>  #include <dt-bindings/usb/pd.h>
> +#include <dt-bindings/leds/common.h>
>  #include "sm8250.dtsi"
>  #include "pm8150.dtsi"
>  #include "pm8150b.dtsi"
> @@ -157,6 +158,25 @@ vreg_pmu_pcie_1p8: ldo9 {
>  	};
>  };
>  
> +&pm8150b_lpg {
> +	status = "okay";
> +
> +	led@1 {
> +		reg = <1>;
> +		label = "led-heartbeat";
> +		linux,default-trigger = "heartbeat";
> +		color = <LED_COLOR_ID_GREEN>;
> +	};
> +
> +	led@2 {
> +		reg = <2>;
> +		label = "led-wlan";
> +		linux,default-trigger = "none";
> +		default-state = "off";
> +		color = <LED_COLOR_ID_RED>;
> +	};
> +};

[Severity: Medium]
When pm8150b_lpg probes in drivers/leds/rgb/leds-qcom-lpg.c, registering
led@1 and led@2 calls:

  devm_led_classdev_register_ext() ->
    led_classdev_register_ext() ->
      led_compose_name() ->
        led_parse_fwnode_props()

In drivers/leds/led-core.c:led_parse_fwnode_props(), the presence of the
deprecated label property causes an early return before color or function
are parsed:

	if (fwnode_property_present(fwnode, "label")) {
		ret = fwnode_property_read_string(fwnode, "label", &props->label);
		if (ret)
			dev_err(dev, "Error parsing 'label' property (%d)\n", ret);
		return;
	}

Because label is set on both nodes in
arch/arm64/boot/dts/qcom/sm8250-hdk.dts, color = <LED_COLOR_ID_GREEN> and
color = <LED_COLOR_ID_RED> are ignored at runtime, and the devices are
registered in sysfs as /sys/class/leds/led-heartbeat and
/sys/class/leds/led-wlan instead of /sys/class/leds/green:heartbeat and
/sys/class/leds/red:wlan.

Since label is also deprecated in
Documentation/devicetree/bindings/leds/common.yaml and
dt-bindings/leds/common.h is already included, should led@1 and led@2 use
the function property instead of label:

	led@1 {
		reg = <1>;
		function = LED_FUNCTION_HEARTBEAT;
		linux,default-trigger = "heartbeat";
		color = <LED_COLOR_ID_GREEN>;
	};

	led@2 {
		reg = <2>;
		function = LED_FUNCTION_WLAN;
		linux,default-trigger = "none";
		default-state = "off";
		color = <LED_COLOR_ID_RED>;
	};

so that the color and function properties take effect?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022113601.2320940-1-dc_redstone@outlook.com?part=6

Re: [PATCH 4/6] arm64: dts: qcom: sm8250-hdk: Enable the PCIe ports

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: undefined phandle reference vreg_3p3 in pcie2 node
--

commit be0d22fcb00f618941a1790f86db070c0405b5a5
Author: redstonee <1516235445@qq.com>

arm64: dts: qcom: sm8250-hdk: Enable the PCIe ports

This commit enables the pcie0 and pcie2 controller and PHY nodes in
arch/arm64/boot/dts/qcom/sm8250-hdk.dts for the on-board WiFi and M.2
connector.

> diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> index 9ff15d9d7f0f6..77273b6c2216a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> @@ -712,3 +712,24 @@ pm8150b_typec_sbu_out: endpoint {
>  &usb_1_qmpphy_dp_in {
>  	remote-endpoint = <&mdss_dp_out>;
>  };
> +
> +&pcie0 {
> +	status = "okay";
> +};
> +
> +&pcie0_phy {
> +	vdda-phy-supply = <&vreg_l5a_0p88>;
> +	vdda-pll-supply = <&vreg_l9a_1p2>;
> +	status = "okay";
> +};
> +
> +&pcie2 {
> +	status = "okay";
> +	vddpe-3v3-supply = <&vreg_3p3>;
> +};

[Severity: Medium]
Does enabling pcie2 with vddpe-3v3-supply = <&vreg_3p3> in
arch/arm64/boot/dts/qcom/sm8250-hdk.dts break building qcom/sm8250-hdk.dtb at
this commit?

Neither arch/arm64/boot/dts/qcom/sm8250-hdk.dts nor any of its included files
(sm8250.dtsi, pm8150.dtsi, pm8150b.dtsi, pm8150l.dtsi) defines the vreg_3p3
label at this point in the series, which causes dtc to fail with a reference
to a non-existent node or label.

The vreg_3p3 fixed-regulator node is only introduced in the subsequent commit
b98ad1ad783f ("arm64: dts: qcom: sm8250-hdk: Add the QCA6390 NIC"). Should the
vreg_3p3 regulator definition be moved into or before this commit so that each
commit in the series builds cleanly for bisection?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022113601.2320940-1-dc_redstone@outlook.com?part=4

Re: [PATCH 1/6] arm64: dts: qcom: sm8250-hdk: Enable the sdhc_2 port

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] arm64: dts: qcom: sm8250-hdk: sd-ufs-cd-pins violates TLMM DT binding schema
--

commit 0b99efa9e9916abab14b14dc1f0beae18f4f1e7f
Author: redstonee <1516235445@qq.com>

arm64: dts: qcom: sm8250-hdk: Enable the sdhc_2 port

This patch adds the default pin configuration state for sdc2 in sm8250.dtsi
and enables the sdhc_2 controller along with its card-detect pin
configuration on the sm8250-hdk board.

> diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> index c1c673086df51..5975878ea0fd2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> @@ -398,6 +398,12 @@ &qupv3_id_1 {
>  
>  &tlmm {
>  	gpio-reserved-ranges = <28 4>, <40 4>;
> +
> +	sd_ufs_cd_pins: sd-ufs-cd-pins {
> +		pins = "gpio77";
> +		function = "gpio";
> +		bias-pull-up;
> +	};
>  };

[Severity: Low]
Does naming this direct child node of &tlmm sd-ufs-cd-pins cause a dtbs_check
schema validation regression?

In Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml,
direct child pin configuration nodes under the tlmm controller must match
the "-state$" pattern (with "-pins$" only allowed for subnodes nested inside
a "-state" node):

  patternProperties:
    "-state$":
      oneOf:
        - $ref: "#/$defs/qcom-sm8250-tlmm-state"
        - patternProperties:
            "-pins$":
              $ref: "#/$defs/qcom-sm8250-tlmm-state"
          additionalProperties: false

Should this node be named with a -state suffix (for example,
sd-ufs-cd-state) to match the binding schema?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022113601.2320940-1-dc_redstone@outlook.com?part=1

Re: [PATCH 5/6] arm64: dts: qcom: sm8250-hdk: Add the QCA6390 NIC

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: sm8250-hdk: vreg_3p3 added after pcie2 references it
- [Low] arm64: dts: qcom: sm8250-hdk: tlmm pin state node names violate schema
--

commit b98ad1ad783f0dda0bddcfceb9a3d14617f06e2d
Author: redstonee <1516235445@qq.com>

arm64: dts: qcom: sm8250-hdk: Add the QCA6390 NIC

This patch adds device tree nodes for the qca6390 wireless and bluetooth
module on the sm8250-hdk board, including its pmu node, regulators, pinctrl
configuration, uart6 bluetooth node, and pcieport0 wifi node.

> diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> index 77273b6c2216a..eb899c92fcfb7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> @@ -32,6 +32,13 @@ vph_pwr: vph-pwr-regulator {
>  		regulator-max-microvolt = <3700000>;
>  	};
>  
> +	vreg_3p3: vreg-3p3-regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vreg_3p3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};

[Severity: Medium]
Should vreg_3p3 be defined in the preceding commit be0d22fcb00f ("arm64: dts:
qcom: sm8250-hdk: Enable the PCIe ports") instead of this patch?

In commit be0d22fcb00f, &pcie2 in arch/arm64/boot/dts/qcom/sm8250-hdk.dts
references <&vreg_3p3>:

	&pcie2 {
		status = "okay";
		vddpe-3v3-supply = <&vreg_3p3>;
	};

Because vreg_3p3 is not defined until this commit (and is not consumed by any
of the qca6390 nodes on pcie0 or uart6), building sm8250-hdk.dtb at commit
be0d22fcb00f fails with a reference to a non-existent node or label
"vreg_3p3", breaking git bisect across the series.

[ ... ]

> @@ -450,6 +525,39 @@ rst-pins {
>  			output-high;
>  		};
>  	};
> +
> +	qca6390_pins: qca6390-pins {
> +		wlan-enable-pins {
> +			pins = "gpio20";
> +			function = "gpio";
> +			drive-strength = <16>;
> +			output-low;
> +			bias-pull-up;
> +		};
> +
> +		bt-enable-pins {
> +			pins = "gpio21";
> +			function = "gpio";
> +			drive-strength = <16>;
> +			output-low;
> +			bias-pull-up;
> +		};
> +	};
> +};

[Severity: Low]
Does the qca6390-pins node name under &tlmm conform to the binding schema in
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml?

The binding specifies unevaluatedProperties: false and requires direct child
pin configuration nodes under &tlmm (which matches "qcom,sm8250-pinctrl") to
end with "-state", while "-pins" is only permitted for nested subnodes inside
a "-state" node:

  patternProperties:
    "-state$":
      oneOf:
        - $ref: "#/$defs/qcom-sm8250-tlmm-state"
        - patternProperties:
            "-pins$":
              $ref: "#/$defs/qcom-sm8250-tlmm-state"
          additionalProperties: false

Because qca6390-pins (as well as sd-ufs-cd-pins and lt9611-pins added under
&tlmm earlier in the series) uses the "-pins" suffix directly under &tlmm,
running dtbs_check on sm8250-hdk.dtb fails schema validation. Should these
top-level pin state nodes under &tlmm use a "-state" suffix instead (for
example, qca6390-default-state)?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022113601.2320940-1-dc_redstone@outlook.com?part=5

Re: [PATCH 2/6] arm64: dts: qcom: sm8250-hdk: Add LT9611UXC HDMI bridge

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: sm8250-hdk: pinctrl node lt9611-pins violates -state schema
- [Medium] arm64: dts: qcom: sm8250-hdk: unlinked mdss_dp and unrelated adsp/cdsp nodes
--

commit b1dadd1c8b42a901f8e62f9b3d2367c950faf2f4
Author: redstonee <1516235445@qq.com>

arm64: dts: qcom: sm8250-hdk: Add LT9611UXC HDMI bridge

This commit enables the LT9611UXC MIPI DSI-to-HDMI bridge on the SM8250 HDK
along with its regulator, HDMI connector, I2C bus, pinctrl state, and MDSS/DSI
nodes, as well as the ADSP, CDSP, and DisplayPort controller nodes.

> diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> index 5975878ea0fd2..d92e569d87410 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts

[ ... ]

> @@ -404,6 +431,20 @@ sd_ufs_cd_pins: sd-ufs-cd-pins {
>  		function = "gpio";
>  		bias-pull-up;
>  	};
> +
> +	lt9611_pins: lt9611-pins {
> +		irq-pins {
> +			pins = "gpio1";
> +			function = "gpio";
> +			bias-disable;
> +		};
> +
> +		rst-pins {
> +			pins = "gpio2";
> +			function = "gpio";
> +			output-high;
> +		};
> +	};
>  };
>  
>  &uart12 {

[Severity: Medium]
Should the lt9611-pins node under &tlmm (as well as sd-ufs-cd-pins from the
preceding commit) be named with a -state suffix, such as lt9611-default-state
or lt9611-state?

In arch/arm64/boot/dts/qcom/sm8250.dtsi, tlmm uses the qcom,sm8250-pinctrl
compatible string. The binding in
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml sets
unevaluatedProperties: false and restricts top-level pin configuration child
nodes to names ending in -state, while -pins is only matched for subnodes
nested inside a -state parent node:

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm8250-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm8250-tlmm-state"
        additionalProperties: false

Naming the top-level child node lt9611-pins causes dtbs_check to fail on
&tlmm and skips validation of the nested irq-pins and rst-pins subnodes.

> @@ -486,3 +527,85 @@ &sdhc_2 {
>  	pinctrl-0 = <&sdc2_default_state>, <&sd_ufs_cd_pins>;
>  	pinctrl-1 = <&sdc2_sleep_state>, <&sd_ufs_cd_pins>;
>  };
> +
> +&adsp {
> +	status = "okay";
> +	firmware-name = "qcom/sm8250/adsp.mbn";
> +};
> +
> +&cdsp {
> +	status = "okay";
> +	firmware-name = "qcom/sm8250/cdsp.mbn";
> +};

[ ... ]

> +&mdss {
> +	status = "okay";
> +};
> +
> +&mdss_dp {
> +	status = "okay";
> +};
> +
> +&mdss_dp_out {
> +	data-lanes = <0 1>;
> +};

[Severity: Medium]
Were &adsp, &cdsp, &mdss_dp, and &mdss_dp_out intended to be included in this
LT9611UXC HDMI bridge patch?

The &adsp and &cdsp remoteproc nodes are unrelated to the MIPI DSI-to-HDMI
bridge and are not mentioned in the commit description.

Additionally, enabling &mdss_dp here before connecting &mdss_dp_out to
usb_1_qmpphy_dp_in (which happens in the follow-up USB-C patch "arm64: dts:
qcom: sm8250-hdk: Add FSA4480 USB-C protocol chip") leaves port@1 of mdss_dp
without a remote-endpoint:

arch/arm64/boot/dts/qcom/sm8250.dtsi:
    port@1 {
        reg = <1>;

        mdss_dp_out: endpoint {
        };
    };

Because add_mdp_components() in drivers/gpu/drm/msm/msm_drv.c skips disabled
interfaces via of_device_is_available(intf), &mdss and &mdss_dsi0 do not
require &mdss_dp to be enabled for the HDMI bridge. When &mdss_dp probes
without a remote-endpoint on port@1, msm_dp_display_probe_tail() in
drivers/gpu/drm/msm/dp/dp_display.c sets dp->next_bridge = NULL instead of
attaching the QMP PHY AUX and Type-C HPD bridges:

    dp->next_bridge = devm_drm_of_get_bridge(&dp->pdev->dev, dp->pdev->dev.of_node, 1, 0);
    if (IS_ERR(dp->next_bridge)) {
        ret = PTR_ERR(dp->next_bridge);
        dp->next_bridge = NULL;
        if (dp->is_edp || ret != -ENODEV)
            return ret;
    }

drm_bridge_connector_init() then falls back to msm_dp_bridge as the HPD
provider and calls msm_dp_bridge_hpd_enable(), which calls
pm_runtime_resume_and_get() and enables internal HPD via
msm_dp_aux_hpd_enable(), keeping the DP controller and RPMHPD_MMCX power
domain permanently resumed.

Should &mdss_dp and &mdss_dp_out be moved to the follow-up USB-C patch where
the DisplayPort graph is connected, and &adsp and &cdsp be split into a
separate commit?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022113601.2320940-1-dc_redstone@outlook.com?part=2

Re: [PATCH 1/6] arm64: dts: qcom: sm8250-hdk: Enable the sdhc_2 port

[Konrad Dybcio]

On 10/22/26 1:35 PM, ShiTou Hong wrote:
> From: redstonee <1516235445@qq.com>
> 
> Signed-off-by: ShiTou Hong <dc_redstone@outlook.com>
> ---

Please fix up your git identity, I'm assuming the author is you,
but we need that to be sure.

Please also write some commit messages - see

https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes

Konrad

[PATCH 1/6] arm64: dts: qcom: sm8250-hdk: Enable the sdhc_2 port

[ShiTou Hong]

The sm8250-hdk has an on-board SD/UFS card slot,
but the SDHCI port hasn't been enabled in the dts,
so we can't use it after booting.

Enable the dts node of SDHCI for the on-board SD card slot.
Add the pinctrl node of the SD card pins.

Co-developed-by: KancyJoe <kancy2333@outlook.com>
Signed-off-by: ShiTou Hong <dc_redstone@outlook.com>
---
 arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 39 +++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index c1c673086..a049d78f5 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -398,6 +398,32 @@ &qupv3_id_1 {
 
 &tlmm {
 	gpio-reserved-ranges = <28 4>, <40 4>;
+
+	sd_ufs_cd_pins: sd-ufs-cd-default-state {
+		pins = "gpio77";
+		function = "gpio";
+		bias-pull-up;
+	};
+
+	sdc2_default: sdc2-default-state {
+		cmd-pins {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data-pins {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		clk-pins {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+	};
 };
 
 &uart12 {
@@ -467,3 +493,16 @@ &usb_2_dwc3 {
 &venus {
 	status = "okay";
 };
+
+&sdhc_2 {
+	status = "okay";
+
+	cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+	vmmc-supply = <&vreg_l9c_2p96>;
+	vqmmc-supply = <&vreg_l6c_2p96>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_default>, <&sd_ufs_cd_pins>;
+	pinctrl-1 = <&sdc2_sleep_state>, <&sd_ufs_cd_pins>;
+};
-- 
2.47.3