From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: x86@kernel.org, Tony Luck <tony.luck@intel.com>,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
Smita.KoralahalliChannabasappa@amd.com,
Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Subject: Re: [PATCH v3 14/17] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems
Date: Mon, 12 May 2025 11:34:01 -0400 [thread overview]
Message-ID: <20250512153401.GA2355@yaz-khff2.amd.com> (raw)
In-Reply-To: <20250509140821.GQaB4MVUiLk-a5FWM-@fat_crate.local>
On Fri, May 09, 2025 at 04:08:21PM +0200, Borislav Petkov wrote:
> On Thu, May 08, 2025 at 11:53:00AM -0400, Yazen Ghannam wrote:
> > Let me flip it around. Why is this check needed at all?
>
> As I said above, some BIOS f*ckup.
>
> > Was there ever a real issue to resolve?
>
> Not that I remember...
>
> > It seems to me the deferred error updates are just following what other code
> > did.
>
> Let's search the web for it:
>
> * https://bbs.archlinux.org/viewtopic.php?id=299379
>
> - silly guests, who cares
>
> * https://gitlab.com/qemu-project/qemu/-/issues/2571
>
> - another misguided qemu...
>
> Aha:
>
> https://lore.kernel.org/lkml/20241219124426.325747-1-pbonzini@redhat.com
>
> the usual virt silly stuff.
>
> > I figure the reason to have the platform give the offset to the OS is so
> > the OS doesn't hard code it (in case it needs to change). These offsets
> > were hard coded in the past (conflict between IBS/THR), and it caused
> > problems when the offsets switched in the hardware. The registers that
> > give the offsets were introduced soon after, I think.
>
> Right.
>
> > So the checks we do are defeating the purpose. The OS is still hard
> > coding the offsets. The goal of this change is to follow the intent of
> > the design. Sometimes we need to let go and trust [the BIOS]. ;)
>
> Look at you being silly :-P
>
> > Now we could update the checks to verify that an offset is not used for
> > multiple interrupt sources.
>
> ... or, we won't do anything until someone in BIOS f*cks up again.
>
> > Let's follow up with the design folks to be sure.
>
> Yah, sounds like we will have to verify them after all. You can see how
> universally widespread the trust in BIOS is...
>
> :-P
>
> In any case, whatever you do, when you axe off stuff, write in the commit
> message why you do so. Silently removing it is making me want to know why it
> is ok now.
>
Right, it sounds like we should take the values from the platform and
just make sure they aren't used for multiple sources. In other words, we
don't hard code the offsets, and we verify that each source has a unique
offset.
I agree we can leave this for now. So I'll drop this part from the patch.
I think this topic can be a separate set, and it should cover all APIC
LVT sources including IBS. I'll add it to the to-do list. :)
Thanks,
Yazen
next prev parent reply other threads:[~2025-05-12 15:34 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 14:54 [PATCH v3 00/17] AMD MCA interrupts rework Yazen Ghannam
2025-04-15 14:54 ` [PATCH v3 01/17] x86/mce: Don't remove sysfs if thresholding sysfs init fails Yazen Ghannam
2025-04-15 14:54 ` [PATCH v3 02/17] x86/mce/amd: Remove return value for mce_threshold_{create,remove}_device() Yazen Ghannam
2025-04-15 14:54 ` [PATCH v3 03/17] x86/mce/amd: Remove smca_banks_map Yazen Ghannam
2025-04-15 14:54 ` [PATCH v3 04/17] x86/mce/amd: Put list_head in threshold_bank Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 05/17] x86/mce: Cleanup bank processing on init Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 06/17] x86/mce: Remove __mcheck_cpu_init_early() Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 07/17] x86/mce: Define BSP-only init Yazen Ghannam
2025-04-17 2:18 ` Borislav Petkov
2025-05-01 17:07 ` Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 08/17] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-04-17 9:52 ` Borislav Petkov
2025-05-01 17:12 ` Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 09/17] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 10/17] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-04-17 12:16 ` Borislav Petkov
2025-05-01 17:23 ` Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 11/17] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 12/17] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 13/17] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-05-07 9:20 ` Borislav Petkov
2025-05-08 15:37 ` Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 14/17] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-05-07 19:35 ` Borislav Petkov
2025-05-08 15:53 ` Yazen Ghannam
2025-05-09 14:08 ` Borislav Petkov
2025-05-12 15:34 ` Yazen Ghannam [this message]
2025-04-15 14:55 ` [PATCH v3 15/17] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-05-09 19:37 ` Borislav Petkov
2025-05-12 15:35 ` Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 16/17] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-04-15 14:55 ` [PATCH v3 17/17] x86/mce: Restore poll settings after storm subsides Yazen Ghannam
2025-05-12 7:46 ` Borislav Petkov
2025-05-12 15:43 ` Yazen Ghannam
2025-05-12 15:53 ` Luck, Tony
2025-05-13 17:44 ` Yazen Ghannam
2025-05-13 17:55 ` Borislav Petkov
2025-05-13 21:06 ` Yazen Ghannam
2025-05-13 22:07 ` Luck, Tony
2025-05-14 14:34 ` Yazen Ghannam
2025-05-15 12:37 ` Borislav Petkov
2025-05-15 15:47 ` Yazen Ghannam
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