From: Vasant Hegde <vasant.hegde@amd.com>
To: <iommu@lists.linux.dev>, <joro@8bytes.org>
Cc: <suravee.suthikulpanit@amd.com>, <wei.huang2@amd.com>,
<jsnitsel@redhat.com>, <jgg@ziepe.ca>,
Vasant Hegde <vasant.hegde@amd.com>
Subject: [PATCH v2 12/16] iommu/amd: Add support for different types of PPR handler
Date: Fri, 28 Jul 2023 05:36:05 +0000 [thread overview]
Message-ID: <20230728053609.165183-13-vasant.hegde@amd.com> (raw)
In-Reply-To: <20230728053609.165183-1-vasant.hegde@amd.com>
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
For AMD IOMMU, the PPR feature is needed to support IO page fault (IOPF).
PPR is enabled per PCI end-point device, and is configured by the PPR bit
in the IOMMU device table entry (i.e DTE[PPR]).
Currently, PPR is enabled for a device when it is initialized for AMD
IOMMU v2API. To support paging for IOPF, the DTE[PPR] bit needs to be
updated when enable/disable IOPF feature.
Introducing struct iommu_dev_data.ppr and enum ppr_handlers to track PPR
setting for each device.
Finally iommu_dev_data.ppr is set only when IOMMU supports PPR. Hence
remove redundant feature support check in set_dte_entry().
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
---
drivers/iommu/amd/amd_iommu_types.h | 7 +++++++
drivers/iommu/amd/iommu.c | 10 ++++------
drivers/iommu/amd/iommu_v2.c | 14 +++++++++++++-
3 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index a066f375ba87..321d361dfb60 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -803,6 +803,12 @@ struct devid_map {
bool cmd_line;
};
+enum ppr_handlers {
+ PPR_HANDLER_NONE, /* No handler specified */
+ PPR_HANDLER_V2API, /* IOMMU v2 API ppr handler */
+ PPR_HANDLER_IOPF, /* IOPF ppr handler */
+};
+
/*
* This struct contains device specific data for the IOMMU
*/
@@ -820,6 +826,7 @@ struct iommu_dev_data {
bool ats_enabled; /* ATS state */
bool pri_tlp; /* PASID TLB required for
PPR completions */
+ enum ppr_handlers ppr;
bool use_vapic; /* Enable device to use vapic mode */
bool defer_attach;
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 5a4170592bf4..e67c6fae452c 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1631,10 +1631,8 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 devid,
if (ats)
flags |= DTE_FLAG_IOTLB;
- if (ppr) {
- if (iommu_feature(iommu, FEATURE_EPHSUP))
- pte_root |= 1ULL << DEV_ENTRY_PPR;
- }
+ if (ppr)
+ pte_root |= 1ULL << DEV_ENTRY_PPR;
if (domain->flags & PD_IOMMUV2_MASK) {
u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
@@ -1727,7 +1725,7 @@ static void do_attach(struct iommu_dev_data *dev_data,
/* Update device table */
set_dte_entry(iommu, dev_data->devid, domain,
- ats, dev_data->iommu_v2);
+ ats, dev_data->ppr);
clone_aliases(iommu, dev_data->dev);
device_flush_dte(dev_data);
@@ -2006,7 +2004,7 @@ static void update_device_table(struct protection_domain *domain)
if (!iommu)
continue;
set_dte_entry(iommu, dev_data->devid, domain,
- dev_data->ats_enabled, dev_data->iommu_v2);
+ dev_data->ats_enabled, dev_data->ppr);
clone_aliases(iommu, dev_data->dev);
}
}
diff --git a/drivers/iommu/amd/iommu_v2.c b/drivers/iommu/amd/iommu_v2.c
index 9bf114382c00..4148cbf069dc 100644
--- a/drivers/iommu/amd/iommu_v2.c
+++ b/drivers/iommu/amd/iommu_v2.c
@@ -740,6 +740,10 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
unsigned long flags;
int ret, tmp;
u32 sbdf;
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
+
+ if (!dev_data)
+ return -ENODEV;
might_sleep();
@@ -762,6 +766,9 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
if (dev_state == NULL)
return -ENOMEM;
+ /* Enable device for PPR support */
+ dev_data->ppr = PPR_HANDLER_V2API;
+
spin_lock_init(&dev_state->lock);
init_waitqueue_head(&dev_state->wq);
dev_state->pdev = pdev;
@@ -832,6 +839,8 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
out_free_dev_state:
kfree(dev_state);
+ dev_data->ppr = PPR_HANDLER_NONE;
+
return ret;
}
EXPORT_SYMBOL(amd_iommu_init_device);
@@ -841,8 +850,9 @@ void amd_iommu_free_device(struct pci_dev *pdev)
struct device_state *dev_state;
unsigned long flags;
u32 sbdf;
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
- if (!amd_iommu_v2_supported())
+ if (!dev_data || !amd_iommu_v2_supported())
return;
sbdf = get_pci_sbdf_id(pdev);
@@ -859,6 +869,8 @@ void amd_iommu_free_device(struct pci_dev *pdev)
spin_unlock_irqrestore(&state_lock, flags);
+ dev_data->ppr = PPR_HANDLER_NONE;
+
put_device_state(dev_state);
free_device_state(dev_state);
}
--
2.31.1
next prev parent reply other threads:[~2023-07-28 5:40 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-28 5:35 [PATCH v2 00/16] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
2023-07-28 5:35 ` [PATCH v2 01/16] iommu/amd: Remove unused amd_io_pgtable.pt_root variable Vasant Hegde
2023-07-28 13:17 ` Jason Gunthorpe
2023-07-28 5:35 ` [PATCH v2 02/16] iommu/amd: Consolidate timeout pre-define to amd_iommu_type.h Vasant Hegde
2023-07-28 13:48 ` Jason Gunthorpe
2023-07-28 5:35 ` [PATCH v2 03/16] iommu/amd: Consolidate logic to allocate protection domain Vasant Hegde
2023-07-28 13:49 ` Jason Gunthorpe
2023-07-28 5:35 ` [PATCH v2 04/16] iommu/amd: Refactor protection domain allocation code Vasant Hegde
2023-07-28 13:53 ` Jason Gunthorpe
2023-07-31 6:30 ` Vasant Hegde
2023-07-31 12:03 ` Jason Gunthorpe
2023-07-28 5:35 ` [PATCH v2 05/16] iommu/amd/iommu_v2: Use protection_domain in struct device_state Vasant Hegde
2023-07-28 14:00 ` Jason Gunthorpe
2023-07-28 5:35 ` [PATCH v2 06/16] iommu/amd: Introduce helper functions for managing GCR3 table Vasant Hegde
2023-07-28 14:09 ` Jason Gunthorpe
2023-07-31 10:40 ` Vasant Hegde
2023-07-28 5:36 ` [PATCH v2 07/16] iommu/amd: Use struct protection_domain in helper functions Vasant Hegde
2023-07-28 14:10 ` Jason Gunthorpe
2023-07-28 5:36 ` [PATCH v2 08/16] iommu/amd: Do not set amd_iommu_pgtable in pass-through mode Vasant Hegde
2023-07-28 14:11 ` Jason Gunthorpe
2023-07-31 6:35 ` Vasant Hegde
2023-07-28 5:36 ` [PATCH v2 09/16] iommu/amd: Miscellaneous clean up when free domain Vasant Hegde
2023-07-28 14:13 ` Jason Gunthorpe
2023-07-31 9:39 ` Vasant Hegde
2023-07-28 5:36 ` [PATCH v2 10/16] iommu/amd: Modify logic for checking GT and PPR features Vasant Hegde
2023-07-28 14:24 ` Jason Gunthorpe
2023-07-31 11:51 ` Vasant Hegde
2023-07-28 5:36 ` [PATCH v2 11/16] iommu/amd: Rename ats related variables Vasant Hegde
2023-07-28 14:27 ` Jason Gunthorpe
2023-07-31 9:15 ` Vasant Hegde
2023-07-28 5:36 ` Vasant Hegde [this message]
2023-07-28 14:31 ` [PATCH v2 12/16] iommu/amd: Add support for different types of PPR handler Jason Gunthorpe
2023-07-31 8:02 ` Vasant Hegde
2023-07-31 12:11 ` Jason Gunthorpe
2023-07-31 12:28 ` Vasant Hegde
2023-07-28 5:36 ` [PATCH v2 13/16] iommu/amd: Introduce iommu_dev_data.flags to track device capabilities Vasant Hegde
2023-07-28 14:38 ` Jason Gunthorpe
2023-07-31 7:57 ` Vasant Hegde
2023-07-31 12:08 ` Jason Gunthorpe
2023-08-04 6:40 ` Vasant Hegde
2023-07-28 5:36 ` [PATCH v2 14/16] iommu/amd: Enable device ATS/PASID/PRI capabilities independently Vasant Hegde
2023-07-28 14:40 ` Jason Gunthorpe
2023-07-28 5:36 ` [PATCH v2 15/16] iommu/amd: Initialize iommu_device->max_pasids Vasant Hegde
2023-07-28 14:46 ` Jason Gunthorpe
2023-07-31 7:03 ` Vasant Hegde
2023-07-31 12:07 ` Jason Gunthorpe
2023-07-31 16:04 ` Vasant Hegde
2023-07-28 5:36 ` [PATCH v2 16/16] iommu/amd: Simplify amd_iommu_device_info() Vasant Hegde
2023-07-28 14:47 ` Jason Gunthorpe
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