Re: PATCH: Fix ll/sc for mips (take 3)

[Hartvig Ekner <hartvige@mips.com>]

Some of MIPS's cores do externalize the event of a "LL" and make it
visible on the bus interface. Similarly, the SC is externalized and
requires a go/nogo response from the system logic. Think of it as
putting a shared LLAddr & LLBit outside the processor. The SC will
only succeed if the internal LLBit is ok *and* the external logic gives
the go-ahead as well.

The reasoning behind all this is that one can then utilize LL/SC in
multi CPU systems without full coherency support being required.

But then again, this might not be relevant for MIPS/Linux as it will not
run without full HW coherency on multiple CPUs?

/Hartvig

Maciej W. Rozycki writes:
> 
> On Tue, 5 Feb 2002, Ralf Baechle wrote:
> 
> > Some of the processor manuals explicitly note that the execution of a
> > ll instruction may not be visible at all externally.  That's the case if
> > the address is already in a primary cache line in exclusive (ll) or
> > dirty (sc) state.  That makes even if a processor supports full coherency
> > since there is no reason to indicate the update to any other external
> > agent.  Or am I missing something?
> 
>  By definition, apart from an ordinary load, an "ll" does only the
> following two additional actions:
> 
> 1. Loads the LLAddr register (it's visible in CP0, at least in certain
> implementations) to set up the ll comparator. 
> 
> 2. Sets the LLbit flip-flop to set the ll state to valid initially.
> 
> None of the actions should normally involve externally visible activity. 
> 
> -- 
> +  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
> +--------------------------------------------------------------+
> +        e-mail: macro@ds2.pg.gda.pl, PGP key available        +
> 
> 


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