[PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[Steven J. Hill]

The ISA exception bit selects whether exceptions are taken in classic
or microMIPS mode. This bit is Config3.ISAOnExc and was improperly
defined as bits 16 and 17 instead of just bit 16. A new function was
added so that platforms could set this bit when running a kernel
compiled with only microMIPS instructions.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
---
Changes from v5:
* Make 'set_micromips_exception_mode' function to always be called.

 arch/mips/include/asm/mipsregs.h |   18 +++++++++++++++++-
 arch/mips/kernel/cpu-probe.c     |    3 ---
 arch/mips/kernel/traps.c         |    5 +++++
 3 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 87e6207..cc0f5d7 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -596,7 +596,7 @@
 #define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
-#define MIPS_CONF3_ISA_OE	(_ULCAST_(3) << 16)
+#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
 #define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
 
 #define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
@@ -1161,6 +1161,22 @@ do {									\
 #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
 
 /*
+ * Set exceptions to be taken in microMIPS mode only, otherwise
+ * set for classic exceptions.
+ */
+static inline void set_micromips_exception_mode(void)
+{
+	unsigned int config3 = read_c0_config3();
+
+#ifdef CONFIG_CPU_MICROMIPS
+	if (config3 & MIPS_CONF3_ISA)
+		write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
+	else
+#endif
+		write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
+}
+
+/*
  * Macros to access the floating point coprocessor control registers
  */
 #define read_32bit_cp1_register(source)					\
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c6568bf..b0d04a2 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -272,9 +272,6 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 		c->options |= MIPS_CPU_ULRI;
 	if (config3 & MIPS_CONF3_ISA)
 		c->options |= MIPS_CPU_MICROMIPS;
-#ifdef CONFIG_CPU_MICROMIPS
-	write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
-#endif
 	if (config3 & MIPS_CONF3_VZ)
 		c->ases |= MIPS_ASE_VZ;
 
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a75ae40..151ed59 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1837,6 +1837,11 @@ void __init trap_init(void)
 			ebase += (read_c0_ebase() & 0x3ffff000);
 	}
 
+	/*
+	 * Set microMIPS exceptions for platforms that support it.
+	 */
+	set_micromips_exception_mode();
+
 	if (board_ebase_setup)
 		board_ebase_setup();
 	per_cpu_trap_init(true);
-- 
1.7.2.5

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[Sergei Shtylyov]

Hello.

On 06/05/2013 11:49 PM, Steven J. Hill wrote:

> The ISA exception bit selects whether exceptions are taken in classic
> or microMIPS mode. This bit is Config3.ISAOnExc and was improperly
> defined as bits 16 and 17 instead of just bit 16. A new function was
> added so that platforms could set this bit when running a kernel
> compiled with only microMIPS instructions.

     Ahem, isn't that function a material for another patch?

> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
> Changes from v5:
> * Make 'set_micromips_exception_mode' function to always be called.
>
>   arch/mips/include/asm/mipsregs.h |   18 +++++++++++++++++-
>   arch/mips/kernel/cpu-probe.c     |    3 ---
>   arch/mips/kernel/traps.c         |    5 +++++
>   3 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
> index 87e6207..cc0f5d7 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -596,7 +596,7 @@
>   #define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
>   #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
>   #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
> -#define MIPS_CONF3_ISA_OE	(_ULCAST_(3) << 16)
> +#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
>   #define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
>   
>   #define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
> @@ -1161,6 +1161,22 @@ do {									\
>   #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
>   
>   /*
> + * Set exceptions to be taken in microMIPS mode only, otherwise
> + * set for classic exceptions.
> + */
> +static inline void set_micromips_exception_mode(void)
> +{
> +	unsigned int config3 = read_c0_config3();
> +
> +#ifdef CONFIG_CPU_MICROMIPS
> +	if (config3 & MIPS_CONF3_ISA)
> +		write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
> +	else
> +#endif
> +		write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
> +}
> +
> +/*
>    * Macros to access the floating point coprocessor control registers
>    */
>   #define read_32bit_cp1_register(source)					\
[...]
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index a75ae40..151ed59 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -1837,6 +1837,11 @@ void __init trap_init(void)
>   			ebase += (read_c0_ebase() & 0x3ffff000);
>   	}
>   
> +	/*
> +	 * Set microMIPS exceptions for platforms that support it.
> +	 */
> +	set_micromips_exception_mode();

     If we have reduced the call sites to 1, do we still need the 
function? :-)

WBR, Sergei

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[David Daney]

On 06/05/2013 12:49 PM, Steven J. Hill wrote:
> The ISA exception bit selects whether exceptions are taken in classic
> or microMIPS mode. This bit is Config3.ISAOnExc and was improperly
> defined as bits 16 and 17 instead of just bit 16. A new function was
> added so that platforms could set this bit when running a kernel
> compiled with only microMIPS instructions.
>
> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
> Changes from v5:
> * Make 'set_micromips_exception_mode' function to always be called.

Version 5 was better in my opinion...


>
>   arch/mips/include/asm/mipsregs.h |   18 +++++++++++++++++-
>   arch/mips/kernel/cpu-probe.c     |    3 ---
>   arch/mips/kernel/traps.c         |    5 +++++
>   3 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
> index 87e6207..cc0f5d7 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -596,7 +596,7 @@
>   #define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
>   #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
>   #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
> -#define MIPS_CONF3_ISA_OE	(_ULCAST_(3) << 16)
> +#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
>   #define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
>
>   #define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
> @@ -1161,6 +1161,22 @@ do {									\
>   #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
>
>   /*
> + * Set exceptions to be taken in microMIPS mode only, otherwise
> + * set for classic exceptions.
> + */
> +static inline void set_micromips_exception_mode(void)
> +{
> +	unsigned int config3 = read_c0_config3();
> +
> +#ifdef CONFIG_CPU_MICROMIPS
> +	if (config3 & MIPS_CONF3_ISA)
> +		write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
> +	else
> +#endif
> +		write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);

You can only manipulate this bit if you know microMIPS is supported.  So 
I think you should either not touch it for the non-microMIPS case, or 
make the write conditional on the presence of microMIPS support in the CPU.

David Daney


> +}
> +
> +/*

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[David Daney]

On 06/05/2013 01:01 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 06/05/2013 11:49 PM, Steven J. Hill wrote:
>
>> The ISA exception bit selects whether exceptions are taken in classic
>> or microMIPS mode. This bit is Config3.ISAOnExc and was improperly
>> defined as bits 16 and 17 instead of just bit 16. A new function was
>> added so that platforms could set this bit when running a kernel
>> compiled with only microMIPS instructions.
>
>      Ahem, isn't that function a material for another patch?


I think you might be going overboard.  The entire patch relates to 
exactly one bit a config register, can't you let it be a single patch?

David Daney

>
>> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
>> ---
>> Changes from v5:
>> * Make 'set_micromips_exception_mode' function to always be called.
>>
>>   arch/mips/include/asm/mipsregs.h |   18 +++++++++++++++++-
>>   arch/mips/kernel/cpu-probe.c     |    3 ---
>>   arch/mips/kernel/traps.c         |    5 +++++
>>   3 files changed, 22 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/mips/include/asm/mipsregs.h
>> b/arch/mips/include/asm/mipsregs.h
>> index 87e6207..cc0f5d7 100644
>> --- a/arch/mips/include/asm/mipsregs.h
>> +++ b/arch/mips/include/asm/mipsregs.h
>> @@ -596,7 +596,7 @@
>>   #define MIPS_CONF3_RXI        (_ULCAST_(1) << 12)
>>   #define MIPS_CONF3_ULRI        (_ULCAST_(1) << 13)
>>   #define MIPS_CONF3_ISA        (_ULCAST_(3) << 14)
>> -#define MIPS_CONF3_ISA_OE    (_ULCAST_(3) << 16)
>> +#define MIPS_CONF3_ISA_OE    (_ULCAST_(1) << 16)
>>   #define MIPS_CONF3_VZ        (_ULCAST_(1) << 23)
>>   #define MIPS_CONF4_MMUSIZEEXT    (_ULCAST_(255) << 0)
>> @@ -1161,6 +1161,22 @@ do {                                    \
>>   #define write_c0_brcm_sleepcount(val)
>> __write_32bit_c0_register($22, 7, val)
>>   /*
>> + * Set exceptions to be taken in microMIPS mode only, otherwise
>> + * set for classic exceptions.
>> + */
>> +static inline void set_micromips_exception_mode(void)
>> +{
>> +    unsigned int config3 = read_c0_config3();
>> +
>> +#ifdef CONFIG_CPU_MICROMIPS
>> +    if (config3 & MIPS_CONF3_ISA)
>> +        write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
>> +    else
>> +#endif
>> +        write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
>> +}
>> +
>> +/*
>>    * Macros to access the floating point coprocessor control registers
>>    */
>>   #define read_32bit_cp1_register(source)                    \
> [...]
>> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
>> index a75ae40..151ed59 100644
>> --- a/arch/mips/kernel/traps.c
>> +++ b/arch/mips/kernel/traps.c
>> @@ -1837,6 +1837,11 @@ void __init trap_init(void)
>>               ebase += (read_c0_ebase() & 0x3ffff000);
>>       }
>> +    /*
>> +     * Set microMIPS exceptions for platforms that support it.
>> +     */
>> +    set_micromips_exception_mode();
>
>      If we have reduced the call sites to 1, do we still need the
> function? :-)
>
> WBR, Sergei
>
>
>
>

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[Steven J. Hill]

On 06/05/2013 03:53 PM, David Daney wrote:
>
> You can only manipulate this bit if you know microMIPS is supported.  So
> I think you should either not touch it for the non-microMIPS case, or
> make the write conditional on the presence of microMIPS support in the CPU.
>
I decided to surround with SYS_SUPPORTS_MICROMIPS so the function could 
be optimized out in v7 of the patch.

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[Steven J. Hill]

On 06/05/2013 03:53 PM, David Daney wrote:
>
> You can only manipulate this bit if you know microMIPS is supported.  So
> I think you should either not touch it for the non-microMIPS case, or
> make the write conditional on the presence of microMIPS support in the CPU.
>
I decided to surround with SYS_SUPPORTS_MICROMIPS so the function could 
be optimized out in v7 of the patch.

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[Jonas Gorski]

On Wed, Jun 5, 2013 at 11:15 PM, Steven J. Hill <Steven.Hill@imgtec.com> wrote:
> On 06/05/2013 03:53 PM, David Daney wrote:
>>
>>
>> You can only manipulate this bit if you know microMIPS is supported.  So
>> I think you should either not touch it for the non-microMIPS case, or
>> make the write conditional on the presence of microMIPS support in the
>> CPU.
>>
> I decided to surround with SYS_SUPPORTS_MICROMIPS so the function could be
> optimized out in v7 of the patch.

Since this is (AFAICT) run after cpu_probe, and cpu probe sets
MIPS_CPU_MICROMIPS in options[0] if config3 has  MIPS_CONF3_ISA set
(as seen in the context), couldn't you do just the following in
cpu_trap:

	if (cpu_has_mmips) {
		unsigned int config3 = read_c0_config3();

		if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
			write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
		else
			write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
	}


Regards
Jonas

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[David Daney]

On 06/05/2013 02:23 PM, Jonas Gorski wrote:
> On Wed, Jun 5, 2013 at 11:15 PM, Steven J. Hill <Steven.Hill@imgtec.com> wrote:
>> On 06/05/2013 03:53 PM, David Daney wrote:
>>>
>>>
>>> You can only manipulate this bit if you know microMIPS is supported.  So
>>> I think you should either not touch it for the non-microMIPS case, or
>>> make the write conditional on the presence of microMIPS support in the
>>> CPU.
>>>
>> I decided to surround with SYS_SUPPORTS_MICROMIPS so the function could be
>> optimized out in v7 of the patch.
>
> Since this is (AFAICT) run after cpu_probe, and cpu probe sets
> MIPS_CPU_MICROMIPS in options[0] if config3 has  MIPS_CONF3_ISA set
> (as seen in the context), couldn't you do just the following in
> cpu_trap:
>
> 	if (cpu_has_mmips) {
> 		unsigned int config3 = read_c0_config3();
>
> 		if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
> 			write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
> 		else
> 			write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
> 	}
>

Yes, that would work.  It even looks nicer.

David Daney



>
> Regards
> Jonas
>
>

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[Sergei Shtylyov]

On 06/06/2013 01:07 AM, David Daney wrote:
> On 06/05/2013 01:01 PM, Sergei Shtylyov wrote:
>> Hello.
>>
>> On 06/05/2013 11:49 PM, Steven J. Hill wrote:
>>
>>> The ISA exception bit selects whether exceptions are taken in classic
>>> or microMIPS mode. This bit is Config3.ISAOnExc and was improperly
>>> defined as bits 16 and 17 instead of just bit 16. A new function was
>>> added so that platforms could set this bit when running a kernel
>>> compiled with only microMIPS instructions.
>>
>>      Ahem, isn't that function a material for another patch?
>
>
> I think you might be going overboard.  The entire patch relates to 
> exactly one bit a config register, can't you let it be a single patch?

    The purpose of the patch declared in its subject is just to fix the 
bit itself.
Instead the patch does zillion other things, which IMHO not even always 
can be
considered fixes, so no, I'm not feeling like I'm going overboard with this.

> David Daney

WBR, Sergei

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[Steven J. Hill]

On 06/05/2013 04:23 PM, Jonas Gorski wrote:
>
> 	if (cpu_has_mmips) {
> 		unsigned int config3 = read_c0_config3();
>
> 		if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
> 			write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
> 		else
> 			write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
> 	}
>
>
I like this being in 'trap_init' instead. Any objections?

Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit.

[Steven J. Hill]

On 06/05/2013 04:23 PM, Jonas Gorski wrote:
>
> 	if (cpu_has_mmips) {
> 		unsigned int config3 = read_c0_config3();
>
> 		if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
> 			write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
> 		else
> 			write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
> 	}
>
>
I like this being in 'trap_init' instead. Any objections?