From: "Bowman, Terry" <terry.bowman@amd.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
dan.j.williams@intel.com, bhelgaas@google.com,
shiju.jose@huawei.com, ming.li@zohomail.com,
Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,
lukas@wunner.de, Benjamin.Cheatham@amd.com,
sathyanarayanan.kuppuswamy@linux.intel.com,
linux-cxl@vger.kernel.org, alucerop@amd.com, ira.weiny@intel.com,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [RESEND v13 00/25] Enable CXL PCIe Port Protocol Error handling and logging
Date: Thu, 4 Dec 2025 11:30:45 -0600 [thread overview]
Message-ID: <00537640-96a1-4476-afd4-c8c4894d7931@amd.com> (raw)
In-Reply-To: <20251104221200.GA1874852@bhelgaas>
On 11/4/2025 4:12 PM, Bjorn Helgaas wrote:
> On Tue, Nov 04, 2025 at 03:54:21PM -0600, Bowman, Terry wrote:
>>
>>
>> On 11/4/2025 1:11 PM, Bjorn Helgaas wrote:
>>> On Tue, Nov 04, 2025 at 11:02:40AM -0600, Terry Bowman wrote:
>>>> This patchset updates CXL Protocol Error handling for CXL Ports and CXL
>>>> Endpoints (EP). Previous versions of this series can be found here:
>>>> https://lore.kernel.org/linux-cxl/20250925223440.3539069-1-terry.bowman@amd.com/
>>>> ...
>>>> Terry Bowman (24):
>>>> CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h
>>>> PCI/CXL: Introduce pcie_is_cxl()
>>>> cxl/pci: Remove unnecessary CXL Endpoint handling helper functions
>>>> cxl/pci: Remove unnecessary CXL RCH handling helper functions
>>>> cxl: Move CXL driver's RCH error handling into core/ras_rch.c
>>>> CXL/AER: Replace device_lock() in cxl_rch_handle_error_iter() with
>>>> guard() lock
>>>> CXL/AER: Move AER drivers RCH error handling into pcie/aer_cxl_rch.c
>>>> PCI/AER: Report CXL or PCIe bus error type in trace logging
>>>> cxl/pci: Update RAS handler interfaces to also support CXL Ports
>>>> cxl/pci: Log message if RAS registers are unmapped
>>>> cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports
>>>> cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors
>>>> cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers
>>>> CXL/PCI: Introduce PCI_ERS_RESULT_PANIC
>>>> CXL/AER: Introduce pcie/aer_cxl_vh.c in AER driver for forwarding CXL
>>>> errors
>>>> cxl: Introduce cxl_pci_drv_bound() to check for bound driver
>>>> cxl: Change CXL handlers to use guard() instead of scoped_guard()
>>>> cxl/pci: Introduce CXL protocol error handlers for Endpoints
>>>> CXL/PCI: Introduce CXL Port protocol error handlers
>>>> PCI/AER: Dequeue forwarded CXL error
>>>> CXL/PCI: Export and rename merge_result() to pci_ers_merge_result()
>>>> CXL/PCI: Introduce CXL uncorrectable protocol error recovery
>>>> CXL/PCI: Enable CXL protocol errors during CXL Port probe
>>>> CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup
>>> Is the mix of "CXL/PCI" vs "cxl/pci" in the above telling me
>>> something, or should they all match?
>>>
>>> As a rule of thumb, I'm going to look at things that start with "PCI"
>>> and skip most of the rest on the assumption that the rest only have
>>> incidental effects on PCI.
>>
>> I think there was logic behind the (un)capitalized but I forget the
>> reasoning. It's better to keep it simple. I'll change to use
>> PCI/CXL and AER/CXL.
>
> I don't know what "AER/CXL" means. I think "PCI" and "CXL" are the
> big chunks here and one of them should be first in the prefix.
>
> I do think there's value in using "PCI/AER" for things specific to AER
> and "PCI/ERR" for more generic PCI error handling, and maybe "PCI/CXL"
> for significant CXL-related things in drivers/pci/.
I was informed any patch touching PCI files requires a PCI maintainer
review or acknowledgment. I misunderstood how to communicate this.
In my workflow, I used uppercase tags like PCI or AER to indicate that
a patch needed PCI review or ack. For example, when I wrote CXL/PCI, I
intended to signal that the patch was primarily CXL-related but in a
PCI context, and therefore might need PCI review.
To avoid confusion in the future, can you advise on the best way to
indicate a patch needs your PCI review—even if the PCI changes are
minor and don’t warrant leading with the PCI label?
Also, can you review the following patches?
[RESEND v13 01/25] CXL-PCI-Move-CXL-DVSEC-definitions-into-uapi-lin
[RESEND v13 02/25] PCI-CXL-Introduce-pcie_is_cxl
[RESEND v13 07/25] CXL-AER-Replace-device_lock-in-cxl_rch_handle_er
[RESEND v13 08/25] CXL-AER-Move-AER-drivers-RCH-error-handling-into
[RESEND v13 16/25] CXL-AER-Introduce-pcie-aer_cxl_vh.c-in-AER-drive
[RESEND v13 20/25] CXL-PCI-Introduce-CXL-Port-protocol-error-handle
[RESEND v13 22/25] CXL-PCI-Export-and-rename-merge_result-to-pci_er
[RESEND v13 23/25] CXL-PCI-Introduce-CXL-uncorrectable-protocol-err
[RESEND v13 25/25] CXL-PCI-Disable-CXL-protocol-error-interrupts-du
-Terry
next prev parent reply other threads:[~2025-12-04 17:30 UTC|newest]
Thread overview: 103+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 17:02 [RESEND v13 00/25] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-11-04 17:02 ` [RESEND v13 01/25] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2025-11-04 17:50 ` Jonathan Cameron
2025-11-19 3:19 ` dan.j.williams
2025-12-08 18:04 ` Bjorn Helgaas
2025-12-08 22:13 ` Bowman, Terry
2025-11-04 17:02 ` [RESEND v13 02/25] PCI/CXL: Introduce pcie_is_cxl() Terry Bowman
2025-11-04 17:52 ` Jonathan Cameron
2025-11-19 3:19 ` dan.j.williams
2025-11-19 15:55 ` Bowman, Terry
2025-11-19 23:34 ` dan.j.williams
2025-11-21 20:31 ` Gregory Price
2025-11-04 17:02 ` [RESEND v13 03/25] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-11-04 17:53 ` Jonathan Cameron
2025-11-19 3:20 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 04/25] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2025-11-19 3:20 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 05/25] cxl: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c Terry Bowman
2025-11-19 3:20 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 06/25] cxl: Move CXL driver's RCH error handling into core/ras_rch.c Terry Bowman
2025-11-04 18:03 ` Jonathan Cameron
2025-11-19 3:20 ` dan.j.williams
2025-11-19 16:07 ` Bowman, Terry
2025-11-04 17:02 ` [RESEND v13 07/25] CXL/AER: Replace device_lock() in cxl_rch_handle_error_iter() with guard() lock Terry Bowman
2025-11-04 18:05 ` Jonathan Cameron
2025-11-04 19:53 ` Dave Jiang
2025-11-19 3:20 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 08/25] CXL/AER: Move AER drivers RCH error handling into pcie/aer_cxl_rch.c Terry Bowman
2025-11-19 3:20 ` dan.j.williams
2025-11-19 8:26 ` Lukas Wunner
2025-11-19 23:36 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 09/25] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-11-04 18:08 ` Jonathan Cameron
2025-11-04 18:26 ` Bjorn Helgaas
2025-11-04 17:02 ` [RESEND v13 10/25] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-11-04 18:10 ` Jonathan Cameron
2025-11-11 8:17 ` Alison Schofield
2025-11-19 3:19 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 11/25] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-11-19 3:27 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 12/25] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-11-19 21:23 ` dan.j.williams
2025-11-19 22:02 ` Bowman, Terry
2025-11-19 23:40 ` dan.j.williams
2025-11-21 14:56 ` Bowman, Terry
2025-11-04 17:02 ` [RESEND v13 13/25] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-11-05 8:30 ` Alejandro Lucero Palau
2025-11-19 22:00 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 14/25] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-11-04 18:15 ` Jonathan Cameron
2025-11-04 20:03 ` Dave Jiang
2025-11-11 8:23 ` Alison Schofield
2025-11-04 17:02 ` [RESEND v13 15/25] CXL/PCI: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2025-11-04 19:03 ` Bjorn Helgaas
2025-11-20 0:17 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 16/25] CXL/AER: Introduce pcie/aer_cxl_vh.c in AER driver for forwarding CXL errors Terry Bowman
2025-11-20 0:44 ` dan.j.williams
2025-11-20 0:53 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 17/25] cxl: Introduce cxl_pci_drv_bound() to check for bound driver Terry Bowman
2025-11-05 17:51 ` Gregory Price
2025-11-05 19:03 ` Gregory Price
2025-11-05 22:26 ` Gregory Price
2025-11-06 17:11 ` Gregory Price
2025-11-06 23:32 ` Bowman, Terry
2025-11-11 8:33 ` Alison Schofield
2025-11-13 21:42 ` Alison Schofield
2025-11-13 22:39 ` Bowman, Terry
2025-11-20 1:24 ` dan.j.williams
2025-11-04 17:02 ` [RESEND v13 18/25] cxl: Change CXL handlers to use guard() instead of scoped_guard() Terry Bowman
2025-11-04 18:18 ` Jonathan Cameron
2025-11-04 20:15 ` Dave Jiang
2025-11-04 17:02 ` [RESEND v13 19/25] cxl/pci: Introduce CXL protocol error handlers for Endpoints Terry Bowman
2025-11-04 18:29 ` Jonathan Cameron
2025-11-04 19:09 ` Bjorn Helgaas
2025-11-04 17:03 ` [RESEND v13 20/25] CXL/PCI: Introduce CXL Port protocol error handlers Terry Bowman
2025-11-04 18:32 ` Jonathan Cameron
2025-11-04 21:20 ` Dave Jiang
2025-11-04 21:27 ` Bowman, Terry
2025-11-04 23:39 ` Dave Jiang
2025-11-04 17:03 ` [RESEND v13 21/25] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-11-04 18:40 ` Jonathan Cameron
2025-11-04 18:45 ` Bjorn Helgaas
2025-11-20 3:33 ` dan.j.williams
2025-11-04 17:03 ` [RESEND v13 22/25] CXL/PCI: Export and rename merge_result() to pci_ers_merge_result() Terry Bowman
2025-11-04 18:41 ` Jonathan Cameron
2025-11-04 19:03 ` Bjorn Helgaas
2025-11-14 15:20 ` Bowman, Terry
2025-11-14 16:09 ` Jonathan Cameron
2025-11-04 17:03 ` [RESEND v13 23/25] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-11-04 18:47 ` Jonathan Cameron
2025-11-04 23:43 ` Dave Jiang
2025-11-05 14:59 ` Bowman, Terry
2025-11-05 16:10 ` Dave Jiang
2025-11-11 8:37 ` Alison Schofield
2025-12-08 18:40 ` Bjorn Helgaas
2025-11-04 17:03 ` [RESEND v13 24/25] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-11-04 17:03 ` [RESEND v13 25/25] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-11-20 3:10 ` dan.j.williams
2025-11-04 19:11 ` [RESEND v13 00/25] Enable CXL PCIe Port Protocol Error handling and logging Bjorn Helgaas
2025-11-04 21:54 ` Bowman, Terry
2025-11-04 22:12 ` Bjorn Helgaas
2025-12-04 17:30 ` Bowman, Terry [this message]
2025-12-08 18:42 ` Bjorn Helgaas
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