Re: [RESEND v13 12/25] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports

[<dan.j.williams@intel.com>]

Terry Bowman wrote:
> CXL currently has separate trace routines for CXL Port errors and CXL
> Endpoint errors. This is inconvenient for the user because they must enable
> 2 sets of trace routines. Make updates to the trace logging such that a
> single trace routine logs both CXL Endpoint and CXL Port protocol errors.

No, this is not inconvient, this is required for compatible evolution of
tracepoints. The change in this patch breaks compatibility as it
violates the expectation the type and order of TP_ARGS does not change
from one kernel to next.

> Keep the trace log fields 'memdev' and 'host'. While these are not accurate
> for non-Endpoints the fields will remain as-is to prevent breaking
> userspace RAS trace consumers.
> 
> Add serial number parameter to the trace logging. This is used for EPs
> and 0 is provided for CXL port devices without a serial number.
> 
> Leave the correctable and uncorrectable trace routines' TP_STRUCT__entry()
> unchanged with respect to member data types and order.
> 
> Below is output of correctable and uncorrectable protocol error logging.
> CXL Root Port and CXL Endpoint examples are included below.
> 
> Root Port:
> cxl_aer_correctable_error: memdev=0000:0c:00.0 host=pci0000:0c serial: 0 status='CRC Threshold Hit'
> cxl_aer_uncorrectable_error: memdev=0000:0c:00.0 host=pci0000:0c serial: 0 status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Parity Error'

A root port is not a "memdev", another awkward side effect of trying to
combine 2 trace points with different use cases.

So a NAK from me for this change (unless there is an strong reason for
Linux to inflict the compat breakage), please keep the separate
tracepoints they are for distinctly different use cases. A memdev
protocol error is contained to that memdev, a port protocol error
implicates every CXL.cachemem descendant of that port.