From: sashiko-bot@kernel.org
To: "Hans Zhang" <18255117159@163.com>
Cc: linux-pci@vger.kernel.org, wsa+renesas@sang-engineering.com
Subject: Re: [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper
Date: Wed, 06 May 2026 20:18:35 +0000 [thread overview]
Message-ID: <20260506201836.68790C2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260506152346.166056-2-18255117159@163.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The header drivers/pci/pci.h fails to include <linux/delay.h> despite using msleep() in a static inline function.
--
commit 3b0eb6b945c6f31bfd19dfe4708d2d2cc57ab371
Author: Hans Zhang <18255117159@163.com>
PCI: Add pcie_wait_after_link_train() helper
This commit introduces a static inline helper pcie_wait_after_link_train()
to enforce a minimum 100 ms wait after Link training completes for downstream
ports supporting speeds greater than 5.0 GT/s. This allows multiple host
controller drivers to share the delay logic.
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 4a14f88e543a2..a8705a2a2d852 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -60,6 +60,19 @@ struct pcie_tlp_log;
> */
> #define PCIE_RESET_CONFIG_WAIT_MS 100
>
> +/**
> + * pcie_wait_after_link_train - Wait 100 ms if link speed > 5 GT/s
> + * @max_link_speed: the maximum link speed (2 = 5.0 GT/s, 3 = 8.0 GT/s, ...)
> + *
> + * Must be called after Link training completes and before the first
> + * Configuration Request is sent.
> + */
> +static inline void pcie_wait_after_link_train(int max_link_speed)
> +{
> + if (max_link_speed > 2)
> + msleep(PCIE_RESET_CONFIG_WAIT_MS);
Does this file need to include <linux/delay.h>?
The new helper uses msleep(), but drivers/pci/pci.h does not include
<linux/delay.h>. While this might not cause immediate build failures if
callers already include the header, it could cause implicit function
declaration errors for any future C files that include pci.h without
including <linux/delay.h> first.
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260506152346.166056-1-18255117159@163.com?part=1
next prev parent reply other threads:[~2026-05-06 20:18 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-06 15:23 [PATCH v2 0/8] PCI: Add common helper for 100 ms delay after link training Hans Zhang
2026-05-06 15:23 ` [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:34 ` Biju Das
2026-05-06 16:16 ` Hans Zhang
2026-05-06 15:55 ` Manivannan Sadhasivam
2026-05-06 16:13 ` Hans Zhang
2026-05-06 20:18 ` sashiko-bot [this message]
2026-05-06 15:23 ` [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training Hans Zhang
2026-05-06 15:31 ` Biju Das
2026-05-06 16:21 ` Hans Zhang
2026-05-06 16:27 ` Biju Das
2026-05-06 16:31 ` Hans Zhang
2026-05-06 16:03 ` Manivannan Sadhasivam
2026-05-06 16:14 ` Hans Zhang
2026-05-06 20:39 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 3/8] PCI: cadence: HPA: Add " Hans Zhang
2026-05-06 21:05 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up Hans Zhang
2026-05-06 16:04 ` Manivannan Sadhasivam
2026-05-06 16:11 ` Hans Zhang
2026-05-06 16:51 ` Manivannan Sadhasivam
2026-05-06 21:12 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 5/8] PCI: dwc: Use common pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:23 ` [PATCH v2 6/8] PCI: aardvark: Add 100 ms delay after link training Hans Zhang
2026-05-06 21:48 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 7/8] PCI: mediatek-gen3: " Hans Zhang
2026-05-06 22:14 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 8/8] PCI: rzg3s-host: " Hans Zhang
2026-05-06 16:52 ` Claudiu Beznea
2026-05-09 16:25 ` Hans Zhang
2026-05-06 22:28 ` sashiko-bot
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