Linux PCI subsystem development
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Hans Zhang" <18255117159@163.com>
Cc: linux-pci@vger.kernel.org, wsa+renesas@sang-engineering.com
Subject: Re: [PATCH v2 8/8] PCI: rzg3s-host: Add 100 ms delay after link training
Date: Wed, 06 May 2026 22:28:06 +0000	[thread overview]
Message-ID: <20260506222807.28525C2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260506152346.166056-9-18255117159@163.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The added link training delay is redundantly misplaced and silently fails to apply when the Device Tree property is absent.
--

commit 54b605149567b07684ca19210d899f1f515af48d
Author: Hans Zhang <18255117159@163.com>

PCI: rzg3s-host: Add 100 ms delay after link training

This commit attempts to enforce a 100 ms delay after link training completes
for speeds above 5.0 GT/s. It adds a call to pcie_wait_after_link_train()
at the end of rzg3s_pcie_host_init().

> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index d86e7516dcc29..6ab59c5464cfa 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -1390,6 +1390,8 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
>  	val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
>  	dev_info(host->dev, "PCIe link status [0x%x]\n", val);
>  
> +	pcie_wait_after_link_train(host->max_link_speed);

If the max-link-speed Device Tree property is omitted, host->max_link_speed
is populated with -EINVAL.

When -EINVAL is passed to pcie_wait_after_link_train(), the max_link_speed > 2
check evaluates to false. Will this cause the delay to be skipped entirely,
even if the actual link speed is above 5.0 GT/s?

Additionally, is this added delay redundant?

Looking at rzg3s_pcie_host_setup(), it already unconditionally sleeps for
100ms before returning:

drivers/pci/controller/pcie-rzg3s-host.c:rzg3s_pcie_host_setup() {
...
	ret = rzg3s_pcie_host_init(host);
	if (ret) {
...
	}

	ret = rzg3s_pcie_set_max_link_speed(host);
	if (ret)
		dev_info(dev, "Failed to set max link speed\n");

	msleep(PCIE_RESET_CONFIG_WAIT_MS);

	return 0;
}

Since rzg3s_pcie_set_max_link_speed() can trigger link retraining, should
the wait occur after that final link training completes rather than here
in rzg3s_pcie_host_init()?

> +
>  	return 0;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260506152346.166056-1-18255117159@163.com?part=8

      parent reply	other threads:[~2026-05-06 22:28 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-06 15:23 [PATCH v2 0/8] PCI: Add common helper for 100 ms delay after link training Hans Zhang
2026-05-06 15:23 ` [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:34   ` Biju Das
2026-05-06 16:16     ` Hans Zhang
2026-05-06 15:55   ` Manivannan Sadhasivam
2026-05-06 16:13     ` Hans Zhang
2026-05-06 20:18   ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training Hans Zhang
2026-05-06 15:31   ` Biju Das
2026-05-06 16:21     ` Hans Zhang
2026-05-06 16:27       ` Biju Das
2026-05-06 16:31         ` Hans Zhang
2026-05-06 16:03   ` Manivannan Sadhasivam
2026-05-06 16:14     ` Hans Zhang
2026-05-06 20:39   ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 3/8] PCI: cadence: HPA: Add " Hans Zhang
2026-05-06 21:05   ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up Hans Zhang
2026-05-06 16:04   ` Manivannan Sadhasivam
2026-05-06 16:11     ` Hans Zhang
2026-05-06 16:51       ` Manivannan Sadhasivam
2026-05-06 21:12   ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 5/8] PCI: dwc: Use common pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:23 ` [PATCH v2 6/8] PCI: aardvark: Add 100 ms delay after link training Hans Zhang
2026-05-06 21:48   ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 7/8] PCI: mediatek-gen3: " Hans Zhang
2026-05-06 22:14   ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 8/8] PCI: rzg3s-host: " Hans Zhang
2026-05-06 16:52   ` Claudiu Beznea
2026-05-09 16:25     ` Hans Zhang
2026-05-06 22:28   ` sashiko-bot [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260506222807.28525C2BCB0@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=18255117159@163.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=sashiko@lists.linux.dev \
    --cc=wsa+renesas@sang-engineering.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox