Re: [PATCH v2 7/8] PCI: mediatek-gen3: Add 100 ms delay after link training

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The patch fails to apply the required 100 ms delay when the 'max-link-speed' device tree property is absent, rendering the fix ineffective for default configurations.
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commit 10a23926b0b81ebd001326cf3638896f24f80c55
Author: Hans Zhang <18255117159@163.com>
PCI: mediatek-gen3: Add 100 ms delay after link training

This commit adds a 100 ms delay after link training completes for speeds
greater than 5.0 GT/s to comply with PCIe r6.0 sec 6.6.1. It uses the
pcie_wait_after_link_train() helper and passes the max_link_speed from
the controller structure.

> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index b0accd8285892..7c5f2ba7157bf 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -570,6 +570,8 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
>  		goto err_power_down_device;
>  	}
>  
> +	pcie_wait_after_link_train(pcie->max_link_speed);

Will this apply the delay when the max-link-speed device tree property is
absent?

If the property is not specified, pcie->max_link_speed remains 0, but the
hardware defaults to Gen3 (8.0 GT/s). Passing 0 to the helper skips the delay
because of the internal check:

drivers/pci/pci.h:pcie_wait_after_link_train() {
	if (max_link_speed > 2)
		msleep(PCIE_RESET_CONFIG_WAIT_MS);
}

Since the hardware defaults to Gen3 when unspecified, does the driver
need to check the actual negotiated link speed or the default hardware
capability here to ensure the delay is applied?

> +
>  	return 0;
>  
>  err_power_down_device:

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Sashiko AI review · https://sashiko.dev/#/patchset/20260506152346.166056-1-18255117159@163.com?part=7