Re: [PATCH] PCI: dwc: ep: Cache MSI outbound iATU mapping

[Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>]

On 12/10/2025 12:43 PM, Niklas Cassel wrote:
> From: Koichiro Den <den@valinux.co.jp>
>
> dw_pcie_ep_raise_msi_irq() currently programs an outbound iATU window
> for the MSI target address on every interrupt and tears it down again
> via dw_pcie_ep_unmap_addr().
>
> On systems that heavily use the AXI bridge interface (for example when
> the integrated eDMA engine is active), this means the outbound iATU
> registers are updated while traffic is in flight. The DesignWare
> endpoint databook 5.40a - "3.10.6.1 iATU Outbound Programming Overview"
> warns that updating iATU registers in this situation is not supported,
> and the behavior is undefined.
>
> Under high MSI and eDMA load this pattern results in occasional bogus
> outbound transactions and IOMMU faults, on the RC side, such as:
>
>    ipmmu-vmsa eed40000.iommu: Unhandled fault: status 0x00001502 iova 0xfe000000
>
> followed by the system becoming unresponsive. This is the actual output
> observed on Renesas R-Car S4, with its ipmmu_hc used with PCIe ch0.
>
> There is no need to reprogram the iATU region used for MSI on every
> interrupt. The host-provided MSI address is stable while MSI is enabled,
> and the endpoint driver already dedicates a scratch buffer for MSI
> generation.
>
> Cache the aligned MSI address and map size, program the outbound iATU
> once, and keep the window enabled. Subsequent interrupts only perform a
> write to the MSI scratch buffer, avoiding dynamic iATU reprogramming in
> the hot path and fixing the lockups seen under load.
>
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
> [cassel: do same change for dw_pcie_ep_raise_msix_irq()]
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
> Notes: Without this patch, I also see IOMMU errors on the host side,
> when running drivers/nvme/target/pci-epf.c with a large queue depth.
>
> pci_epc_raise_irq() does take a mutex, so the calls to these functions
> are serialized, so it really appears that the DWC controller does not
> handle iATU reprogramming while there are outstanding transactions.
>
> Just like Koichiro describes here:
> https://lore.kernel.org/linux-pci/ddriorsgyjs6klcb6d7pi2u3ah3wxlzku7v2dpyjlo6tmalvfw@yj5dczlkggt6/
>
> I also see the iova faulting on the RC side to be the start of "addr_space"
> on the EP, so it appears that a transaction has gone through untranslated.
> (Most likely because the DWC controller does handle the iATU table being
> modified while there are outstanding transactions.)
>
> This patch has been tested using pci-epf-test and nvmet-pci-epf on rock5b.
>
> pci-epf-test does change between MSI and MSI-X without calling
> dw_pcie_ep_stop(), however, the msg_addr address written by the host
> will be the same address, at least when using a Linux host using a DWC
> based controller. If another host ends up using different msg_addr for
> MSI and MSI-X, then I think that we will need to modify pci-epf-test to
> call a function when changing IRQ type, such that pcie-designware-ep.c
> can tear down the MSI/MSI-X mapping.
>
>   .../pci/controller/dwc/pcie-designware-ep.c   | 82 ++++++++++++++++---
>   drivers/pci/controller/dwc/pcie-designware.h  |  5 ++
>   2 files changed, 75 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7f2112c2fb21..2bbeddaa73d4 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -601,6 +601,16 @@ static void dw_pcie_ep_stop(struct pci_epc *epc)
>   	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>   	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>   
> +	/*
> +	 * Tear down the dedicated outbound window used for MSI
> +	 * generation. This avoids leaking an iATU window across
> +	 * endpoint stop/start cycles.
> +	 */
> +	if (ep->msi_iatu_mapped) {
> +		dw_pcie_ep_unmap_addr(epc, 0, 0, ep->msi_mem_phys);
> +		ep->msi_iatu_mapped = false;
> +	}
> +
>   	dw_pcie_stop_link(pci);
>   }
>   
> @@ -702,14 +712,37 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
>   	msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower;
>   
>   	msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &map_size, &offset);
> -	ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> -				  map_size);
> -	if (ret)
> -		return ret;
>   
> -	writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset);
> +	/*
> +	 * Program the outbound iATU once and keep it enabled.
> +	 *
> +	 * The spec warns that updating iATU registers while there are
> +	 * operations in flight on the AXI bridge interface is not
> +	 * supported, so we avoid reprogramming the region on every MSI,
> +	 * specifically unmapping immediately after writel().
> +	 */
> +	if (!ep->msi_iatu_mapped) {
> +		ret = dw_pcie_ep_map_addr(epc, func_no, 0,
> +					  ep->msi_mem_phys, msg_addr,
> +					  map_size);
> +		if (ret)
> +			return ret;
> +
> +		ep->msi_iatu_mapped = true;
> +		ep->msi_msg_addr = msg_addr;
> +		ep->msi_map_size = map_size;
> +	} else if (WARN_ON_ONCE(ep->msi_msg_addr != msg_addr ||
> +				ep->msi_map_size != map_size)) {
> +		/*
> +		 * The host changed the MSI target address or the required
> +		 * mapping size changed. Reprogramming the iATU at runtime is
> +		 * unsafe on this controller, so bail out instead of trying to
> +		 * update the existing region.
> +		 */
> +		return -EINVAL;
> +	}
>   
> -	dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
> +	writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset);
>   
>   	return 0;
>   }
> @@ -786,14 +819,36 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
>   	}
>   
>   	msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &map_size, &offset);
> -	ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> -				  map_size);
> -	if (ret)
> -		return ret;
>   
> -	writel(msg_data, ep->msi_mem + offset);
> +	/*
> +	 * Program the outbound iATU once and keep it enabled.
> +	 *
> +	 * The spec warns that updating iATU registers while there are
> +	 * operations in flight on the AXI bridge interface is not
> +	 * supported, so we avoid reprogramming the region on every MSI-X,
> +	 * specifically unmapping immediately after writel().
> +	 */
> +	if (!ep->msi_iatu_mapped) {
This is wrong, in MSIX each vector can give you different address, you 
can't expect same address for
all the vectors in MSIX table. In ARM based system you might see only 
single address for X86 this will
change.

And also we see in MSIX the address are getting updated at runtime with 
x86 windows host machines.

Use the MSIX doorbell method which will not use iATU at all, 
dw_pcie_ep_raise_msix_irq_doorbell().

- Krishna Chaitanya.
> +		ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> +					  map_size);
> +		if (ret)
> +			return ret;
> +
> +		ep->msi_iatu_mapped = true;
> +		ep->msi_msg_addr = msg_addr;
> +		ep->msi_map_size = map_size;
> +	} else if (WARN_ON_ONCE(ep->msi_msg_addr != msg_addr ||
> +				ep->msi_map_size != map_size)) {
> +		/*
> +		 * The host changed the MSI-X target address or the required
> +		 * mapping size changed. Reprogramming the iATU at runtime is
> +		 * unsafe on this controller, so bail out instead of trying to
> +		 * update the existing region.
> +		 */
> +		return -EINVAL;
> +	}
>   
> -	dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
> +	writel(msg_data, ep->msi_mem + offset);
>   
>   	return 0;
>   }
> @@ -1086,6 +1141,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>   	struct device *dev = pci->dev;
>   
>   	INIT_LIST_HEAD(&ep->func_list);
> +	ep->msi_iatu_mapped = false;
> +	ep->msi_msg_addr = 0;
> +	ep->msi_map_size = 0;
>   
>   	epc = devm_pci_epc_create(dev, &epc_ops);
>   	if (IS_ERR(epc)) {
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index a31bd93490dc..1093c622826d 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -472,6 +472,11 @@ struct dw_pcie_ep {
>   	void __iomem		*msi_mem;
>   	phys_addr_t		msi_mem_phys;
>   	struct pci_epf_bar	*epf_bar[PCI_STD_NUM_BARS];
> +
> +	/* MSI outbound iATU state */
> +	bool			msi_iatu_mapped;
> +	u64			msi_msg_addr;
> +	size_t			msi_map_size;
>   };
>   
>   struct dw_pcie_ops {