Re: [PATCH] PCI: dwc: ep: Cache MSI outbound iATU mapping

[Niklas Cassel <cassel@kernel.org>]

On Tue, Dec 23, 2025 at 02:23:39PM +0800, Shawn Lin wrote:
> > On 12/23/2025 6:42 AM, Shawn Lin wrote:
> > > I checked the IP configurtion parameters for RK3588 DM controller for
> > > sure, it sets MSIX_TABLE_EN=1.
> > > 
> > > Looking into dw_pcie_ep_raise_msix_irq_doorbell(), it doesn't seem to
> > > match the dwc databook. No matter for non-AXI mode or AXI access mode,
> > > shouldn't we need to generate a MSI-X table RAM with data/address/
> > > vector/TC in advanced? Am I missing anything because I didn't look
> > The MSI-X table will updated automatically when host updates the MSI-X
> > table, when MSI-X is enabled
> > by host.
> 
> Thanks for these details.
> I re-read the databook, especially "Figure 3-49 iMSIX-TX: MSIX
> Transmit ". Yes, it's updated automatically when host write access
> it, which either comes from RX or local DBI(for debug purpose).

Shawn,

if you have time to help figure out why we cannot simply
replace dw_pcie_ep_raise_msix_irq() with dw_pcie_ep_raise_msix_irq_doorbell()
in rockchip_pcie_raise_irq(), that would be appreciated.

As you can see, we get IOMMU errors on the host side if we
reprogram the outbound iATU while outgoing transactions are in flight.

Mani, perhaps we should even add a WARN_ON() in dw_pcie_ep_raise_msix_irq()
that warns users that this function is broken and will lead to transactions
to random writes on the host side memory, which is quite bad...


Kind regards,
Niklas