Re: [PATCH] PCI: dwc: ep: Cache MSI outbound iATU mapping

[Niklas Cassel <cassel@kernel.org>]

Hello all,

On Tue, Dec 23, 2025 at 02:23:39PM +0800, Shawn Lin wrote:
> > > I checked the IP configurtion parameters for RK3588 DM controller for
> > > sure, it sets MSIX_TABLE_EN=1.
> > > 
> > > Looking into dw_pcie_ep_raise_msix_irq_doorbell(), it doesn't seem to
> > > match the dwc databook. No matter for non-AXI mode or AXI access mode,
> > > shouldn't we need to generate a MSI-X table RAM with data/address/
> > > vector/TC in advanced? Am I missing anything because I didn't look
> > The MSI-X table will updated automatically when host updates the MSI-X
> > table, when MSI-X is enabled
> > by host.
> 
> Thanks for these details.
> I re-read the databook, especially "Figure 3-49 iMSIX-TX: MSIX
> Transmit ". Yes, it's updated automatically when host write access
> it, which either comes from RX or local DBI(for debug purpose).

With the help of Shawn, I managed to get dw_pcie_ep_raise_msix_irq_doorbell()
to work on RK3588.

By default, on RK3588, the MSI-X table is stored in BAR4 at offset 0x4000.

There seems to be a limitation that the iMSIX-TX doorbell feature only
works when the MSI-X table is stored in this default location.


As you know, by default, pci-epf-test stores the MSI-X table in BAR0,
after the registers defined by pci-epf-test itself.
This works fine when triggering a MSI-X using dw_pcie_ep_raise_msix_irq(),
but does not work when using dw_pcie_ep_raise_msix_irq_doorbell() (at least
not or RK3588).

Additionally, on RK3588, at offset 0x0 in BAR4, the eDMA registers are
mapped, so we cannot simply use BAR4 as test_reg_bar, as that would conflict
with the registers defined by pci-epf-test-itself.


The solution here is most likely to let EPC drivers define a
"HW limitation" of the MSI-X table (BAR number and offset), and create a new
API in the PCI endpoint framework that exposes this, and modify all EPF
drivers to use this API before calling pci_epc_set_msix().


Personally, I'm too busy to work on this right now.
For our use case with the NVMe PCI EPF, we can simply force it to only
use MSI (instead of MSI-X).

But... I could submit a WARN() in dw_pcie_ep_raise_msix_irq() that explains
that this function is broken, and that dw_pcie_ep_raise_msix_irq_doorbell()
should be used instead, on platforms that support it.

Or, if it is preferred, we could simply modify all DWC based drivers that is
not using dw_pcie_ep_raise_msix_irq_doorbell() (i.e. all except layerspace)
to simply not set "msix_capable = true" in epc_features, as we know that all
drivers that are using dw_pcie_ep_raise_msix_irq() are broken.

Thoughts?


Kind regards,
Niklas