[RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior

[RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Andrew Jones]

Users need a way determine that their harts conform to rva23u64 that
isn't error-prone. While patches 2 and 6 make it possible to determine,
it requires a bunch of probes and checks themselves (see patch9 for the
recipe). This RFC proposes adding an RVA23U64 hwprobe base behavior
(patch8) allowing easy determination. It also proposes adding the bases
to /proc/cpuinfo (patches 10 and 11) -- but those two patches are probably
even more RFCy than the hwprobe proposal...

The first three patches have been posted previously by their respective
authors and are currently under active review (except patch2 which
appears to have gotten lost in the shuffle). I've collected these
patches into the series since they're necessary for the base and
because I wanted to repost patch2 and patch3 with some changes. patch4
and patch6 expose more extensions to userspace. patch9 adds a consistency
test for the new hwprobe base behavior bit.

Thanks,
drew


Andrew Jones (8):
  riscv: Add B to hwcap
  riscv: hwprobe.rst: Replace tabs with spaces
  riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe
  riscv: Export have_user_pmlen* booleans
  riscv: hwprobe: Introduce rva23u64 base behavior
  riscv: selftests: hwprobe: Check rva23u64 consistency
  riscv: /proc/cpuinfo: Add rva23 bases to output
  riscv: /proc/cpuinfo: Also output rva20 and rva22 isa bases

Charlie Jenkins (1):
  riscv: Standardize extension capitilization

Jesse Taube (1):
  RISC-V: Add Zicclsm to cpufeature and hwprobe

Paul Walmsley (1):
  riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1

 Documentation/arch/riscv/hwprobe.rst          |  42 ++-
 arch/riscv/include/asm/cpufeature.h           |  14 +
 arch/riscv/include/asm/hwcap.h                |  23 +-
 arch/riscv/include/asm/hwprobe.h              |   3 +-
 arch/riscv/include/asm/switch_to.h            |   4 +-
 arch/riscv/include/uapi/asm/hwcap.h           |   1 +
 arch/riscv/include/uapi/asm/hwprobe.h         |   9 +-
 arch/riscv/kernel/cpu.c                       |  38 +++
 arch/riscv/kernel/cpufeature.c                | 168 ++++++++++--
 arch/riscv/kernel/process.c                   |  12 +-
 arch/riscv/kernel/sys_hwprobe.c               | 249 +++++++++++++-----
 arch/riscv/kvm/main.c                         |   2 +-
 arch/riscv/kvm/vcpu_fp.c                      |  28 +-
 arch/riscv/kvm/vcpu_onereg.c                  |  22 +-
 arch/riscv/kvm/vcpu_vector.c                  |  14 +-
 .../testing/selftests/riscv/hwprobe/hwprobe.c | 112 +++++++-
 .../selftests/riscv/hwprobe/which-cpus.c      |  20 +-
 17 files changed, 610 insertions(+), 151 deletions(-)

-- 
2.43.0


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[RFC PATCH v1 01/11] riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1

[Andrew Jones]

From: Paul Walmsley <pjw@kernel.org>

We've run out of bits to describe RISC-V ISA extensions in our initial
hwprobe key, RISCV_HWPROBE_KEY_IMA_EXT_0.  So, let's add
RISCV_HWPROBE_KEY_IMA_EXT_1, along with the framework to set the
appropriate hwprobe tuple, and add testing for it.

Signed-off-by: Paul Walmsley <pjw@kernel.org>
Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 Documentation/arch/riscv/hwprobe.rst          |   4 +
 arch/riscv/include/asm/hwprobe.h              |   3 +-
 arch/riscv/include/uapi/asm/hwprobe.h         |   1 +
 arch/riscv/kernel/sys_hwprobe.c               | 169 +++++++++++-------
 .../selftests/riscv/hwprobe/which-cpus.c      |  18 +-
 5 files changed, 120 insertions(+), 75 deletions(-)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 641ec4abb906..03484a2546da 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -387,3 +387,7 @@ The following keys are defined:
 
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicbop block in bytes.
+
+* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
+  extensions that are compatible with the
+  :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 8c572a464719..8b9f5e1cf4cb 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
 
 #include <uapi/asm/hwprobe.h>
 
-#define RISCV_HWPROBE_MAX_KEY 15
+#define RISCV_HWPROBE_MAX_KEY		16
 
 static inline bool riscv_hwprobe_key_is_valid(__s64 key)
 {
@@ -20,6 +20,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key)
 	switch (key) {
 	case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
 	case RISCV_HWPROBE_KEY_IMA_EXT_0:
+	case RISCV_HWPROBE_KEY_IMA_EXT_1:
 	case RISCV_HWPROBE_KEY_CPUPERF_0:
 	case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
 	case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index cd3c126730c3..ed2621a5a47d 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -113,6 +113,7 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0	13
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14
 #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE	15
+#define RISCV_HWPROBE_KEY_IMA_EXT_1		16
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index e6787ba7f2fc..53731ace7984 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -24,6 +24,14 @@
 #include <vdso/vsyscall.h>
 
 
+#define EXT_KEY(isa_arg, ext, pv, missing)					\
+	do {										\
+		if (__riscv_isa_extension_available(isa_arg, RISCV_ISA_EXT_##ext))	\
+			pv |= RISCV_HWPROBE_EXT_##ext;				\
+		else									\
+			missing |= RISCV_HWPROBE_EXT_##ext;				\
+	} while (false)
+
 static void hwprobe_arch_id(struct riscv_hwprobe *pair,
 			    const struct cpumask *cpus)
 {
@@ -93,90 +101,109 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	for_each_cpu(cpu, cpus) {
 		struct riscv_isainfo *isainfo = &hart_isa[cpu];
 
-#define EXT_KEY(ext)									\
-	do {										\
-		if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext))	\
-			pair->value |= RISCV_HWPROBE_EXT_##ext;				\
-		else									\
-			missing |= RISCV_HWPROBE_EXT_##ext;				\
-	} while (false)
-
 		/*
 		 * Only use EXT_KEY() for extensions which can be exposed to userspace,
 		 * regardless of the kernel's configuration, as no other checks, besides
 		 * presence in the hart_isa bitmap, are made.
 		 */
-		EXT_KEY(ZAAMO);
-		EXT_KEY(ZABHA);
-		EXT_KEY(ZACAS);
-		EXT_KEY(ZALASR);
-		EXT_KEY(ZALRSC);
-		EXT_KEY(ZAWRS);
-		EXT_KEY(ZBA);
-		EXT_KEY(ZBB);
-		EXT_KEY(ZBC);
-		EXT_KEY(ZBKB);
-		EXT_KEY(ZBKC);
-		EXT_KEY(ZBKX);
-		EXT_KEY(ZBS);
-		EXT_KEY(ZCA);
-		EXT_KEY(ZCB);
-		EXT_KEY(ZCLSD);
-		EXT_KEY(ZCMOP);
-		EXT_KEY(ZICBOM);
-		EXT_KEY(ZICBOP);
-		EXT_KEY(ZICBOZ);
-		EXT_KEY(ZICNTR);
-		EXT_KEY(ZICOND);
-		EXT_KEY(ZIHINTNTL);
-		EXT_KEY(ZIHINTPAUSE);
-		EXT_KEY(ZIHPM);
-		EXT_KEY(ZILSD);
-		EXT_KEY(ZIMOP);
-		EXT_KEY(ZKND);
-		EXT_KEY(ZKNE);
-		EXT_KEY(ZKNH);
-		EXT_KEY(ZKSED);
-		EXT_KEY(ZKSH);
-		EXT_KEY(ZKT);
-		EXT_KEY(ZTSO);
+		EXT_KEY(isainfo->isa, ZAAMO, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZABHA, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZACAS, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZALASR, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZALRSC, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZAWRS, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZBA, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZBB, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZBC, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZBKB, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZBKC, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZBKX, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZBS, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZCA, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZCB, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZCLSD, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZCMOP, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICBOM, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICBOP, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICBOZ, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICNTR, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICOND, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZIHINTNTL, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZIHINTPAUSE, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZIHPM, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZILSD, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZIMOP, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZKND, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZKNE, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZKNH, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZKSED, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZKSH, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZKT, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZTSO, pair->value, missing);
 
 		/*
 		 * All the following extensions must depend on the kernel
 		 * support of V.
 		 */
 		if (has_vector()) {
-			EXT_KEY(ZVBB);
-			EXT_KEY(ZVBC);
-			EXT_KEY(ZVE32F);
-			EXT_KEY(ZVE32X);
-			EXT_KEY(ZVE64D);
-			EXT_KEY(ZVE64F);
-			EXT_KEY(ZVE64X);
-			EXT_KEY(ZVFBFMIN);
-			EXT_KEY(ZVFBFWMA);
-			EXT_KEY(ZVFH);
-			EXT_KEY(ZVFHMIN);
-			EXT_KEY(ZVKB);
-			EXT_KEY(ZVKG);
-			EXT_KEY(ZVKNED);
-			EXT_KEY(ZVKNHA);
-			EXT_KEY(ZVKNHB);
-			EXT_KEY(ZVKSED);
-			EXT_KEY(ZVKSH);
-			EXT_KEY(ZVKT);
+			EXT_KEY(isainfo->isa, ZVBB, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVBC, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVE32X, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVE64X, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVKB, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVKG, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVKNED, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVKNHA, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVKNHB, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVKSED, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVKSH, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZVKT, pair->value, missing);
 		}
 
-		EXT_KEY(ZCD);
-		EXT_KEY(ZCF);
-		EXT_KEY(ZFA);
-		EXT_KEY(ZFBFMIN);
-		EXT_KEY(ZFH);
-		EXT_KEY(ZFHMIN);
+		EXT_KEY(isainfo->isa, ZCD, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZCF, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZFA, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZFBFMIN, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZFH, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZFHMIN, pair->value, missing);
 
 		if (IS_ENABLED(CONFIG_RISCV_ISA_SUPM))
-			EXT_KEY(SUPM);
-#undef EXT_KEY
+			EXT_KEY(isainfo->isa, SUPM, pair->value, missing);
+	}
+
+	/* Now turn off reporting features if any CPU is missing it. */
+	pair->value &= ~missing;
+}
+
+static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
+			     const struct cpumask *cpus)
+{
+	int cpu;
+	u64 missing = 0;
+
+	pair->value = 0;
+
+	/*
+	 * Loop through and record extensions that 1) anyone has, and 2) anyone
+	 * doesn't have.
+	 */
+	for_each_cpu(cpu, cpus) {
+		/* struct riscv_isainfo *isainfo = &hart_isa[cpu]; */
+
+		/*
+		 * Only use EXT_KEY() for extensions which can be
+		 * exposed to userspace, regardless of the kernel's
+		 * configuration, as no other checks, besides presence
+		 * in the hart_isa bitmap, are made.
+		 */
+		/* Nothing here yet */
 	}
 
 	/* Now turn off reporting features if any CPU is missing it. */
@@ -287,6 +314,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
 		hwprobe_isa_ext0(pair, cpus);
 		break;
 
+	case RISCV_HWPROBE_KEY_IMA_EXT_1:
+		hwprobe_isa_ext1(pair, cpus);
+		break;
+
 	case RISCV_HWPROBE_KEY_CPUPERF_0:
 	case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF:
 		pair->value = hwprobe_misaligned(cpus);
diff --git a/tools/testing/selftests/riscv/hwprobe/which-cpus.c b/tools/testing/selftests/riscv/hwprobe/which-cpus.c
index 3ab53067e8dd..587feb198c04 100644
--- a/tools/testing/selftests/riscv/hwprobe/which-cpus.c
+++ b/tools/testing/selftests/riscv/hwprobe/which-cpus.c
@@ -83,9 +83,9 @@ static void do_which_cpus(int argc, char **argv, cpu_set_t *cpus)
 
 int main(int argc, char **argv)
 {
-	struct riscv_hwprobe pairs[2];
+	struct riscv_hwprobe pairs[3];
 	cpu_set_t cpus_aff, cpus;
-	__u64 ext0_all;
+	__u64 ext0_all, ext1_all;
 	long rc;
 
 	rc = sched_getaffinity(0, sizeof(cpu_set_t), &cpus_aff);
@@ -112,6 +112,11 @@ int main(int argc, char **argv)
 	assert(rc == 0 && pairs[0].key == RISCV_HWPROBE_KEY_IMA_EXT_0);
 	ext0_all = pairs[0].value;
 
+	pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_1, };
+	rc = riscv_hwprobe(pairs, 1, 0, NULL, 0);
+	assert(rc == 0 && pairs[0].key == RISCV_HWPROBE_KEY_IMA_EXT_1);
+	ext1_all = pairs[0].value;
+
 	pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR, .value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA, };
 	CPU_ZERO(&cpus);
 	rc = riscv_hwprobe(pairs, 1, 0, (unsigned long *)&cpus, RISCV_HWPROBE_WHICH_CPUS);
@@ -134,20 +139,23 @@ int main(int argc, char **argv)
 
 	pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR, .value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA, };
 	pairs[1] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_0, .value = ext0_all, };
+	pairs[2] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_1, .value = ext1_all, };
 	CPU_ZERO(&cpus);
-	rc = riscv_hwprobe(pairs, 2, sizeof(cpu_set_t), (unsigned long *)&cpus, RISCV_HWPROBE_WHICH_CPUS);
+	rc = riscv_hwprobe(pairs, 3, sizeof(cpu_set_t), (unsigned long *)&cpus, RISCV_HWPROBE_WHICH_CPUS);
 	ksft_test_result(rc == 0 && CPU_COUNT(&cpus) == sysconf(_SC_NPROCESSORS_ONLN), "set all cpus\n");
 
 	pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR, .value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA, };
 	pairs[1] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_0, .value = ext0_all, };
+	pairs[2] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_1, .value = ext1_all, };
 	memcpy(&cpus, &cpus_aff, sizeof(cpu_set_t));
-	rc = riscv_hwprobe(pairs, 2, sizeof(cpu_set_t), (unsigned long *)&cpus, RISCV_HWPROBE_WHICH_CPUS);
+	rc = riscv_hwprobe(pairs, 3, sizeof(cpu_set_t), (unsigned long *)&cpus, RISCV_HWPROBE_WHICH_CPUS);
 	ksft_test_result(rc == 0 && CPU_EQUAL(&cpus, &cpus_aff), "set all affinity cpus\n");
 
 	pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR, .value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA, };
 	pairs[1] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_0, .value = ~ext0_all, };
+	pairs[2] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_1, .value = ~ext1_all, };
 	memcpy(&cpus, &cpus_aff, sizeof(cpu_set_t));
-	rc = riscv_hwprobe(pairs, 2, sizeof(cpu_set_t), (unsigned long *)&cpus, RISCV_HWPROBE_WHICH_CPUS);
+	rc = riscv_hwprobe(pairs, 3, sizeof(cpu_set_t), (unsigned long *)&cpus, RISCV_HWPROBE_WHICH_CPUS);
 	ksft_test_result(rc == 0 && CPU_COUNT(&cpus) == 0, "clear all cpus\n");
 
 	ksft_finished();
-- 
2.43.0


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[RFC PATCH v1 02/11] RISC-V: Add Zicclsm to cpufeature and hwprobe

[Andrew Jones]

From: Jesse Taube <jesse@rivosinc.com>

Zicclsm requires misaligned support for all regular load and store
instructions, both scalar and vector, but not AMOs or other
specialized forms of memory access, to main memory regions with both
the cacheability and coherence PMAs, as defined in the profiles spec.
Even though mandated, misaligned loads and stores might execute
extremely slowly. Standard software distributions should assume their
existence only for correctness, not for performance.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
[Rebased, rewrote doc text, minor commit message revisions]
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 4 ++++
 arch/riscv/include/asm/hwcap.h        | 1 +
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/cpufeature.c        | 1 +
 arch/riscv/kernel/sys_hwprobe.c       | 1 +
 5 files changed, 8 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 03484a2546da..0598c9ddd73f 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -289,6 +289,10 @@ The following keys are defined:
        defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
        load/store pair for RV32 with the main manual") of the riscv-isa-manual.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported,
+       as defined in the RISC-V Profiles specification starting from commit
+       b1d80660 ("Updated to ratified state.")
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
      :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
      mistakenly classified as a bitmask rather than a value.
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4369a2338541..496694d3e182 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -110,6 +110,7 @@
 #define RISCV_ISA_EXT_ZALASR		101
 #define RISCV_ISA_EXT_ZILSD		102
 #define RISCV_ISA_EXT_ZCLSD		103
+#define RISCV_ISA_EXT_ZICCLSM		104
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index ed2621a5a47d..6a0163b54718 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -86,6 +86,7 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZICBOP	(1ULL << 60)
 #define		RISCV_HWPROBE_EXT_ZILSD		(1ULL << 61)
 #define		RISCV_HWPROBE_EXT_ZCLSD		(1ULL << 62)
+#define		RISCV_HWPROBE_EXT_ZICCLSM	(1ULL << 63)
 
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fa591aff9d33..cf27b7a2547f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -481,6 +481,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
+	__RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM),
 	__RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
 	__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
 	__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 53731ace7984..1423b447fe9a 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -126,6 +126,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(isainfo->isa, ZICBOM, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICBOP, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICBOZ, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICNTR, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICOND, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZIHINTNTL, pair->value, missing);
-- 
2.43.0


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[RFC PATCH v1 03/11] riscv: Standardize extension capitilization

[Andrew Jones]

From: Charlie Jenkins <charlie@rivosinc.com>

The base extensions are often lowercase and were written as lowercase in
hwcap, but other references to these extensions in the kernel are
uppercase. Standardize the case to make it easier to handle macro
expansion.

Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
[Apply KVM_ISA_EXT_ARR(), fixup all KVM use.]
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 arch/riscv/include/asm/hwcap.h     | 18 ++++++++---------
 arch/riscv/include/asm/switch_to.h |  4 ++--
 arch/riscv/kernel/cpufeature.c     | 32 +++++++++++++++---------------
 arch/riscv/kernel/sys_hwprobe.c    |  4 ++--
 arch/riscv/kvm/main.c              |  2 +-
 arch/riscv/kvm/vcpu_fp.c           | 28 +++++++++++++-------------
 arch/riscv/kvm/vcpu_onereg.c       | 22 ++++++++++----------
 arch/riscv/kvm/vcpu_vector.c       | 14 ++++++-------
 8 files changed, 62 insertions(+), 62 deletions(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 496694d3e182..03acd22bbbaa 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -10,15 +10,15 @@
 
 #include <uapi/asm/hwcap.h>
 
-#define RISCV_ISA_EXT_a		('a' - 'a')
-#define RISCV_ISA_EXT_c		('c' - 'a')
-#define RISCV_ISA_EXT_d		('d' - 'a')
-#define RISCV_ISA_EXT_f		('f' - 'a')
-#define RISCV_ISA_EXT_h		('h' - 'a')
-#define RISCV_ISA_EXT_i		('i' - 'a')
-#define RISCV_ISA_EXT_m		('m' - 'a')
-#define RISCV_ISA_EXT_q		('q' - 'a')
-#define RISCV_ISA_EXT_v		('v' - 'a')
+#define RISCV_ISA_EXT_A		('a' - 'a')
+#define RISCV_ISA_EXT_C		('c' - 'a')
+#define RISCV_ISA_EXT_D		('d' - 'a')
+#define RISCV_ISA_EXT_F		('f' - 'a')
+#define RISCV_ISA_EXT_H		('h' - 'a')
+#define RISCV_ISA_EXT_I		('i' - 'a')
+#define RISCV_ISA_EXT_M		('m' - 'a')
+#define RISCV_ISA_EXT_Q		('q' - 'a')
+#define RISCV_ISA_EXT_V		('v' - 'a')
 
 /*
  * These macros represent the logical IDs of each multi-letter RISC-V ISA
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 0e71eb82f920..ff35a4d04f85 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -60,8 +60,8 @@ static inline void __switch_to_fpu(struct task_struct *prev,
 
 static __always_inline bool has_fpu(void)
 {
-	return riscv_has_extension_likely(RISCV_ISA_EXT_f) ||
-		riscv_has_extension_likely(RISCV_ISA_EXT_d);
+	return riscv_has_extension_likely(RISCV_ISA_EXT_F) ||
+		riscv_has_extension_likely(RISCV_ISA_EXT_D);
 }
 #else
 static __always_inline bool has_fpu(void) { return false; }
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index cf27b7a2547f..25ed1d6958d7 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -83,7 +83,7 @@ EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
 static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data,
 			       const unsigned long *isa_bitmap)
 {
-	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
+	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_F))
 		return 0;
 
 	return -EPROBE_DEFER;
@@ -145,7 +145,7 @@ static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data,
 	 * Due to extension ordering, d is checked before f, so no deferral
 	 * is required.
 	 */
-	if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) {
+	if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D)) {
 		pr_warn_once("This kernel does not support systems with F but not D\n");
 		return -EINVAL;
 	}
@@ -188,7 +188,7 @@ static int riscv_ext_vector_float_validate(const struct riscv_isa_ext_data *data
 	 * Since this function validates vector only, and v/Zve* are probed
 	 * after f/d, there's no need for a deferral here.
 	 */
-	if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
+	if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D))
 		return -EINVAL;
 
 	return 0;
@@ -223,7 +223,7 @@ static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data,
 				  const unsigned long *isa_bitmap)
 {
 	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
-	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
+	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D))
 		return 0;
 
 	return -EPROBE_DEFER;
@@ -236,7 +236,7 @@ static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
 		return -EINVAL;
 
 	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
-	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
+	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_F))
 		return 0;
 
 	return -EPROBE_DEFER;
@@ -469,15 +469,15 @@ static const unsigned int riscv_c_exts[] = {
  * New entries to this struct should follow the ordering rules described above.
  */
 const struct riscv_isa_ext_data riscv_isa_ext[] = {
-	__RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
-	__RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
-	__RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_a, riscv_a_exts),
-	__RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate),
-	__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate),
-	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
-	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
-	__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
-	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
+	__RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_I),
+	__RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_M),
+	__RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_A, riscv_a_exts),
+	__RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_F, riscv_ext_f_validate),
+	__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_D, riscv_ext_d_validate),
+	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q),
+	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts),
+	__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts, riscv_ext_vector_float_validate),
+	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
@@ -873,8 +873,8 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
 		 * marchid.
 		 */
 		if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) {
-			this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
-			clear_bit(RISCV_ISA_EXT_v, source_isa);
+			this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_V];
+			clear_bit(RISCV_ISA_EXT_V, source_isa);
 		}
 
 		riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 1423b447fe9a..76e673ab42a5 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -88,10 +88,10 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	if (has_fpu())
 		pair->value |= RISCV_HWPROBE_IMA_FD;
 
-	if (riscv_isa_extension_available(NULL, c))
+	if (riscv_isa_extension_available(NULL, C))
 		pair->value |= RISCV_HWPROBE_IMA_C;
 
-	if (has_vector() && riscv_isa_extension_available(NULL, v))
+	if (has_vector() && riscv_isa_extension_available(NULL, V))
 		pair->value |= RISCV_HWPROBE_IMA_V;
 
 	/*
diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
index 45536af521f0..4d8c6e04aa7e 100644
--- a/arch/riscv/kvm/main.c
+++ b/arch/riscv/kvm/main.c
@@ -85,7 +85,7 @@ static int __init riscv_kvm_init(void)
 	char slist[64];
 	const char *str;
 
-	if (!riscv_isa_extension_available(NULL, h)) {
+	if (!riscv_isa_extension_available(NULL, H)) {
 		kvm_info("hypervisor extension not available\n");
 		return -ENODEV;
 	}
diff --git a/arch/riscv/kvm/vcpu_fp.c b/arch/riscv/kvm/vcpu_fp.c
index 030904d82b58..5cb6b04f6f96 100644
--- a/arch/riscv/kvm/vcpu_fp.c
+++ b/arch/riscv/kvm/vcpu_fp.c
@@ -19,8 +19,8 @@ void kvm_riscv_vcpu_fp_reset(struct kvm_vcpu *vcpu)
 	struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
 
 	cntx->sstatus &= ~SR_FS;
-	if (riscv_isa_extension_available(vcpu->arch.isa, f) ||
-	    riscv_isa_extension_available(vcpu->arch.isa, d))
+	if (riscv_isa_extension_available(vcpu->arch.isa, F) ||
+	    riscv_isa_extension_available(vcpu->arch.isa, D))
 		cntx->sstatus |= SR_FS_INITIAL;
 	else
 		cntx->sstatus |= SR_FS_OFF;
@@ -36,9 +36,9 @@ void kvm_riscv_vcpu_guest_fp_save(struct kvm_cpu_context *cntx,
 				  const unsigned long *isa)
 {
 	if ((cntx->sstatus & SR_FS) == SR_FS_DIRTY) {
-		if (riscv_isa_extension_available(isa, d))
+		if (riscv_isa_extension_available(isa, D))
 			__kvm_riscv_fp_d_save(cntx);
-		else if (riscv_isa_extension_available(isa, f))
+		else if (riscv_isa_extension_available(isa, F))
 			__kvm_riscv_fp_f_save(cntx);
 		kvm_riscv_vcpu_fp_clean(cntx);
 	}
@@ -48,9 +48,9 @@ void kvm_riscv_vcpu_guest_fp_restore(struct kvm_cpu_context *cntx,
 				     const unsigned long *isa)
 {
 	if ((cntx->sstatus & SR_FS) != SR_FS_OFF) {
-		if (riscv_isa_extension_available(isa, d))
+		if (riscv_isa_extension_available(isa, D))
 			__kvm_riscv_fp_d_restore(cntx);
-		else if (riscv_isa_extension_available(isa, f))
+		else if (riscv_isa_extension_available(isa, F))
 			__kvm_riscv_fp_f_restore(cntx);
 		kvm_riscv_vcpu_fp_clean(cntx);
 	}
@@ -59,17 +59,17 @@ void kvm_riscv_vcpu_guest_fp_restore(struct kvm_cpu_context *cntx,
 void kvm_riscv_vcpu_host_fp_save(struct kvm_cpu_context *cntx)
 {
 	/* No need to check host sstatus as it can be modified outside */
-	if (riscv_isa_extension_available(NULL, d))
+	if (riscv_isa_extension_available(NULL, D))
 		__kvm_riscv_fp_d_save(cntx);
-	else if (riscv_isa_extension_available(NULL, f))
+	else if (riscv_isa_extension_available(NULL, F))
 		__kvm_riscv_fp_f_save(cntx);
 }
 
 void kvm_riscv_vcpu_host_fp_restore(struct kvm_cpu_context *cntx)
 {
-	if (riscv_isa_extension_available(NULL, d))
+	if (riscv_isa_extension_available(NULL, D))
 		__kvm_riscv_fp_d_restore(cntx);
-	else if (riscv_isa_extension_available(NULL, f))
+	else if (riscv_isa_extension_available(NULL, F))
 		__kvm_riscv_fp_f_restore(cntx);
 }
 #endif
@@ -87,7 +87,7 @@ int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu,
 	void *reg_val;
 
 	if ((rtype == KVM_REG_RISCV_FP_F) &&
-	    riscv_isa_extension_available(vcpu->arch.isa, f)) {
+	    riscv_isa_extension_available(vcpu->arch.isa, F)) {
 		if (KVM_REG_SIZE(reg->id) != sizeof(u32))
 			return -EINVAL;
 		if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr))
@@ -98,7 +98,7 @@ int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu,
 		else
 			return -ENOENT;
 	} else if ((rtype == KVM_REG_RISCV_FP_D) &&
-		   riscv_isa_extension_available(vcpu->arch.isa, d)) {
+		   riscv_isa_extension_available(vcpu->arch.isa, D)) {
 		if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) {
 			if (KVM_REG_SIZE(reg->id) != sizeof(u32))
 				return -EINVAL;
@@ -132,7 +132,7 @@ int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu,
 	void *reg_val;
 
 	if ((rtype == KVM_REG_RISCV_FP_F) &&
-	    riscv_isa_extension_available(vcpu->arch.isa, f)) {
+	    riscv_isa_extension_available(vcpu->arch.isa, F)) {
 		if (KVM_REG_SIZE(reg->id) != sizeof(u32))
 			return -EINVAL;
 		if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr))
@@ -143,7 +143,7 @@ int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu,
 		else
 			return -ENOENT;
 	} else if ((rtype == KVM_REG_RISCV_FP_D) &&
-		   riscv_isa_extension_available(vcpu->arch.isa, d)) {
+		   riscv_isa_extension_available(vcpu->arch.isa, D)) {
 		if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) {
 			if (KVM_REG_SIZE(reg->id) != sizeof(u32))
 				return -EINVAL;
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 865dae903aa0..901dca0edcb9 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -26,14 +26,14 @@
 /* Mapping between KVM ISA Extension ID & guest ISA extension ID */
 static const unsigned long kvm_isa_ext_arr[] = {
 	/* Single letter extensions (alphabetically sorted) */
-	[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,
-	[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,
-	[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
-	[KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_f,
-	[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
-	[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
-	[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
-	[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
+	KVM_ISA_EXT_ARR(A),
+	KVM_ISA_EXT_ARR(C),
+	KVM_ISA_EXT_ARR(D),
+	KVM_ISA_EXT_ARR(F),
+	KVM_ISA_EXT_ARR(H),
+	KVM_ISA_EXT_ARR(I),
+	KVM_ISA_EXT_ARR(M),
+	KVM_ISA_EXT_ARR(V),
 	/* Multi letter extensions (alphabetically sorted) */
 	KVM_ISA_EXT_ARR(SMNPM),
 	KVM_ISA_EXT_ARR(SMSTATEEN),
@@ -986,7 +986,7 @@ static inline unsigned long num_fp_f_regs(const struct kvm_vcpu *vcpu)
 {
 	const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
 
-	if (riscv_isa_extension_available(vcpu->arch.isa, f))
+	if (riscv_isa_extension_available(vcpu->arch.isa, F))
 		return sizeof(cntx->fp.f) / sizeof(u32);
 	else
 		return 0;
@@ -1015,7 +1015,7 @@ static inline unsigned long num_fp_d_regs(const struct kvm_vcpu *vcpu)
 {
 	const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
 
-	if (riscv_isa_extension_available(vcpu->arch.isa, d))
+	if (riscv_isa_extension_available(vcpu->arch.isa, D))
 		return sizeof(cntx->fp.d.f) / sizeof(u64) + 1;
 	else
 		return 0;
@@ -1094,7 +1094,7 @@ static inline unsigned long num_sbi_regs(struct kvm_vcpu *vcpu)
 
 static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu)
 {
-	if (!riscv_isa_extension_available(vcpu->arch.isa, v))
+	if (!riscv_isa_extension_available(vcpu->arch.isa, V))
 		return 0;
 
 	/* vstart, vl, vtype, vcsr, vlenb and 32 vector regs */
diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c
index 05f3cc2d8e31..8bc85593e1d4 100644
--- a/arch/riscv/kvm/vcpu_vector.c
+++ b/arch/riscv/kvm/vcpu_vector.c
@@ -25,7 +25,7 @@ void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu)
 
 	cntx->vector.vlenb = riscv_v_vsize / 32;
 
-	if (riscv_isa_extension_available(isa, v)) {
+	if (riscv_isa_extension_available(isa, V)) {
 		cntx->sstatus |= SR_VS_INITIAL;
 		WARN_ON(!cntx->vector.datap);
 		memset(cntx->vector.datap, 0, riscv_v_vsize);
@@ -44,7 +44,7 @@ void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx,
 				      unsigned long *isa)
 {
 	if ((cntx->sstatus & SR_VS) == SR_VS_DIRTY) {
-		if (riscv_isa_extension_available(isa, v))
+		if (riscv_isa_extension_available(isa, V))
 			__kvm_riscv_vector_save(cntx);
 		kvm_riscv_vcpu_vector_clean(cntx);
 	}
@@ -54,7 +54,7 @@ void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx,
 					 unsigned long *isa)
 {
 	if ((cntx->sstatus & SR_VS) != SR_VS_OFF) {
-		if (riscv_isa_extension_available(isa, v))
+		if (riscv_isa_extension_available(isa, V))
 			__kvm_riscv_vector_restore(cntx);
 		kvm_riscv_vcpu_vector_clean(cntx);
 	}
@@ -63,13 +63,13 @@ void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx,
 void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx)
 {
 	/* No need to check host sstatus as it can be modified outside */
-	if (riscv_isa_extension_available(NULL, v))
+	if (riscv_isa_extension_available(NULL, V))
 		__kvm_riscv_vector_save(cntx);
 }
 
 void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx)
 {
-	if (riscv_isa_extension_available(NULL, v))
+	if (riscv_isa_extension_available(NULL, V))
 		__kvm_riscv_vector_restore(cntx);
 }
 
@@ -149,7 +149,7 @@ int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu,
 	void *reg_addr;
 	int rc;
 
-	if (!riscv_isa_extension_available(isa, v))
+	if (!riscv_isa_extension_available(isa, V))
 		return -ENOENT;
 
 	rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr);
@@ -175,7 +175,7 @@ int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu,
 	void *reg_addr;
 	int rc;
 
-	if (!riscv_isa_extension_available(isa, v))
+	if (!riscv_isa_extension_available(isa, V))
 		return -ENOENT;
 
 	if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) {
-- 
2.43.0


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[RFC PATCH v1 04/11] riscv: Add B to hwcap

[Andrew Jones]

Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs
are all set.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 arch/riscv/include/asm/hwcap.h      | 1 +
 arch/riscv/include/uapi/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c      | 8 ++++++++
 3 files changed, 10 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 03acd22bbbaa..c17e11caca83 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -11,6 +11,7 @@
 #include <uapi/asm/hwcap.h>
 
 #define RISCV_ISA_EXT_A		('a' - 'a')
+#define RISCV_ISA_EXT_B		('b' - 'a')
 #define RISCV_ISA_EXT_C		('c' - 'a')
 #define RISCV_ISA_EXT_D		('d' - 'a')
 #define RISCV_ISA_EXT_F		('f' - 'a')
diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index c52bb7bbbabe..96b7cf854e09 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,6 +21,7 @@
 #define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))
 #define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))
 #define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_B	(1 << ('B' - 'A'))
 #define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))
 
 #endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 25ed1d6958d7..ca7a34f66738 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -429,6 +429,12 @@ static const unsigned int riscv_c_exts[] = {
 	RISCV_ISA_EXT_ZCD,
 };
 
+static const unsigned int riscv_b_exts[] = {
+	RISCV_ISA_EXT_ZBA,
+	RISCV_ISA_EXT_ZBB,
+	RISCV_ISA_EXT_ZBS,
+};
+
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
  * chapter 27 of the unprivileged specification.
@@ -476,6 +482,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_D, riscv_ext_d_validate),
 	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q),
 	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts),
+	__RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts, riscv_ext_vector_float_validate),
 	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
@@ -1089,6 +1096,7 @@ void __init riscv_fill_hwcap(void)
 	isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
 	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
 	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
+	isa2hwcap['b' - 'a'] = COMPAT_HWCAP_ISA_B;
 	isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
 
 	if (!acpi_disabled) {
-- 
2.43.0


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[RFC PATCH v1 05/11] riscv: hwprobe.rst: Replace tabs with spaces

[Andrew Jones]

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 Documentation/arch/riscv/hwprobe.rst | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 0598c9ddd73f..4484f2a7f798 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -362,7 +362,7 @@ The following keys are defined:
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor
         extension is supported in the T-Head ISA extensions spec starting from
-	commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
+        commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
 
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicbom block in bytes.
@@ -375,19 +375,19 @@ The following keys are defined:
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
         extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
-	Extensions Specification.
+        Extensions Specification.
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
         extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
-	Instruction Extensions Specification.
+        Instruction Extensions Specification.
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
         vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
-	Clip Instructions Extensions Specification.
+        Clip Instructions Extensions Specification.
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
         vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
-	Instruction Extensions Specification.
+        Instruction Extensions Specification.
 
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicbop block in bytes.
-- 
2.43.0


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[RFC PATCH v1 06/11] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe

[Andrew Jones]

Ziccrse is already present in cpufeature.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 16 ++++++++++++++++
 arch/riscv/include/asm/hwcap.h        |  3 +++
 arch/riscv/include/uapi/asm/hwprobe.h |  4 ++++
 arch/riscv/kernel/cpufeature.c        |  3 +++
 arch/riscv/kernel/sys_hwprobe.c       |  7 +++++--
 5 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 4484f2a7f798..97226b7c5936 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -395,3 +395,19 @@ The following keys are defined:
 * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
   extensions that are compatible with the
   :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is supported,
+    as defined in the RISC-V Profiles specification starting from commit
+    b1d80660 ("Updated to ratified state.")
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported,
+    as defined in the RISC-V Profiles specification starting from commit
+    b1d80660 ("Updated to ratified state.")
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported,
+    as defined in the RISC-V Profiles specification starting from commit
+    b1d80660 ("Updated to ratified state.")
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported,
+    as defined in the RISC-V Profiles specification starting from commit
+    b1d80660 ("Updated to ratified state.")
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index c17e11caca83..8e764dbc7413 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -112,6 +112,9 @@
 #define RISCV_ISA_EXT_ZILSD		102
 #define RISCV_ISA_EXT_ZCLSD		103
 #define RISCV_ISA_EXT_ZICCLSM		104
+#define RISCV_ISA_EXT_ZICCAMOA		105
+#define RISCV_ISA_EXT_ZICCIF		106
+#define RISCV_ISA_EXT_ZA64RS		107
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 6a0163b54718..fed9ea6fd2b5 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -115,6 +115,10 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14
 #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE	15
 #define RISCV_HWPROBE_KEY_IMA_EXT_1		16
+#define		RISCV_HWPROBE_EXT_ZICCAMOA	(1 << 0)
+#define		RISCV_HWPROBE_EXT_ZICCIF	(1 << 1)
+#define		RISCV_HWPROBE_EXT_ZICCRSE	(1 << 2)
+#define		RISCV_HWPROBE_EXT_ZA64RS	(1 << 3)
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index ca7a34f66738..b001e78eecf6 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -488,6 +488,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
+	__RISCV_ISA_EXT_DATA(ziccamoa, RISCV_ISA_EXT_ZICCAMOA),
+	__RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF),
 	__RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM),
 	__RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
 	__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
@@ -498,6 +500,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
 	__RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
+	__RISCV_ISA_EXT_DATA(za64rs, RISCV_ISA_EXT_ZA64RS),
 	__RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
 	__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
 	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 76e673ab42a5..31d222301bf0 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -196,7 +196,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 	 * doesn't have.
 	 */
 	for_each_cpu(cpu, cpus) {
-		/* struct riscv_isainfo *isainfo = &hart_isa[cpu]; */
+		struct riscv_isainfo *isainfo = &hart_isa[cpu];
 
 		/*
 		 * Only use EXT_KEY() for extensions which can be
@@ -204,7 +204,10 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 		 * configuration, as no other checks, besides presence
 		 * in the hart_isa bitmap, are made.
 		 */
-		/* Nothing here yet */
+		EXT_KEY(isainfo->isa, ZICCAMOA, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICCRSE, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZA64RS, pair->value, missing);
 	}
 
 	/* Now turn off reporting features if any CPU is missing it. */
-- 
2.43.0


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[RFC PATCH v1 07/11] riscv: Export have_user_pmlen* booleans

[Andrew Jones]

A following patch will need to access have_user_pmlen_7 from
another file.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 arch/riscv/kernel/process.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 31a392993cb4..4fa14aff7f8d 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -274,8 +274,8 @@ enum {
 	PMLEN_16 = 16,
 };
 
-static bool have_user_pmlen_7;
-static bool have_user_pmlen_16;
+bool riscv_have_user_pmlen_7;
+bool riscv_have_user_pmlen_16;
 
 /*
  * Control the relaxed ABI allowing tagged user addresses into the kernel.
@@ -306,10 +306,10 @@ long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
 	pmlen = FIELD_GET(PR_PMLEN_MASK, arg);
 	if (pmlen == PMLEN_0) {
 		pmm = ENVCFG_PMM_PMLEN_0;
-	} else if (pmlen <= PMLEN_7 && have_user_pmlen_7) {
+	} else if (pmlen <= PMLEN_7 && riscv_have_user_pmlen_7) {
 		pmlen = PMLEN_7;
 		pmm = ENVCFG_PMM_PMLEN_7;
-	} else if (pmlen <= PMLEN_16 && have_user_pmlen_16) {
+	} else if (pmlen <= PMLEN_16 && riscv_have_user_pmlen_16) {
 		pmlen = PMLEN_16;
 		pmm = ENVCFG_PMM_PMLEN_16;
 	} else {
@@ -407,8 +407,8 @@ static int __init tagged_addr_init(void)
 	 * Assume the supported PMLEN values are the same on all harts.
 	 */
 	csr_clear(CSR_ENVCFG, ENVCFG_PMM);
-	have_user_pmlen_7 = try_to_set_pmm(ENVCFG_PMM_PMLEN_7);
-	have_user_pmlen_16 = try_to_set_pmm(ENVCFG_PMM_PMLEN_16);
+	riscv_have_user_pmlen_7 = try_to_set_pmm(ENVCFG_PMM_PMLEN_7);
+	riscv_have_user_pmlen_16 = try_to_set_pmm(ENVCFG_PMM_PMLEN_16);
 
 	if (!register_sysctl("abi", tagged_addr_sysctl_table))
 		return -EINVAL;
-- 
2.43.0


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[RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Andrew Jones]

Provide a bit to conveniently determine when RVA23U64 is supported.
While it's already possible to determine RVA23U64 support with five
hwprobe calls and four prctl calls it would be error-prone to require
anything (and we presume eventually almost everything) that needs to
check for RVA23U64 support to all implement those calls and specific
checks. And, while RVA23U64 is the IMA base with mandated extensions,
most software will consider it a new base. For these reasons, add
the RVA23U64 bit as a base behavior bit.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 Documentation/arch/riscv/hwprobe.rst          |  8 +++
 arch/riscv/include/uapi/asm/hwprobe.h         |  3 +-
 arch/riscv/kernel/sys_hwprobe.c               | 72 +++++++++++++++++++
 .../selftests/riscv/hwprobe/which-cpus.c      |  2 +-
 4 files changed, 83 insertions(+), 2 deletions(-)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 97226b7c5936..6d915e7ba58a 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -67,6 +67,14 @@ The following keys are defined:
       programs (it may still be executed in userspace via a
       kernel-controlled mechanism such as the vDSO).
 
+  * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64`: Support for all mandatory
+    extensions of RVA23U64, as defined in the RISC-V Profiles specification
+    starting from commit b1d80660 ("Updated to ratified state.")
+
+    The RVA23U64 base is based upon the IMA base and therefore IMA extension
+    keys (e.g. :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`:) may be used to probe
+    optional extensions.
+
 * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
   that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
   base system behavior.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index fed9ea6fd2b5..72d2a4d0b733 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -21,7 +21,8 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_MARCHID	1
 #define RISCV_HWPROBE_KEY_MIMPID	2
 #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR	3
-#define		RISCV_HWPROBE_BASE_BEHAVIOR_IMA	(1 << 0)
+#define		RISCV_HWPROBE_BASE_BEHAVIOR_IMA		(1 << 0)
+#define		RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64	(1 << 1)
 #define RISCV_HWPROBE_KEY_IMA_EXT_0	4
 #define		RISCV_HWPROBE_IMA_FD		(1 << 0)
 #define		RISCV_HWPROBE_IMA_C		(1 << 1)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 31d222301bf0..4b9981b15ebe 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -23,6 +23,7 @@
 #include <asm/vendor_extensions/thead_hwprobe.h>
 #include <vdso/vsyscall.h>
 
+extern bool riscv_have_user_pmlen_7;
 
 #define EXT_KEY(isa_arg, ext, pv, missing)					\
 	do {										\
@@ -222,6 +223,75 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext)
 	return (pair.value & ext);
 }
 
+#define HWPROBE_EXT0_RVA23U64 (					\
+	/* IMA is always supported */				\
+	RISCV_HWPROBE_IMA_FD				|	\
+	RISCV_HWPROBE_IMA_C				|	\
+	/* B is Zba, Zbb and Zbs */				\
+	RISCV_HWPROBE_EXT_ZBA				|	\
+	RISCV_HWPROBE_EXT_ZBB				|	\
+	RISCV_HWPROBE_EXT_ZBS				|	\
+	/* ZICSR is always supported */				\
+	RISCV_HWPROBE_EXT_ZICNTR			|	\
+	RISCV_HWPROBE_EXT_ZIHPM				|	\
+	/* ZICCIF is in EXT1 */					\
+	/* ZICCRSE is in EXT1 */				\
+	/* ZICCAMOA is in EXT1 */				\
+	RISCV_HWPROBE_EXT_ZICCLSM			|	\
+	/* ZA64RS is in EXT1 */					\
+	RISCV_HWPROBE_EXT_ZIHINTPAUSE			|	\
+	/* ZIC64B (check block sizes are 64b) */		\
+	RISCV_HWPROBE_EXT_ZICBOM			|	\
+	RISCV_HWPROBE_EXT_ZICBOP			|	\
+	RISCV_HWPROBE_EXT_ZICBOZ			|	\
+	RISCV_HWPROBE_EXT_ZFHMIN			|	\
+	RISCV_HWPROBE_EXT_ZKT				|	\
+	RISCV_HWPROBE_IMA_V				|	\
+	RISCV_HWPROBE_EXT_ZVFHMIN			|	\
+	RISCV_HWPROBE_EXT_ZVBB				|	\
+	RISCV_HWPROBE_EXT_ZVKT				|	\
+	RISCV_HWPROBE_EXT_ZIHINTNTL			|	\
+	RISCV_HWPROBE_EXT_ZICOND			|	\
+	RISCV_HWPROBE_EXT_ZIMOP				|	\
+	RISCV_HWPROBE_EXT_ZCMOP				|	\
+	RISCV_HWPROBE_EXT_ZCB				|	\
+	RISCV_HWPROBE_EXT_ZFA				|	\
+	RISCV_HWPROBE_EXT_ZAWRS				|	\
+	RISCV_HWPROBE_EXT_SUPM /* (check PMLEN=7 support) */	\
+)
+
+#define HWPROBE_EXT1_RVA23U64 (					\
+	RISCV_HWPROBE_EXT_ZICCIF			|	\
+	RISCV_HWPROBE_EXT_ZICCRSE			|	\
+	RISCV_HWPROBE_EXT_ZICCAMOA			|	\
+	RISCV_HWPROBE_EXT_ZA64RS				\
+)
+
+static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
+{
+	struct riscv_hwprobe pair;
+
+	if (!IS_ENABLED(CONFIG_64BIT))
+		return false;
+
+	/* Additional mandates for Zic64b and Supm */
+	if (riscv_cbom_block_size != 64 ||
+	    riscv_cbop_block_size != 64 ||
+	    riscv_cboz_block_size != 64 ||
+	    !riscv_have_user_pmlen_7)
+		return false;
+
+	hwprobe_isa_ext0(&pair, cpus);
+	if ((pair.value & HWPROBE_EXT0_RVA23U64) != HWPROBE_EXT0_RVA23U64)
+		return false;
+
+	hwprobe_isa_ext1(&pair, cpus);
+	if ((pair.value & HWPROBE_EXT1_RVA23U64) != HWPROBE_EXT1_RVA23U64)
+		return false;
+
+	return true;
+}
+
 #if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
 static u64 hwprobe_misaligned(const struct cpumask *cpus)
 {
@@ -312,6 +382,8 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
 	 */
 	case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
 		pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
+		if (hwprobe_has_rva23u64(cpus))
+			pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64;
 		break;
 
 	case RISCV_HWPROBE_KEY_IMA_EXT_0:
diff --git a/tools/testing/selftests/riscv/hwprobe/which-cpus.c b/tools/testing/selftests/riscv/hwprobe/which-cpus.c
index 587feb198c04..f8c797b1d0fd 100644
--- a/tools/testing/selftests/riscv/hwprobe/which-cpus.c
+++ b/tools/testing/selftests/riscv/hwprobe/which-cpus.c
@@ -105,7 +105,7 @@ int main(int argc, char **argv)
 	pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR, };
 	rc = riscv_hwprobe(pairs, 1, 0, NULL, 0);
 	assert(rc == 0 && pairs[0].key == RISCV_HWPROBE_KEY_BASE_BEHAVIOR &&
-	       pairs[0].value == RISCV_HWPROBE_BASE_BEHAVIOR_IMA);
+	       (pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA));
 
 	pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_0, };
 	rc = riscv_hwprobe(pairs, 1, 0, NULL, 0);
-- 
2.43.0


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[RFC PATCH v1 09/11] riscv: selftests: hwprobe: Check rva23u64 consistency

[Andrew Jones]

When the rva23u64 base behavior is advertised ensure all its
mandated extensions are also advertised. The prctl calls are
necessary to ensure PMLEN=0 and PMLEN=7 are supported, as that's
also mandated by the profiles spec for rva23u64.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 .../testing/selftests/riscv/hwprobe/hwprobe.c | 112 +++++++++++++++++-
 1 file changed, 111 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.c b/tools/testing/selftests/riscv/hwprobe/hwprobe.c
index 54c435af9923..780658867313 100644
--- a/tools/testing/selftests/riscv/hwprobe/hwprobe.c
+++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.c
@@ -1,7 +1,115 @@
 // SPDX-License-Identifier: GPL-2.0-only
+#include <assert.h>
+#include <uapi/linux/prctl.h>
+#include <sys/auxv.h>
+#include <sys/prctl.h>
+
 #include "hwprobe.h"
 #include "kselftest.h"
 
+#define RVA23U64_HWCAP ( \
+	(1 << ('I' - 'A')) | \
+	(1 << ('M' - 'A')) | \
+	(1 << ('A' - 'A')) | \
+	(1 << ('F' - 'A')) | \
+	(1 << ('D' - 'A')) | \
+	(1 << ('C' - 'A')) | \
+	(1 << ('B' - 'A')) | \
+	(1 << ('V' - 'A')) \
+)
+
+#define RVA23U64_EXT0 ( \
+	RISCV_HWPROBE_IMA_FD | \
+	RISCV_HWPROBE_IMA_C | \
+	RISCV_HWPROBE_IMA_V | \
+	RISCV_HWPROBE_EXT_ZBA | \
+	RISCV_HWPROBE_EXT_ZBB | \
+	RISCV_HWPROBE_EXT_ZBS | \
+	RISCV_HWPROBE_EXT_ZICBOZ | \
+	RISCV_HWPROBE_EXT_ZKT | \
+	RISCV_HWPROBE_EXT_ZVBB | \
+	RISCV_HWPROBE_EXT_ZVKT | \
+	RISCV_HWPROBE_EXT_ZFHMIN | \
+	RISCV_HWPROBE_EXT_ZIHINTNTL | \
+	RISCV_HWPROBE_EXT_ZVFHMIN | \
+	RISCV_HWPROBE_EXT_ZFA | \
+	RISCV_HWPROBE_EXT_ZICNTR | \
+	RISCV_HWPROBE_EXT_ZICOND | \
+	RISCV_HWPROBE_EXT_ZIHINTPAUSE | \
+	RISCV_HWPROBE_EXT_ZIHPM | \
+	RISCV_HWPROBE_EXT_ZIMOP | \
+	RISCV_HWPROBE_EXT_ZCB | \
+	RISCV_HWPROBE_EXT_ZCMOP | \
+	RISCV_HWPROBE_EXT_ZAWRS | \
+	RISCV_HWPROBE_EXT_SUPM | \
+	RISCV_HWPROBE_EXT_ZICBOM | \
+	RISCV_HWPROBE_EXT_ZICBOP | \
+	RISCV_HWPROBE_EXT_ZICCLSM \
+)
+
+#define RVA23U64_EXT1 ( \
+	RISCV_HWPROBE_EXT_ZICCAMOA | \
+	RISCV_HWPROBE_EXT_ZICCIF | \
+	RISCV_HWPROBE_EXT_ZICCRSE | \
+	RISCV_HWPROBE_EXT_ZA64RS \
+)
+
+static void check_rva23u64(unsigned long *cpus, size_t cpusetsize)
+{
+	struct riscv_hwprobe pairs[] = {
+		{ .key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR, },
+		{ .key = RISCV_HWPROBE_KEY_IMA_EXT_0, },
+		{ .key = RISCV_HWPROBE_KEY_IMA_EXT_1, },
+		{ .key = RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE, },
+		{ .key = RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE, },
+		{ .key = RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE, },
+	};
+	long ret, pmlen0, pmlen7;
+	unsigned long hwcap;
+
+	ret = riscv_hwprobe(pairs, ARRAY_SIZE(pairs), cpusetsize, cpus, 0);
+	assert(ret == 0);
+	assert(pairs[0].key == RISCV_HWPROBE_KEY_BASE_BEHAVIOR);
+	assert(pairs[1].key == RISCV_HWPROBE_KEY_IMA_EXT_0);
+	assert(pairs[3].key == RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE);
+	assert(pairs[4].key == RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE);
+	assert(pairs[5].key == RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE);
+
+	if (!(pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64)) {
+		ksft_test_result_skip("rva23u64 check, no RVA23U64 base behavior\n");
+		return;
+	}
+
+	assert(pairs[2].key == RISCV_HWPROBE_KEY_IMA_EXT_1);
+	assert(pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA);
+
+	if (prctl(PR_SET_TAGGED_ADDR_CTRL, 0 << PR_PMLEN_SHIFT, 0, 0, 0)) {
+		ksft_test_result_skip("rva23u64 check, failed PR_SET_TAGGED_ADDR_CTRL\n");
+		return;
+	}
+	ret = prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0);
+	if (ret < 0) {
+		ksft_test_result_skip("rva23u64 check, failed PR_GET_TAGGED_ADDR_CTRL\n");
+		return;
+	}
+	pmlen0 = (ret & PR_PMLEN_MASK) >> PR_PMLEN_SHIFT;
+
+	ret = prctl(PR_SET_TAGGED_ADDR_CTRL, 7 << PR_PMLEN_SHIFT, 0, 0, 0);
+	assert(ret == 0);
+	ret = prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0);
+	assert(ret >= 0);
+	pmlen7 = (ret & PR_PMLEN_MASK) >> PR_PMLEN_SHIFT;
+
+	hwcap = getauxval(AT_HWCAP);
+
+	ksft_test_result((pairs[1].value & RVA23U64_EXT0) == RVA23U64_EXT0 &&
+			 (pairs[2].value & RVA23U64_EXT1) == RVA23U64_EXT1 &&
+			 pairs[3].value == 64 && pairs[4].value == 64 && pairs[5].value == 64 &&
+			 pmlen0 == 0 && pmlen7 == 7 &&
+			 (hwcap & RVA23U64_HWCAP) == RVA23U64_HWCAP,
+			 "rva23u64 is consistent\n");
+}
+
 int main(int argc, char **argv)
 {
 	struct riscv_hwprobe pairs[8];
@@ -9,7 +117,7 @@ int main(int argc, char **argv)
 	long out;
 
 	ksft_print_header();
-	ksft_set_plan(5);
+	ksft_set_plan(6);
 
 	/* Fake the CPU_SET ops. */
 	cpus = -1;
@@ -62,5 +170,7 @@ int main(int argc, char **argv)
 			 pairs[1].key == 1 && pairs[1].value != 0xAAAA,
 			 "Unknown key overwritten with -1 and doesn't block other elements\n");
 
+	check_rva23u64(&cpus, 1);
+
 	ksft_finished();
 }
-- 
2.43.0


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[RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output

[Andrew Jones]

Output the rva23(u|s)64 ISA bases that the ISA extensions provide on
new 'isa bases' lines both for the LCD of all harts and per hart, as
shown in the example output below when booting qemu with
-cpu rva23s64,sv39=on,pmp=on:

processor       : 0
hart            : 4
isa bases       : rv64ima rva23u64
isa             : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
mmu             : sv39
mvendorid       : 0x0
marchid         : 0x0
mimpid          : 0x0
hart isa bases  : rv64ima rva23u64
hart isa        : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 arch/riscv/include/asm/cpufeature.h | 10 ++++
 arch/riscv/kernel/cpu.c             | 34 ++++++++++++
 arch/riscv/kernel/cpufeature.c      | 83 +++++++++++++++++++++++++++++
 3 files changed, 127 insertions(+)

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 62837fa981e8..e750735c5686 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -25,7 +25,15 @@ struct riscv_cpuinfo {
 	unsigned long mimpid;
 };
 
+enum {
+	RISCV_ISA_BASE_IMA,
+	RISCV_ISA_BASE_RVA23U64,
+	RISCV_ISA_BASE_RVA23S64,
+	RISCV_NR_ISA_BASES,
+};
+
 struct riscv_isainfo {
+	DECLARE_BITMAP(isa_bases, RISCV_NR_ISA_BASES);
 	DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
 };
 
@@ -152,4 +160,6 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi
 	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
 }
 
+void riscv_set_isa_bases(unsigned long *isa_bases, const unsigned long *isa_bitmap);
+
 #endif
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3dbc8cc557dd..228867d7dc00 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -305,6 +305,34 @@ static void print_mmu(struct seq_file *f)
 	seq_printf(f, "mmu\t\t: %s\n", sv_type);
 }
 
+static DECLARE_BITMAP(riscv_isa_bases, RISCV_NR_ISA_BASES);
+
+static const char * const riscv_isa_base_names[] = {
+#ifdef CONFIG_32BIT
+	[RISCV_ISA_BASE_IMA] = "rv32ima",
+#else
+	[RISCV_ISA_BASE_IMA] = "rv64ima",
+#endif
+	[RISCV_ISA_BASE_RVA23U64] = "rva23u64",
+	[RISCV_ISA_BASE_RVA23S64] = "rva23s64",
+};
+
+static void print_isa_bases(struct seq_file *m,
+			    const unsigned long *isa_bases,
+			    const unsigned long *isa)
+{
+	unsigned int i;
+
+	if (bitmap_empty(isa_bases, RISCV_NR_ISA_BASES))
+		riscv_set_isa_bases((unsigned long *)isa_bases, isa);
+
+	for (i = 0; i < RISCV_NR_ISA_BASES; i++) {
+		if (test_bit(i, isa_bases))
+			seq_printf(m, " %s", riscv_isa_base_names[i]);
+	}
+	seq_puts(m, "\n");
+}
+
 static void *c_start(struct seq_file *m, loff_t *pos)
 {
 	if (*pos == nr_cpu_ids)
@@ -336,6 +364,9 @@ static int c_show(struct seq_file *m, void *v)
 	seq_printf(m, "processor\t: %lu\n", cpu_id);
 	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
 
+	seq_puts(m, "isa bases\t:");
+	print_isa_bases(m, riscv_isa_bases, NULL);
+
 	/*
 	 * For historical raisins, the isa: line is limited to the lowest common
 	 * denominator of extensions supported across all harts. A true list of
@@ -360,6 +391,9 @@ static int c_show(struct seq_file *m, void *v)
 	seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
 	seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
 
+	seq_puts(m, "hart isa bases\t:");
+	print_isa_bases(m, hart_isa[cpu_id].isa_bases, hart_isa[cpu_id].isa);
+
 	/*
 	 * Print the ISA extensions specific to this hart, which may show
 	 * additional extensions not present across all harts.
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b001e78eecf6..07a42545e9e0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -1262,3 +1262,86 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
 	}
 }
 #endif
+
+extern bool riscv_have_user_pmlen_7;
+
+void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)
+{
+	const unsigned long *isa = isa_bitmap ? isa_bitmap : riscv_isa;
+	DECLARE_BITMAP(ext_mask, RISCV_ISA_EXT_MAX) = { 0 };
+	DECLARE_BITMAP(tmp, RISCV_ISA_EXT_MAX);
+
+	/* IMA */
+	set_bit(RISCV_ISA_EXT_I, ext_mask);
+	set_bit(RISCV_ISA_EXT_M, ext_mask);
+	set_bit(RISCV_ISA_EXT_A, ext_mask);
+
+	if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		return;
+
+	set_bit(RISCV_ISA_BASE_IMA, bases);
+
+	/* RVA23U64 */
+
+	/* Zic64b and Supm with PMLEN=7 */
+	if (riscv_cbom_block_size != 64 ||
+	    riscv_cbop_block_size != 64 ||
+	    riscv_cboz_block_size != 64 ||
+	    !riscv_have_user_pmlen_7)
+		return;
+
+	set_bit(RISCV_ISA_EXT_F, ext_mask);
+	set_bit(RISCV_ISA_EXT_D, ext_mask);
+	set_bit(RISCV_ISA_EXT_C, ext_mask);
+	set_bit(RISCV_ISA_EXT_B, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICNTR, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICCIF, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICCRSE, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICCAMOA, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZA64RS, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZIHINTPAUSE, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICBOM, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICBOP, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICBOZ, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZFHMIN, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZKT, ext_mask);
+	set_bit(RISCV_ISA_EXT_V, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZVFHMIN, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZVBB, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZVKT, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZIHINTNTL, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICOND, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZIMOP, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZCMOP, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZCB, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZFA, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZAWRS, ext_mask);
+	set_bit(RISCV_ISA_EXT_SUPM, ext_mask);
+
+	if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		return;
+
+	set_bit(RISCV_ISA_BASE_RVA23U64, bases);
+
+	/* RVA23S64 */
+	set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
+	/* TODO: Ss1p13 */
+	/* Svbare, Sv39 -- assumed */
+	set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
+	/* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */
+	set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
+	set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
+	set_bit(RISCV_ISA_EXT_SVNAPOT, ext_mask);
+	set_bit(RISCV_ISA_EXT_SSTC, ext_mask);
+	set_bit(RISCV_ISA_EXT_SSCOFPMF, ext_mask);
+	set_bit(RISCV_ISA_EXT_SSNPM, ext_mask);
+	/* TODO: Ssu64xl */
+	/* TODO: Sha = Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa */
+	set_bit(RISCV_ISA_EXT_H, ext_mask);
+
+	if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		set_bit(RISCV_ISA_BASE_RVA23S64, bases);
+}
-- 
2.43.0


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[RFC PATCH v1 11/11] riscv: /proc/cpuinfo: Also output rva20 and rva22 isa bases

[Andrew Jones]

Include rva(20|22)(u|s)64 isa bases in the output when they are
detected.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 arch/riscv/include/asm/cpufeature.h |  4 ++
 arch/riscv/kernel/cpu.c             |  4 ++
 arch/riscv/kernel/cpufeature.c      | 65 +++++++++++++++++++++++------
 3 files changed, 61 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index e750735c5686..41431e89bb3b 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -27,6 +27,10 @@ struct riscv_cpuinfo {
 
 enum {
 	RISCV_ISA_BASE_IMA,
+	RISCV_ISA_BASE_RVA20U64,
+	RISCV_ISA_BASE_RVA20S64,
+	RISCV_ISA_BASE_RVA22U64,
+	RISCV_ISA_BASE_RVA22S64,
 	RISCV_ISA_BASE_RVA23U64,
 	RISCV_ISA_BASE_RVA23S64,
 	RISCV_NR_ISA_BASES,
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 228867d7dc00..007958744ae5 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -313,6 +313,10 @@ static const char * const riscv_isa_base_names[] = {
 #else
 	[RISCV_ISA_BASE_IMA] = "rv64ima",
 #endif
+	[RISCV_ISA_BASE_RVA20U64] = "rva20u64",
+	[RISCV_ISA_BASE_RVA20S64] = "rva20s64",
+	[RISCV_ISA_BASE_RVA22U64] = "rva22u64",
+	[RISCV_ISA_BASE_RVA22S64] = "rva22s64",
 	[RISCV_ISA_BASE_RVA23U64] = "rva23u64",
 	[RISCV_ISA_BASE_RVA23S64] = "rva23s64",
 };
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 07a42545e9e0..ac46b974e5e4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -1281,33 +1281,74 @@ void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)
 
 	set_bit(RISCV_ISA_BASE_IMA, bases);
 
-	/* RVA23U64 */
-
-	/* Zic64b and Supm with PMLEN=7 */
-	if (riscv_cbom_block_size != 64 ||
-	    riscv_cbop_block_size != 64 ||
-	    riscv_cboz_block_size != 64 ||
-	    !riscv_have_user_pmlen_7)
-		return;
-
+	/* RVA20U64 */
 	set_bit(RISCV_ISA_EXT_F, ext_mask);
 	set_bit(RISCV_ISA_EXT_D, ext_mask);
 	set_bit(RISCV_ISA_EXT_C, ext_mask);
-	set_bit(RISCV_ISA_EXT_B, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICNTR, ext_mask);
-	set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICCIF, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICCRSE, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICCAMOA, ext_mask);
-	set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask);
+	/* Spec says Za128rs, but Za64rs is compatible and mandated by later profiles */
 	set_bit(RISCV_ISA_EXT_ZA64RS, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask);
+
+	if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		return;
+
+	set_bit(RISCV_ISA_BASE_RVA20U64, bases);
+
+	/* RVA20S64 */
+	set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
+	/* TODO: Ss1p11 */
+	/* Svbare, Sv39 -- assumed */
+	set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
+	/* TODO: Ssccptr, Sstvecd, Sstvala */
+
+	if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		set_bit(RISCV_ISA_BASE_RVA20S64, bases);
+
+	/* RVA22U64 */
+
+	/* Zic64b */
+	if (riscv_cbom_block_size != 64 ||
+	    riscv_cbop_block_size != 64 ||
+	    riscv_cboz_block_size != 64)
+		return;
+
+	set_bit(RISCV_ISA_EXT_B, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZIHINTPAUSE, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICBOM, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICBOP, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICBOZ, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZFHMIN, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZKT, ext_mask);
+
+	if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		return;
+
+	set_bit(RISCV_ISA_BASE_RVA22U64, bases);
+
+	/* RVA22S64 */
+	set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
+	/* TODO: Ss1p12 */
+	/* Svbare, Sv39 -- assumed */
+	set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
+	/* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */
+	set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
+	set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
+
+	if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		set_bit(RISCV_ISA_BASE_RVA22S64, bases);
+
+	/* RVA23U64 */
+
+	/* Supm with PMLEN=7 */
+	if (!riscv_have_user_pmlen_7)
+		return;
+
 	set_bit(RISCV_ISA_EXT_V, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZVFHMIN, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZVBB, ext_mask);
-- 
2.43.0


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Re: [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Andrew Jones]

On Thu, Feb 05, 2026 at 06:23:46PM -0600, Andrew Jones wrote:
...
> +static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
> +{
> +	struct riscv_hwprobe pair;
> +
> +	if (!IS_ENABLED(CONFIG_64BIT))
> +		return false;
> +
> +	/* Additional mandates for Zic64b and Supm */
> +	if (riscv_cbom_block_size != 64 ||
> +	    riscv_cbop_block_size != 64 ||
> +	    riscv_cboz_block_size != 64 ||
> +	    !riscv_have_user_pmlen_7)
> +		return false;
> +

Thanks to kernel test robot's report I'll fix the compilation of this for
configs without RISCV_ISA_SUPM with the following change and something
similar for patch10.

Thanks,
drew

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 4b9981b15ebe..3fd63ac7dd60 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -278,7 +278,7 @@ static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
        if (riscv_cbom_block_size != 64 ||
            riscv_cbop_block_size != 64 ||
            riscv_cboz_block_size != 64 ||
-           !riscv_have_user_pmlen_7)
+           !IS_ENABLED(CONFIG_RISCV_ISA_SUPM) || !riscv_have_user_pmlen_7)
                return false;

        hwprobe_isa_ext0(&pair, cpus);

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Re: [RFC PATCH v1 04/11] riscv: Add B to hwcap

[Guodong Xu]

Hi, Drew

On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs
> are all set.
>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> ---
>  arch/riscv/include/asm/hwcap.h      | 1 +
>  arch/riscv/include/uapi/asm/hwcap.h | 1 +
>  arch/riscv/kernel/cpufeature.c      | 8 ++++++++
>  3 files changed, 10 insertions(+)

I saw you chose not to add B to hwprobe in this series, per
your review of my patch [1]. I have a different opinion.

As you said, FD, C, and V are all exported through both hwcap
and hwprobe. Adding B to hwprobe too keeps things consistent,
users can query all the single-letter extensions from one
interface without needing to know that B is missing in hwprobe
and that they'd have to check Zba/Zbb/Zbs to infer B support.

Relying on the rva23u64 base bit to imply B also doesn't cover
chips that implement B without being rva23u64 compliant. Eg. my
patchset [2] adds support for existing (non-rva23u64) SoCs.

Link: https://lore.kernel.org/all/k3riksgjci3jw7tgqf27tu6vrfxfs6e7jo5jinwwadyruyqgb6@apqyim4zdcqc/
[1]
Link: https://lore.kernel.org/all/20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com/
[2]

Thanks,
Guodong



Guodong

>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 03acd22bbbaa..c17e11caca83 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -11,6 +11,7 @@
>  #include <uapi/asm/hwcap.h>
>
>  #define RISCV_ISA_EXT_A                ('a' - 'a')
> +#define RISCV_ISA_EXT_B                ('b' - 'a')
>  #define RISCV_ISA_EXT_C                ('c' - 'a')
>  #define RISCV_ISA_EXT_D                ('d' - 'a')
>  #define RISCV_ISA_EXT_F                ('f' - 'a')
> diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
> index c52bb7bbbabe..96b7cf854e09 100644
> --- a/arch/riscv/include/uapi/asm/hwcap.h
> +++ b/arch/riscv/include/uapi/asm/hwcap.h
> @@ -21,6 +21,7 @@
>  #define COMPAT_HWCAP_ISA_F     (1 << ('F' - 'A'))
>  #define COMPAT_HWCAP_ISA_D     (1 << ('D' - 'A'))
>  #define COMPAT_HWCAP_ISA_C     (1 << ('C' - 'A'))
> +#define COMPAT_HWCAP_ISA_B     (1 << ('B' - 'A'))
>  #define COMPAT_HWCAP_ISA_V     (1 << ('V' - 'A'))
>
>  #endif /* _UAPI_ASM_RISCV_HWCAP_H */
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 25ed1d6958d7..ca7a34f66738 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -429,6 +429,12 @@ static const unsigned int riscv_c_exts[] = {
>         RISCV_ISA_EXT_ZCD,
>  };
>
> +static const unsigned int riscv_b_exts[] = {
> +       RISCV_ISA_EXT_ZBA,
> +       RISCV_ISA_EXT_ZBB,
> +       RISCV_ISA_EXT_ZBS,
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * chapter 27 of the unprivileged specification.
> @@ -476,6 +482,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>         __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_D, riscv_ext_d_validate),
>         __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q),
>         __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts),
> +       __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),
>         __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts, riscv_ext_vector_float_validate),
>         __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H),
>         __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
> @@ -1089,6 +1096,7 @@ void __init riscv_fill_hwcap(void)
>         isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
>         isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
>         isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
> +       isa2hwcap['b' - 'a'] = COMPAT_HWCAP_ISA_B;
>         isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
>
>         if (!acpi_disabled) {
> --
> 2.43.0
>

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Re: [RFC PATCH v1 06/11] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe

[Guodong Xu]

On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> Ziccrse is already present in cpufeature.
>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> ---
>  Documentation/arch/riscv/hwprobe.rst  | 16 ++++++++++++++++
>  arch/riscv/include/asm/hwcap.h        |  3 +++
>  arch/riscv/include/uapi/asm/hwprobe.h |  4 ++++
>  arch/riscv/kernel/cpufeature.c        |  3 +++
>  arch/riscv/kernel/sys_hwprobe.c       |  7 +++++--
>  5 files changed, 31 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 4484f2a7f798..97226b7c5936 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -395,3 +395,19 @@ The following keys are defined:
>  * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
>    extensions that are compatible with the
>    :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is supported,
> +    as defined in the RISC-V Profiles specification starting from commit
> +    b1d80660 ("Updated to ratified state.")
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported,
> +    as defined in the RISC-V Profiles specification starting from commit
> +    b1d80660 ("Updated to ratified state.")
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported,
> +    as defined in the RISC-V Profiles specification starting from commit
> +    b1d80660 ("Updated to ratified state.")
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported,
> +    as defined in the RISC-V Profiles specification starting from commit
> +    b1d80660 ("Updated to ratified state.")
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index c17e11caca83..8e764dbc7413 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -112,6 +112,9 @@
>  #define RISCV_ISA_EXT_ZILSD            102
>  #define RISCV_ISA_EXT_ZCLSD            103
>  #define RISCV_ISA_EXT_ZICCLSM          104
> +#define RISCV_ISA_EXT_ZICCAMOA         105
> +#define RISCV_ISA_EXT_ZICCIF           106
> +#define RISCV_ISA_EXT_ZA64RS           107
>
>  #define RISCV_ISA_EXT_XLINUXENVCFG     127
>
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 6a0163b54718..fed9ea6fd2b5 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -115,6 +115,10 @@ struct riscv_hwprobe {
>  #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0    14
>  #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE    15
>  #define RISCV_HWPROBE_KEY_IMA_EXT_1            16
> +#define                RISCV_HWPROBE_EXT_ZICCAMOA      (1 << 0)
> +#define                RISCV_HWPROBE_EXT_ZICCIF        (1 << 1)
> +#define                RISCV_HWPROBE_EXT_ZICCRSE       (1 << 2)
> +#define                RISCV_HWPROBE_EXT_ZA64RS        (1 << 3)
>  /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
>  /* Flags */
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index ca7a34f66738..b001e78eecf6 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -488,6 +488,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>         __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
>         __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
>         __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
> +       __RISCV_ISA_EXT_DATA(ziccamoa, RISCV_ISA_EXT_ZICCAMOA),

It might be good to also enforce extension dependencies here:
Za64rs depends on Zalrsc, and Ziccamoa depends on Zaamo. I did
something similar in my series [1]. Like this:

+ __RISCV_ISA_EXT_DATA_VALIDATE(ziccamoa, RISCV_ISA_EXT_ZICCAMOA,
riscv_ext_zaamo_depends),

If you agree, I can prepare a standalone patch adding these dependency
checks and send it your way.

> +       __RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF),
>         __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM),
>         __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
>         __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
> @@ -498,6 +500,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>         __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
>         __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
>         __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
> +       __RISCV_ISA_EXT_DATA(za64rs, RISCV_ISA_EXT_ZA64RS),

And add dependency here for za64rs:
+       __RISCV_ISA_EXT_DATA_VALIDATE(za64rs, RISCV_ISA_EXT_ZA64RS,
riscv_ext_zalrsc_depends),

Link: https://lore.kernel.org/all/20260207-isa-ext-parse-export-v1-4-a64d3a8bc20a@riscstar.com/
[1]

BR,
Guodong


Guodong

>         __RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
>         __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
>         __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 76e673ab42a5..31d222301bf0 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -196,7 +196,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
>          * doesn't have.
>          */
>         for_each_cpu(cpu, cpus) {
> -               /* struct riscv_isainfo *isainfo = &hart_isa[cpu]; */
> +               struct riscv_isainfo *isainfo = &hart_isa[cpu];
>
>                 /*
>                  * Only use EXT_KEY() for extensions which can be
> @@ -204,7 +204,10 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
>                  * configuration, as no other checks, besides presence
>                  * in the hart_isa bitmap, are made.
>                  */
> -               /* Nothing here yet */
> +               EXT_KEY(isainfo->isa, ZICCAMOA, pair->value, missing);
> +               EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing);
> +               EXT_KEY(isainfo->isa, ZICCRSE, pair->value, missing);
> +               EXT_KEY(isainfo->isa, ZA64RS, pair->value, missing);
>         }
>
>         /* Now turn off reporting features if any CPU is missing it. */
> --
> 2.43.0
>

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Re: [RFC PATCH v1 07/11] riscv: Export have_user_pmlen* booleans

[Guodong Xu]

On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> A following patch will need to access have_user_pmlen_7 from
> another file.

The variables are made non-static here but without an extern
declaration in a header.

How about adding the declarations to asm/processor.h, inside the
protection of the CONFIG_RISCV_ISA_SUPM block?

sys_hwprobe.c already includes asm/processor.h, so no new includes
would be needed.

PS: I spotted one more of your patch [10/11] refers to it, which adds
another bare extern in cpufeature.c.

BR,
Guodong



>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> ---
>  arch/riscv/kernel/process.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> index 31a392993cb4..4fa14aff7f8d 100644
> --- a/arch/riscv/kernel/process.c
> +++ b/arch/riscv/kernel/process.c
> @@ -274,8 +274,8 @@ enum {
>         PMLEN_16 = 16,
>  };
>
> -static bool have_user_pmlen_7;
> -static bool have_user_pmlen_16;
> +bool riscv_have_user_pmlen_7;
> +bool riscv_have_user_pmlen_16;
>
>  /*
>   * Control the relaxed ABI allowing tagged user addresses into the kernel.
> @@ -306,10 +306,10 @@ long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
>         pmlen = FIELD_GET(PR_PMLEN_MASK, arg);
>         if (pmlen == PMLEN_0) {
>                 pmm = ENVCFG_PMM_PMLEN_0;
> -       } else if (pmlen <= PMLEN_7 && have_user_pmlen_7) {
> +       } else if (pmlen <= PMLEN_7 && riscv_have_user_pmlen_7) {
>                 pmlen = PMLEN_7;
>                 pmm = ENVCFG_PMM_PMLEN_7;
> -       } else if (pmlen <= PMLEN_16 && have_user_pmlen_16) {
> +       } else if (pmlen <= PMLEN_16 && riscv_have_user_pmlen_16) {
>                 pmlen = PMLEN_16;
>                 pmm = ENVCFG_PMM_PMLEN_16;
>         } else {
> @@ -407,8 +407,8 @@ static int __init tagged_addr_init(void)
>          * Assume the supported PMLEN values are the same on all harts.
>          */
>         csr_clear(CSR_ENVCFG, ENVCFG_PMM);
> -       have_user_pmlen_7 = try_to_set_pmm(ENVCFG_PMM_PMLEN_7);
> -       have_user_pmlen_16 = try_to_set_pmm(ENVCFG_PMM_PMLEN_16);
> +       riscv_have_user_pmlen_7 = try_to_set_pmm(ENVCFG_PMM_PMLEN_7);
> +       riscv_have_user_pmlen_16 = try_to_set_pmm(ENVCFG_PMM_PMLEN_16);
>
>         if (!register_sysctl("abi", tagged_addr_sysctl_table))
>                 return -EINVAL;
> --
> 2.43.0
>

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Re: [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Guodong Xu]

Hi, Drew

On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> Provide a bit to conveniently determine when RVA23U64 is supported.
> While it's already possible to determine RVA23U64 support with five
> hwprobe calls and four prctl calls it would be error-prone to require
> anything (and we presume eventually almost everything) that needs to
> check for RVA23U64 support to all implement those calls and specific
> checks. And, while RVA23U64 is the IMA base with mandated extensions,
> most software will consider it a new base. For these reasons, add
> the RVA23U64 bit as a base behavior bit.
>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> ---
>  Documentation/arch/riscv/hwprobe.rst          |  8 +++
>  arch/riscv/include/uapi/asm/hwprobe.h         |  3 +-
>  arch/riscv/kernel/sys_hwprobe.c               | 72 +++++++++++++++++++
>  .../selftests/riscv/hwprobe/which-cpus.c      |  2 +-
>  4 files changed, 83 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 97226b7c5936..6d915e7ba58a 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -67,6 +67,14 @@ The following keys are defined:
>        programs (it may still be executed in userspace via a
>        kernel-controlled mechanism such as the vDSO).
>
> +  * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64`: Support for all mandatory
> +    extensions of RVA23U64, as defined in the RISC-V Profiles specification
> +    starting from commit b1d80660 ("Updated to ratified state.")

Should we reference the commit which ratifies RVA23 to its 1.0 version?
I mean commit 0273f3c9 ("rva23/rvb23 ratified"), Oct 2024.

At commit b1d80660, rva23-profile.adoc exists and covers RVA23U64,
however, it is still at revnumber 0.1-draft ("Development stage"). As
its evolving nature, the content revolves from 0.1 to 1.0. I believe
it's more useful to people to point them to a ratified version, instead
of introducing history to them.

Another suggestion, how about just referring to the ratified 1.0
document itself, which can be found at RISC-V International's official
website [1], following the link "Ratified Profiles Specification".

Link: https://riscv.org/specifications/ratified/ [1]

> +
> +    The RVA23U64 base is based upon the IMA base and therefore IMA extension
> +    keys (e.g. :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`:) may be used to probe
> +    optional extensions.
> +
>  * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
>    that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
>    base system behavior.
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index fed9ea6fd2b5..72d2a4d0b733 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -21,7 +21,8 @@ struct riscv_hwprobe {
>  #define RISCV_HWPROBE_KEY_MARCHID      1
>  #define RISCV_HWPROBE_KEY_MIMPID       2
>  #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR        3
> -#define                RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
> +#define                RISCV_HWPROBE_BASE_BEHAVIOR_IMA         (1 << 0)
> +#define                RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64    (1 << 1)
>  #define RISCV_HWPROBE_KEY_IMA_EXT_0    4
>  #define                RISCV_HWPROBE_IMA_FD            (1 << 0)
>  #define                RISCV_HWPROBE_IMA_C             (1 << 1)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 31d222301bf0..4b9981b15ebe 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -23,6 +23,7 @@
>  #include <asm/vendor_extensions/thead_hwprobe.h>
>  #include <vdso/vsyscall.h>
>
> +extern bool riscv_have_user_pmlen_7;

Suggest to put this in a header, like <asm/processor.h>

>
>  #define EXT_KEY(isa_arg, ext, pv, missing)                                     \
>         do {                                                                            \
> @@ -222,6 +223,75 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext)
>         return (pair.value & ext);
>  }
>
> +#define HWPROBE_EXT0_RVA23U64 (                                        \
> +       /* IMA is always supported */                           \
> +       RISCV_HWPROBE_IMA_FD                            |       \
> +       RISCV_HWPROBE_IMA_C                             |       \
> +       /* B is Zba, Zbb and Zbs */                             \
> +       RISCV_HWPROBE_EXT_ZBA                           |       \
> +       RISCV_HWPROBE_EXT_ZBB                           |       \
> +       RISCV_HWPROBE_EXT_ZBS                           |       \
> +       /* ZICSR is always supported */                         \
> +       RISCV_HWPROBE_EXT_ZICNTR                        |       \
> +       RISCV_HWPROBE_EXT_ZIHPM                         |       \
> +       /* ZICCIF is in EXT1 */                                 \
> +       /* ZICCRSE is in EXT1 */                                \
> +       /* ZICCAMOA is in EXT1 */                               \
> +       RISCV_HWPROBE_EXT_ZICCLSM                       |       \
> +       /* ZA64RS is in EXT1 */                                 \
> +       RISCV_HWPROBE_EXT_ZIHINTPAUSE                   |       \
> +       /* ZIC64B (check block sizes are 64b) */                \
> +       RISCV_HWPROBE_EXT_ZICBOM                        |       \
> +       RISCV_HWPROBE_EXT_ZICBOP                        |       \
> +       RISCV_HWPROBE_EXT_ZICBOZ                        |       \
> +       RISCV_HWPROBE_EXT_ZFHMIN                        |       \
> +       RISCV_HWPROBE_EXT_ZKT                           |       \
> +       RISCV_HWPROBE_IMA_V                             |       \
> +       RISCV_HWPROBE_EXT_ZVFHMIN                       |       \
> +       RISCV_HWPROBE_EXT_ZVBB                          |       \
> +       RISCV_HWPROBE_EXT_ZVKT                          |       \
> +       RISCV_HWPROBE_EXT_ZIHINTNTL                     |       \
> +       RISCV_HWPROBE_EXT_ZICOND                        |       \
> +       RISCV_HWPROBE_EXT_ZIMOP                         |       \
> +       RISCV_HWPROBE_EXT_ZCMOP                         |       \
> +       RISCV_HWPROBE_EXT_ZCB                           |       \
> +       RISCV_HWPROBE_EXT_ZFA                           |       \
> +       RISCV_HWPROBE_EXT_ZAWRS                         |       \
> +       RISCV_HWPROBE_EXT_SUPM /* (check PMLEN=7 support) */    \
> +)
> +
> +#define HWPROBE_EXT1_RVA23U64 (                                        \
> +       RISCV_HWPROBE_EXT_ZICCIF                        |       \
> +       RISCV_HWPROBE_EXT_ZICCRSE                       |       \
> +       RISCV_HWPROBE_EXT_ZICCAMOA                      |       \
> +       RISCV_HWPROBE_EXT_ZA64RS                                \
> +)
> +
> +static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
> +{
> +       struct riscv_hwprobe pair;
> +
> +       if (!IS_ENABLED(CONFIG_64BIT))
> +               return false;
> +
> +       /* Additional mandates for Zic64b and Supm */
> +       if (riscv_cbom_block_size != 64 ||
> +           riscv_cbop_block_size != 64 ||
> +           riscv_cboz_block_size != 64 ||
> +           !riscv_have_user_pmlen_7)
> +               return false;
> +
> +       hwprobe_isa_ext0(&pair, cpus);
> +       if ((pair.value & HWPROBE_EXT0_RVA23U64) != HWPROBE_EXT0_RVA23U64)
> +               return false;
> +
> +       hwprobe_isa_ext1(&pair, cpus);
> +       if ((pair.value & HWPROBE_EXT1_RVA23U64) != HWPROBE_EXT1_RVA23U64)
> +               return false;
> +
> +       return true;
> +}
> +
>  #if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
>  static u64 hwprobe_misaligned(const struct cpumask *cpus)
>  {
> @@ -312,6 +382,8 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>          */
>         case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
>                 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
> +               if (hwprobe_has_rva23u64(cpus))
> +                       pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64;

There are two separate implementations of RVA23U64 detection in
your patchset:
1. In this patch: hwprobe_has_rva23u64(), which checks against
RISCV_HWPROBE_EXT_* bits.
2. In [Patch 10/11]: riscv_set_isa_bases(), which checks against
RISCV_ISA_EXT_*.

I'm not sure I fully understand your reasoning behind this
duplication (it's too obvious for me not to doubt myself). At
least for now, I think the hwprobe version is not good from an
architecture viewpoint.

My logic is this: RVA23U64 is a hardware implementation feature.
It exists no matter whether you export its sub-components (those
mandatory extensions required by RVA23 Profile) through hwprobe or
not. Profile conformance vs. per-extension export should stay
independent.

DT/ACPI -> RISCV_ISA_EXT_*: these are ground truth.
RISCV_HWPROBE_EXT_*: these are a filtered subset.

We shouldn't be pushed to export (hwprobe) an extension just
to make the RVA23U64 calculation correct. The criteria for
exporting an extension through hwprobe should be based on
whether there is a userspace consumer who needs it
individually.

BR,
Guodong


>                 break;
>
>         case RISCV_HWPROBE_KEY_IMA_EXT_0:
> diff --git a/tools/testing/selftests/riscv/hwprobe/which-cpus.c b/tools/testing/selftests/riscv/hwprobe/which-cpus.c
> index 587feb198c04..f8c797b1d0fd 100644
> --- a/tools/testing/selftests/riscv/hwprobe/which-cpus.c
> +++ b/tools/testing/selftests/riscv/hwprobe/which-cpus.c
> @@ -105,7 +105,7 @@ int main(int argc, char **argv)
>         pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR, };
>         rc = riscv_hwprobe(pairs, 1, 0, NULL, 0);
>         assert(rc == 0 && pairs[0].key == RISCV_HWPROBE_KEY_BASE_BEHAVIOR &&
> -              pairs[0].value == RISCV_HWPROBE_BASE_BEHAVIOR_IMA);
> +              (pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA));
>
>         pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_0, };
>         rc = riscv_hwprobe(pairs, 1, 0, NULL, 0);
> --
> 2.43.0
>

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Re: [RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output

[Guodong Xu]

On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> Output the rva23(u|s)64 ISA bases that the ISA extensions provide on
> new 'isa bases' lines both for the LCD of all harts and per hart, as
> shown in the example output below when booting qemu with
> -cpu rva23s64,sv39=on,pmp=on:
>
> processor       : 0
> hart            : 4
> isa bases       : rv64ima rva23u64
> isa             : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> mmu             : sv39
> mvendorid       : 0x0
> marchid         : 0x0
> mimpid          : 0x0
> hart isa bases  : rv64ima rva23u64
> hart isa        : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> ---
>  arch/riscv/include/asm/cpufeature.h | 10 ++++
>  arch/riscv/kernel/cpu.c             | 34 ++++++++++++
>  arch/riscv/kernel/cpufeature.c      | 83 +++++++++++++++++++++++++++++
>  3 files changed, 127 insertions(+)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 62837fa981e8..e750735c5686 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -25,7 +25,15 @@ struct riscv_cpuinfo {
>         unsigned long mimpid;
>  };
>
> +enum {
> +       RISCV_ISA_BASE_IMA,
> +       RISCV_ISA_BASE_RVA23U64,
> +       RISCV_ISA_BASE_RVA23S64,
> +       RISCV_NR_ISA_BASES,
> +};
> +
>  struct riscv_isainfo {
> +       DECLARE_BITMAP(isa_bases, RISCV_NR_ISA_BASES);
>         DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
>  };
>
> @@ -152,4 +160,6 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi
>         return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
>  }
>
> +void riscv_set_isa_bases(unsigned long *isa_bases, const unsigned long *isa_bitmap);
> +
>  #endif
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 3dbc8cc557dd..228867d7dc00 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -305,6 +305,34 @@ static void print_mmu(struct seq_file *f)
>         seq_printf(f, "mmu\t\t: %s\n", sv_type);
>  }
>
> +static DECLARE_BITMAP(riscv_isa_bases, RISCV_NR_ISA_BASES);
> +
> +static const char * const riscv_isa_base_names[] = {
> +#ifdef CONFIG_32BIT
> +       [RISCV_ISA_BASE_IMA] = "rv32ima",
> +#else
> +       [RISCV_ISA_BASE_IMA] = "rv64ima",
> +#endif
> +       [RISCV_ISA_BASE_RVA23U64] = "rva23u64",
> +       [RISCV_ISA_BASE_RVA23S64] = "rva23s64",
> +};
> +
> +static void print_isa_bases(struct seq_file *m,
> +                           const unsigned long *isa_bases,
> +                           const unsigned long *isa)
> +{
> +       unsigned int i;
> +
> +       if (bitmap_empty(isa_bases, RISCV_NR_ISA_BASES))
> +               riscv_set_isa_bases((unsigned long *)isa_bases, isa);
> +
> +       for (i = 0; i < RISCV_NR_ISA_BASES; i++) {
> +               if (test_bit(i, isa_bases))
> +                       seq_printf(m, " %s", riscv_isa_base_names[i]);
> +       }
> +       seq_puts(m, "\n");
> +}
> +
>  static void *c_start(struct seq_file *m, loff_t *pos)
>  {
>         if (*pos == nr_cpu_ids)
> @@ -336,6 +364,9 @@ static int c_show(struct seq_file *m, void *v)
>         seq_printf(m, "processor\t: %lu\n", cpu_id);
>         seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
>
> +       seq_puts(m, "isa bases\t:");
> +       print_isa_bases(m, riscv_isa_bases, NULL);
> +
>         /*
>          * For historical raisins, the isa: line is limited to the lowest common
>          * denominator of extensions supported across all harts. A true list of
> @@ -360,6 +391,9 @@ static int c_show(struct seq_file *m, void *v)
>         seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
>         seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
>
> +       seq_puts(m, "hart isa bases\t:");
> +       print_isa_bases(m, hart_isa[cpu_id].isa_bases, hart_isa[cpu_id].isa);
> +
>         /*
>          * Print the ISA extensions specific to this hart, which may show
>          * additional extensions not present across all harts.
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index b001e78eecf6..07a42545e9e0 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -1262,3 +1262,86 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
>         }
>  }
>  #endif
> +
> +extern bool riscv_have_user_pmlen_7;
> +
> +void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)

I have no objection to the implementation of this function. My
concern is that, from looking at the patch, the only way to
trigger it is by cat /proc/cpuinfo, i.e., from print_isa_bases().

Shouldn't this be computed during init (e.g., in
riscv_fill_hwcap()) so the result is available to other
consumers like hwprobe?

> +{
> +       const unsigned long *isa = isa_bitmap ? isa_bitmap : riscv_isa;
> +       DECLARE_BITMAP(ext_mask, RISCV_ISA_EXT_MAX) = { 0 };
> +       DECLARE_BITMAP(tmp, RISCV_ISA_EXT_MAX);
> +
> +       /* IMA */
> +       set_bit(RISCV_ISA_EXT_I, ext_mask);
> +       set_bit(RISCV_ISA_EXT_M, ext_mask);
> +       set_bit(RISCV_ISA_EXT_A, ext_mask);
> +
> +       if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
> +               return;
> +
> +       set_bit(RISCV_ISA_BASE_IMA, bases);
> +
> +       /* RVA23U64 */
> +
> +       /* Zic64b and Supm with PMLEN=7 */
> +       if (riscv_cbom_block_size != 64 ||
> +           riscv_cbop_block_size != 64 ||
> +           riscv_cboz_block_size != 64 ||
> +           !riscv_have_user_pmlen_7)
> +               return;
> +
> +       set_bit(RISCV_ISA_EXT_F, ext_mask);
> +       set_bit(RISCV_ISA_EXT_D, ext_mask);
> +       set_bit(RISCV_ISA_EXT_C, ext_mask);
> +       set_bit(RISCV_ISA_EXT_B, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICNTR, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICCIF, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICCRSE, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICCAMOA, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZA64RS, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZIHINTPAUSE, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICBOM, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICBOP, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICBOZ, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZFHMIN, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZKT, ext_mask);
> +       set_bit(RISCV_ISA_EXT_V, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZVFHMIN, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZVBB, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZVKT, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZIHINTNTL, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZICOND, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZIMOP, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZCMOP, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZCB, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZFA, ext_mask);
> +       set_bit(RISCV_ISA_EXT_ZAWRS, ext_mask);
> +       set_bit(RISCV_ISA_EXT_SUPM, ext_mask);
> +
> +       if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
> +               return;
> +
> +       set_bit(RISCV_ISA_BASE_RVA23U64, bases);
> +
> +       /* RVA23S64 */
> +       set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
> +       /* TODO: Ss1p13 */
> +       /* Svbare, Sv39 -- assumed */
> +       set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
> +       /* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */

For this,

> +       set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
> +       set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
> +       set_bit(RISCV_ISA_EXT_SVNAPOT, ext_mask);
> +       set_bit(RISCV_ISA_EXT_SSTC, ext_mask);
> +       set_bit(RISCV_ISA_EXT_SSCOFPMF, ext_mask);
> +       set_bit(RISCV_ISA_EXT_SSNPM, ext_mask);
> +       /* TODO: Ssu64xl */
> +       /* TODO: Sha = Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa */

And this, these TODOs, I'd be happy if my patches 7 and 8 [1] can be
useful here.

Link: https://lore.kernel.org/all/20260207-isa-ext-parse-export-v1-7-a64d3a8bc20a@riscstar.com/
[1]

BR,
Guodong


> +       set_bit(RISCV_ISA_EXT_H, ext_mask);
> +
> +       if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
> +               set_bit(RISCV_ISA_BASE_RVA23S64, bases);
> +}
> --
> 2.43.0
>

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Re: [RFC PATCH v1 04/11] riscv: Add B to hwcap

[Andrew Jones]

On Sat, Feb 21, 2026 at 06:49:18PM +0800, Guodong Xu wrote:
> Hi, Drew
> 
> On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs
> > are all set.
> >
> > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > ---
> >  arch/riscv/include/asm/hwcap.h      | 1 +
> >  arch/riscv/include/uapi/asm/hwcap.h | 1 +
> >  arch/riscv/kernel/cpufeature.c      | 8 ++++++++
> >  3 files changed, 10 insertions(+)
> 
> I saw you chose not to add B to hwprobe in this series, per
> your review of my patch [1]. I have a different opinion.
> 
> As you said, FD, C, and V are all exported through both hwcap
> and hwprobe. Adding B to hwprobe too keeps things consistent,
> users can query all the single-letter extensions from one
> interface without needing to know that B is missing in hwprobe
> and that they'd have to check Zba/Zbb/Zbs to infer B support.
> 
> Relying on the rva23u64 base bit to imply B also doesn't cover
> chips that implement B without being rva23u64 compliant. Eg. my
> patchset [2] adds support for existing (non-rva23u64) SoCs.
>

I think we need to come up with some sort of policy as to what goes to
hwprobe and what doesn't. IMO, hwcap is easy. If RISC-V defines a single
letter extension, such as V or B, then we should add it to hwcap. However,
for hwprobe, we can go two ways:

 1. Add every extension, including 'bundle' extensions, which are nothing
 more than an alias for a collection of extensions. This includes single
 letter bundle extensions like B.

 2. Add only unique extensions, i.e. no purely bundle extensions get
 added.

If we go with (2), then userspace will need to use the base behaviors
(profiles) in order to get any sort of bundling, but I think most people
agree that userspace will target profiles, so (2) seems sufficient. I'm
not sure about applications that won't target profiles but will want to
check for bundle extensions rather than individual extensions. Should we
take on the maintenance burden of adding each bundle extension to hwprobe
for those? In particular, I'm not sure about B, because it's already
available independently of a base behavior (profile) through hwcap.

Thanks,
drew

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Re: [RFC PATCH v1 06/11] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe

[Andrew Jones]

On Sat, Feb 21, 2026 at 06:50:25PM +0800, Guodong Xu wrote:
> On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > Ziccrse is already present in cpufeature.
> >
> > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > ---
> >  Documentation/arch/riscv/hwprobe.rst  | 16 ++++++++++++++++
> >  arch/riscv/include/asm/hwcap.h        |  3 +++
> >  arch/riscv/include/uapi/asm/hwprobe.h |  4 ++++
> >  arch/riscv/kernel/cpufeature.c        |  3 +++
> >  arch/riscv/kernel/sys_hwprobe.c       |  7 +++++--
> >  5 files changed, 31 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index 4484f2a7f798..97226b7c5936 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -395,3 +395,19 @@ The following keys are defined:
> >  * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
> >    extensions that are compatible with the
> >    :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is supported,
> > +    as defined in the RISC-V Profiles specification starting from commit
> > +    b1d80660 ("Updated to ratified state.")
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported,
> > +    as defined in the RISC-V Profiles specification starting from commit
> > +    b1d80660 ("Updated to ratified state.")
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported,
> > +    as defined in the RISC-V Profiles specification starting from commit
> > +    b1d80660 ("Updated to ratified state.")
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported,
> > +    as defined in the RISC-V Profiles specification starting from commit
> > +    b1d80660 ("Updated to ratified state.")
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index c17e11caca83..8e764dbc7413 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -112,6 +112,9 @@
> >  #define RISCV_ISA_EXT_ZILSD            102
> >  #define RISCV_ISA_EXT_ZCLSD            103
> >  #define RISCV_ISA_EXT_ZICCLSM          104
> > +#define RISCV_ISA_EXT_ZICCAMOA         105
> > +#define RISCV_ISA_EXT_ZICCIF           106
> > +#define RISCV_ISA_EXT_ZA64RS           107
> >
> >  #define RISCV_ISA_EXT_XLINUXENVCFG     127
> >
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 6a0163b54718..fed9ea6fd2b5 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -115,6 +115,10 @@ struct riscv_hwprobe {
> >  #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0    14
> >  #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE    15
> >  #define RISCV_HWPROBE_KEY_IMA_EXT_1            16
> > +#define                RISCV_HWPROBE_EXT_ZICCAMOA      (1 << 0)
> > +#define                RISCV_HWPROBE_EXT_ZICCIF        (1 << 1)
> > +#define                RISCV_HWPROBE_EXT_ZICCRSE       (1 << 2)
> > +#define                RISCV_HWPROBE_EXT_ZA64RS        (1 << 3)
> >  /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
> >
> >  /* Flags */
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index ca7a34f66738..b001e78eecf6 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -488,6 +488,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >         __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
> >         __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
> >         __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
> > +       __RISCV_ISA_EXT_DATA(ziccamoa, RISCV_ISA_EXT_ZICCAMOA),
> 
> It might be good to also enforce extension dependencies here:
> Za64rs depends on Zalrsc, and Ziccamoa depends on Zaamo.

There's certainly a practical "dependency". Za64rs wouldn't make much
sense to support without instructions that need a reservation set. And
similarly Ziccamoa doesn't make much sense without Zaamo. However, I'm not
aware of anything that explicitly states Ziccamoa implies Zaamo or Za64rs
implies Zalrsc. So, in the absence of any rules, I vote we leave them
independent.

Thanks,
drew

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Re: [RFC PATCH v1 07/11] riscv: Export have_user_pmlen* booleans

[Andrew Jones]

On Sat, Feb 21, 2026 at 06:50:43PM +0800, Guodong Xu wrote:
> On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > A following patch will need to access have_user_pmlen_7 from
> > another file.
> 
> The variables are made non-static here but without an extern
> declaration in a header.
> 
> How about adding the declarations to asm/processor.h, inside the
> protection of the CONFIG_RISCV_ISA_SUPM block?

Yes, I guess asm/processor.h is a random enough collection of stuff that
have_user_pmlen_7 fits in there as well as anywhere else. Maybe I'll add
a getter function instead, though

 bool riscv_have_user_pmlen(u32 len)

Thanks,
drew

> 
> sys_hwprobe.c already includes asm/processor.h, so no new includes
> would be needed.
> 
> PS: I spotted one more of your patch [10/11] refers to it, which adds
> another bare extern in cpufeature.c.
> 
> BR,
> Guodong
> 
> 
> 
> >
> > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > ---
> >  arch/riscv/kernel/process.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> > index 31a392993cb4..4fa14aff7f8d 100644
> > --- a/arch/riscv/kernel/process.c
> > +++ b/arch/riscv/kernel/process.c
> > @@ -274,8 +274,8 @@ enum {
> >         PMLEN_16 = 16,
> >  };
> >
> > -static bool have_user_pmlen_7;
> > -static bool have_user_pmlen_16;
> > +bool riscv_have_user_pmlen_7;
> > +bool riscv_have_user_pmlen_16;
> >
> >  /*
> >   * Control the relaxed ABI allowing tagged user addresses into the kernel.
> > @@ -306,10 +306,10 @@ long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
> >         pmlen = FIELD_GET(PR_PMLEN_MASK, arg);
> >         if (pmlen == PMLEN_0) {
> >                 pmm = ENVCFG_PMM_PMLEN_0;
> > -       } else if (pmlen <= PMLEN_7 && have_user_pmlen_7) {
> > +       } else if (pmlen <= PMLEN_7 && riscv_have_user_pmlen_7) {
> >                 pmlen = PMLEN_7;
> >                 pmm = ENVCFG_PMM_PMLEN_7;
> > -       } else if (pmlen <= PMLEN_16 && have_user_pmlen_16) {
> > +       } else if (pmlen <= PMLEN_16 && riscv_have_user_pmlen_16) {
> >                 pmlen = PMLEN_16;
> >                 pmm = ENVCFG_PMM_PMLEN_16;
> >         } else {
> > @@ -407,8 +407,8 @@ static int __init tagged_addr_init(void)
> >          * Assume the supported PMLEN values are the same on all harts.
> >          */
> >         csr_clear(CSR_ENVCFG, ENVCFG_PMM);
> > -       have_user_pmlen_7 = try_to_set_pmm(ENVCFG_PMM_PMLEN_7);
> > -       have_user_pmlen_16 = try_to_set_pmm(ENVCFG_PMM_PMLEN_16);
> > +       riscv_have_user_pmlen_7 = try_to_set_pmm(ENVCFG_PMM_PMLEN_7);
> > +       riscv_have_user_pmlen_16 = try_to_set_pmm(ENVCFG_PMM_PMLEN_16);
> >
> >         if (!register_sysctl("abi", tagged_addr_sysctl_table))
> >                 return -EINVAL;
> > --
> > 2.43.0
> >

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Re: [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Andrew Jones]

On Sat, Feb 21, 2026 at 06:51:25PM +0800, Guodong Xu wrote:
> Hi, Drew
> 
> On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > Provide a bit to conveniently determine when RVA23U64 is supported.
> > While it's already possible to determine RVA23U64 support with five
> > hwprobe calls and four prctl calls it would be error-prone to require
> > anything (and we presume eventually almost everything) that needs to
> > check for RVA23U64 support to all implement those calls and specific
> > checks. And, while RVA23U64 is the IMA base with mandated extensions,
> > most software will consider it a new base. For these reasons, add
> > the RVA23U64 bit as a base behavior bit.
> >
> > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > ---
> >  Documentation/arch/riscv/hwprobe.rst          |  8 +++
> >  arch/riscv/include/uapi/asm/hwprobe.h         |  3 +-
> >  arch/riscv/kernel/sys_hwprobe.c               | 72 +++++++++++++++++++
> >  .../selftests/riscv/hwprobe/which-cpus.c      |  2 +-
> >  4 files changed, 83 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index 97226b7c5936..6d915e7ba58a 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -67,6 +67,14 @@ The following keys are defined:
> >        programs (it may still be executed in userspace via a
> >        kernel-controlled mechanism such as the vDSO).
> >
> > +  * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64`: Support for all mandatory
> > +    extensions of RVA23U64, as defined in the RISC-V Profiles specification
> > +    starting from commit b1d80660 ("Updated to ratified state.")
> 
> Should we reference the commit which ratifies RVA23 to its 1.0 version?
> I mean commit 0273f3c9 ("rva23/rvb23 ratified"), Oct 2024.
> 
> At commit b1d80660, rva23-profile.adoc exists and covers RVA23U64,
> however, it is still at revnumber 0.1-draft ("Development stage"). As
> its evolving nature, the content revolves from 0.1 to 1.0. I believe
> it's more useful to people to point them to a ratified version, instead
> of introducing history to them.
> 
> Another suggestion, how about just referring to the ratified 1.0
> document itself, which can be found at RISC-V International's official
> website [1], following the link "Ratified Profiles Specification".
> 
> Link: https://riscv.org/specifications/ratified/ [1]

I prefer a commit, like we do for the extensions, but the commit you point
out looks like the correct one according to the Oct 2024 date, which
matches the PDF date on the web page.

> 
> > +
> > +    The RVA23U64 base is based upon the IMA base and therefore IMA extension
> > +    keys (e.g. :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`:) may be used to probe
> > +    optional extensions.
> > +
> >  * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
> >    that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
> >    base system behavior.
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index fed9ea6fd2b5..72d2a4d0b733 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -21,7 +21,8 @@ struct riscv_hwprobe {
> >  #define RISCV_HWPROBE_KEY_MARCHID      1
> >  #define RISCV_HWPROBE_KEY_MIMPID       2
> >  #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR        3
> > -#define                RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
> > +#define                RISCV_HWPROBE_BASE_BEHAVIOR_IMA         (1 << 0)
> > +#define                RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64    (1 << 1)
> >  #define RISCV_HWPROBE_KEY_IMA_EXT_0    4
> >  #define                RISCV_HWPROBE_IMA_FD            (1 << 0)
> >  #define                RISCV_HWPROBE_IMA_C             (1 << 1)
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index 31d222301bf0..4b9981b15ebe 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -23,6 +23,7 @@
> >  #include <asm/vendor_extensions/thead_hwprobe.h>
> >  #include <vdso/vsyscall.h>
> >
> > +extern bool riscv_have_user_pmlen_7;
> 
> Suggest to put this in a header, like <asm/processor.h>
> 
> >
> >  #define EXT_KEY(isa_arg, ext, pv, missing)                                     \
> >         do {                                                                            \
> > @@ -222,6 +223,75 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext)
> >         return (pair.value & ext);
> >  }
> >
> > +#define HWPROBE_EXT0_RVA23U64 (                                        \
> > +       /* IMA is always supported */                           \
> > +       RISCV_HWPROBE_IMA_FD                            |       \
> > +       RISCV_HWPROBE_IMA_C                             |       \
> > +       /* B is Zba, Zbb and Zbs */                             \
> > +       RISCV_HWPROBE_EXT_ZBA                           |       \
> > +       RISCV_HWPROBE_EXT_ZBB                           |       \
> > +       RISCV_HWPROBE_EXT_ZBS                           |       \
> > +       /* ZICSR is always supported */                         \
> > +       RISCV_HWPROBE_EXT_ZICNTR                        |       \
> > +       RISCV_HWPROBE_EXT_ZIHPM                         |       \
> > +       /* ZICCIF is in EXT1 */                                 \
> > +       /* ZICCRSE is in EXT1 */                                \
> > +       /* ZICCAMOA is in EXT1 */                               \
> > +       RISCV_HWPROBE_EXT_ZICCLSM                       |       \
> > +       /* ZA64RS is in EXT1 */                                 \
> > +       RISCV_HWPROBE_EXT_ZIHINTPAUSE                   |       \
> > +       /* ZIC64B (check block sizes are 64b) */                \
> > +       RISCV_HWPROBE_EXT_ZICBOM                        |       \
> > +       RISCV_HWPROBE_EXT_ZICBOP                        |       \
> > +       RISCV_HWPROBE_EXT_ZICBOZ                        |       \
> > +       RISCV_HWPROBE_EXT_ZFHMIN                        |       \
> > +       RISCV_HWPROBE_EXT_ZKT                           |       \
> > +       RISCV_HWPROBE_IMA_V                             |       \
> > +       RISCV_HWPROBE_EXT_ZVFHMIN                       |       \
> > +       RISCV_HWPROBE_EXT_ZVBB                          |       \
> > +       RISCV_HWPROBE_EXT_ZVKT                          |       \
> > +       RISCV_HWPROBE_EXT_ZIHINTNTL                     |       \
> > +       RISCV_HWPROBE_EXT_ZICOND                        |       \
> > +       RISCV_HWPROBE_EXT_ZIMOP                         |       \
> > +       RISCV_HWPROBE_EXT_ZCMOP                         |       \
> > +       RISCV_HWPROBE_EXT_ZCB                           |       \
> > +       RISCV_HWPROBE_EXT_ZFA                           |       \
> > +       RISCV_HWPROBE_EXT_ZAWRS                         |       \
> > +       RISCV_HWPROBE_EXT_SUPM /* (check PMLEN=7 support) */    \
> > +)
> > +
> > +#define HWPROBE_EXT1_RVA23U64 (                                        \
> > +       RISCV_HWPROBE_EXT_ZICCIF                        |       \
> > +       RISCV_HWPROBE_EXT_ZICCRSE                       |       \
> > +       RISCV_HWPROBE_EXT_ZICCAMOA                      |       \
> > +       RISCV_HWPROBE_EXT_ZA64RS                                \
> > +)
> > +
> > +static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
> > +{
> > +       struct riscv_hwprobe pair;
> > +
> > +       if (!IS_ENABLED(CONFIG_64BIT))
> > +               return false;
> > +
> > +       /* Additional mandates for Zic64b and Supm */
> > +       if (riscv_cbom_block_size != 64 ||
> > +           riscv_cbop_block_size != 64 ||
> > +           riscv_cboz_block_size != 64 ||
> > +           !riscv_have_user_pmlen_7)
> > +               return false;
> > +
> > +       hwprobe_isa_ext0(&pair, cpus);
> > +       if ((pair.value & HWPROBE_EXT0_RVA23U64) != HWPROBE_EXT0_RVA23U64)
> > +               return false;
> > +
> > +       hwprobe_isa_ext1(&pair, cpus);
> > +       if ((pair.value & HWPROBE_EXT1_RVA23U64) != HWPROBE_EXT1_RVA23U64)
> > +               return false;
> > +
> > +       return true;
> > +}
> > +
> >  #if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
> >  static u64 hwprobe_misaligned(const struct cpumask *cpus)
> >  {
> > @@ -312,6 +382,8 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> >          */
> >         case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
> >                 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
> > +               if (hwprobe_has_rva23u64(cpus))
> > +                       pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64;
> 
> There are two separate implementations of RVA23U64 detection in
> your patchset:
> 1. In this patch: hwprobe_has_rva23u64(), which checks against
> RISCV_HWPROBE_EXT_* bits.
> 2. In [Patch 10/11]: riscv_set_isa_bases(), which checks against
> RISCV_ISA_EXT_*.
> 
> I'm not sure I fully understand your reasoning behind this
> duplication (it's too obvious for me not to doubt myself).

We purposely use hwprobe bits in hwprobe since we want to ensure
consistency. We use the isa bits everywhere else as that's the
typical place to check.

> At
> least for now, I think the hwprobe version is not good from an
> architecture viewpoint.
> 
> My logic is this: RVA23U64 is a hardware implementation feature.
> It exists no matter whether you export its sub-components (those
> mandatory extensions required by RVA23 Profile) through hwprobe or
> not. Profile conformance vs. per-extension export should stay
> independent.
> 
> DT/ACPI -> RISCV_ISA_EXT_*: these are ground truth.
> RISCV_HWPROBE_EXT_*: these are a filtered subset.
> 
> We shouldn't be pushed to export (hwprobe) an extension just
> to make the RVA23U64 calculation correct. The criteria for
> exporting an extension through hwprobe should be based on
> whether there is a userspace consumer who needs it
> individually.

I agree with the "only publish stuff in hwprobe that users care about"
approach and we do have precedent for not publishing extensions covered
by the base already (I, M, and A are not individually in hwprobe --
although they are in hwcap).

For this series I could drop any extensions that people are unlikely to
care about individually from hwprobe. Anyway, they can always be added
later when needed. I was fond of my hwprobe consistency selftest though...

Thanks,
drew

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Re: [RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output

[Andrew Jones]

On Sat, Feb 21, 2026 at 06:52:19PM +0800, Guodong Xu wrote:
> On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > Output the rva23(u|s)64 ISA bases that the ISA extensions provide on
> > new 'isa bases' lines both for the LCD of all harts and per hart, as
> > shown in the example output below when booting qemu with
> > -cpu rva23s64,sv39=on,pmp=on:
> >
> > processor       : 0
> > hart            : 4
> > isa bases       : rv64ima rva23u64
> > isa             : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> > mmu             : sv39
> > mvendorid       : 0x0
> > marchid         : 0x0
> > mimpid          : 0x0
> > hart isa bases  : rv64ima rva23u64
> > hart isa        : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> >
> > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > ---
> >  arch/riscv/include/asm/cpufeature.h | 10 ++++
> >  arch/riscv/kernel/cpu.c             | 34 ++++++++++++
> >  arch/riscv/kernel/cpufeature.c      | 83 +++++++++++++++++++++++++++++
> >  3 files changed, 127 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > index 62837fa981e8..e750735c5686 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -25,7 +25,15 @@ struct riscv_cpuinfo {
> >         unsigned long mimpid;
> >  };
> >
> > +enum {
> > +       RISCV_ISA_BASE_IMA,
> > +       RISCV_ISA_BASE_RVA23U64,
> > +       RISCV_ISA_BASE_RVA23S64,
> > +       RISCV_NR_ISA_BASES,
> > +};
> > +
> >  struct riscv_isainfo {
> > +       DECLARE_BITMAP(isa_bases, RISCV_NR_ISA_BASES);
> >         DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
> >  };
> >
> > @@ -152,4 +160,6 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi
> >         return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
> >  }
> >
> > +void riscv_set_isa_bases(unsigned long *isa_bases, const unsigned long *isa_bitmap);
> > +
> >  #endif
> > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> > index 3dbc8cc557dd..228867d7dc00 100644
> > --- a/arch/riscv/kernel/cpu.c
> > +++ b/arch/riscv/kernel/cpu.c
> > @@ -305,6 +305,34 @@ static void print_mmu(struct seq_file *f)
> >         seq_printf(f, "mmu\t\t: %s\n", sv_type);
> >  }
> >
> > +static DECLARE_BITMAP(riscv_isa_bases, RISCV_NR_ISA_BASES);
> > +
> > +static const char * const riscv_isa_base_names[] = {
> > +#ifdef CONFIG_32BIT
> > +       [RISCV_ISA_BASE_IMA] = "rv32ima",
> > +#else
> > +       [RISCV_ISA_BASE_IMA] = "rv64ima",
> > +#endif
> > +       [RISCV_ISA_BASE_RVA23U64] = "rva23u64",
> > +       [RISCV_ISA_BASE_RVA23S64] = "rva23s64",
> > +};
> > +
> > +static void print_isa_bases(struct seq_file *m,
> > +                           const unsigned long *isa_bases,
> > +                           const unsigned long *isa)
> > +{
> > +       unsigned int i;
> > +
> > +       if (bitmap_empty(isa_bases, RISCV_NR_ISA_BASES))
> > +               riscv_set_isa_bases((unsigned long *)isa_bases, isa);
> > +
> > +       for (i = 0; i < RISCV_NR_ISA_BASES; i++) {
> > +               if (test_bit(i, isa_bases))
> > +                       seq_printf(m, " %s", riscv_isa_base_names[i]);
> > +       }
> > +       seq_puts(m, "\n");
> > +}
> > +
> >  static void *c_start(struct seq_file *m, loff_t *pos)
> >  {
> >         if (*pos == nr_cpu_ids)
> > @@ -336,6 +364,9 @@ static int c_show(struct seq_file *m, void *v)
> >         seq_printf(m, "processor\t: %lu\n", cpu_id);
> >         seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
> >
> > +       seq_puts(m, "isa bases\t:");
> > +       print_isa_bases(m, riscv_isa_bases, NULL);
> > +
> >         /*
> >          * For historical raisins, the isa: line is limited to the lowest common
> >          * denominator of extensions supported across all harts. A true list of
> > @@ -360,6 +391,9 @@ static int c_show(struct seq_file *m, void *v)
> >         seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
> >         seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
> >
> > +       seq_puts(m, "hart isa bases\t:");
> > +       print_isa_bases(m, hart_isa[cpu_id].isa_bases, hart_isa[cpu_id].isa);
> > +
> >         /*
> >          * Print the ISA extensions specific to this hart, which may show
> >          * additional extensions not present across all harts.
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index b001e78eecf6..07a42545e9e0 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -1262,3 +1262,86 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
> >         }
> >  }
> >  #endif
> > +
> > +extern bool riscv_have_user_pmlen_7;
> > +
> > +void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)
> 
> I have no objection to the implementation of this function. My
> concern is that, from looking at the patch, the only way to
> trigger it is by cat /proc/cpuinfo, i.e., from print_isa_bases().
> 
> Shouldn't this be computed during init (e.g., in
> riscv_fill_hwcap()) so the result is available to other
> consumers like hwprobe?

Yes, particularly if we drop some stuff from hwprobe making it impossible
to compute rva23 from hwprobe bits.

> 
> > +{
> > +       const unsigned long *isa = isa_bitmap ? isa_bitmap : riscv_isa;
> > +       DECLARE_BITMAP(ext_mask, RISCV_ISA_EXT_MAX) = { 0 };
> > +       DECLARE_BITMAP(tmp, RISCV_ISA_EXT_MAX);
> > +
> > +       /* IMA */
> > +       set_bit(RISCV_ISA_EXT_I, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_M, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_A, ext_mask);
> > +
> > +       if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
> > +               return;
> > +
> > +       set_bit(RISCV_ISA_BASE_IMA, bases);
> > +
> > +       /* RVA23U64 */
> > +
> > +       /* Zic64b and Supm with PMLEN=7 */
> > +       if (riscv_cbom_block_size != 64 ||
> > +           riscv_cbop_block_size != 64 ||
> > +           riscv_cboz_block_size != 64 ||
> > +           !riscv_have_user_pmlen_7)
> > +               return;
> > +
> > +       set_bit(RISCV_ISA_EXT_F, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_D, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_C, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_B, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICNTR, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICCIF, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICCRSE, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICCAMOA, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZA64RS, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZIHINTPAUSE, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICBOM, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICBOP, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICBOZ, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZFHMIN, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZKT, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_V, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZVFHMIN, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZVBB, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZVKT, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZIHINTNTL, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZICOND, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZIMOP, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZCMOP, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZCB, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZFA, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_ZAWRS, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_SUPM, ext_mask);
> > +
> > +       if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
> > +               return;
> > +
> > +       set_bit(RISCV_ISA_BASE_RVA23U64, bases);
> > +
> > +       /* RVA23S64 */
> > +       set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
> > +       /* TODO: Ss1p13 */
> > +       /* Svbare, Sv39 -- assumed */
> > +       set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
> > +       /* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */
> 
> For this,
> 
> > +       set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_SVNAPOT, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_SSTC, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_SSCOFPMF, ext_mask);
> > +       set_bit(RISCV_ISA_EXT_SSNPM, ext_mask);
> > +       /* TODO: Ssu64xl */
> > +       /* TODO: Sha = Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa */
> 
> And this, these TODOs, I'd be happy if my patches 7 and 8 [1] can be
> useful here.
> 
> Link: https://lore.kernel.org/all/20260207-isa-ext-parse-export-v1-7-a64d3a8bc20a@riscstar.com/
> [1]

Absolutely!

Thanks,
drew

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Re: [RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Charlie Jenkins]

On Thu, Feb 05, 2026 at 06:23:38PM -0600, Andrew Jones wrote:
> Users need a way determine that their harts conform to rva23u64 that
> isn't error-prone. While patches 2 and 6 make it possible to determine,
> it requires a bunch of probes and checks themselves (see patch9 for the
> recipe). This RFC proposes adding an RVA23U64 hwprobe base behavior
> (patch8) allowing easy determination. It also proposes adding the bases
> to /proc/cpuinfo (patches 10 and 11) -- but those two patches are probably
> even more RFCy than the hwprobe proposal...
> 
> The first three patches have been posted previously by their respective
> authors and are currently under active review (except patch2 which
> appears to have gotten lost in the shuffle). I've collected these
> patches into the series since they're necessary for the base and
> because I wanted to repost patch2 and patch3 with some changes. patch4
> and patch6 expose more extensions to userspace. patch9 adds a consistency
> test for the new hwprobe base behavior bit.

Great series! Thanks for pulling these all together, I like this
direction. We had dropped patch2 because we were using it for some
misaligned access optimizations but then realized that the extension
wasn't useful for that so then the patches got lost.

In Linux 7.0, patch 1 got applied along with CFI using the first flags of
the second key so there is some rebasing to do.

I think putting the compatibility info in /proc/cpuinfo is a good idea.
There is always hesitance around /proc/cpuinfo because some ill-advised
programs try to parse information from it, but it is nice to have an
easy way for users to see the compatility and since you also added the
hwprobe interface for it this seems reasonable.

- Charlie

> 
> Thanks,
> drew
> 
> 
> Andrew Jones (8):
>   riscv: Add B to hwcap
>   riscv: hwprobe.rst: Replace tabs with spaces
>   riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe
>   riscv: Export have_user_pmlen* booleans
>   riscv: hwprobe: Introduce rva23u64 base behavior
>   riscv: selftests: hwprobe: Check rva23u64 consistency
>   riscv: /proc/cpuinfo: Add rva23 bases to output
>   riscv: /proc/cpuinfo: Also output rva20 and rva22 isa bases
> 
> Charlie Jenkins (1):
>   riscv: Standardize extension capitilization
> 
> Jesse Taube (1):
>   RISC-V: Add Zicclsm to cpufeature and hwprobe
> 
> Paul Walmsley (1):
>   riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1
> 
>  Documentation/arch/riscv/hwprobe.rst          |  42 ++-
>  arch/riscv/include/asm/cpufeature.h           |  14 +
>  arch/riscv/include/asm/hwcap.h                |  23 +-
>  arch/riscv/include/asm/hwprobe.h              |   3 +-
>  arch/riscv/include/asm/switch_to.h            |   4 +-
>  arch/riscv/include/uapi/asm/hwcap.h           |   1 +
>  arch/riscv/include/uapi/asm/hwprobe.h         |   9 +-
>  arch/riscv/kernel/cpu.c                       |  38 +++
>  arch/riscv/kernel/cpufeature.c                | 168 ++++++++++--
>  arch/riscv/kernel/process.c                   |  12 +-
>  arch/riscv/kernel/sys_hwprobe.c               | 249 +++++++++++++-----
>  arch/riscv/kvm/main.c                         |   2 +-
>  arch/riscv/kvm/vcpu_fp.c                      |  28 +-
>  arch/riscv/kvm/vcpu_onereg.c                  |  22 +-
>  arch/riscv/kvm/vcpu_vector.c                  |  14 +-
>  .../testing/selftests/riscv/hwprobe/hwprobe.c | 112 +++++++-
>  .../selftests/riscv/hwprobe/which-cpus.c      |  20 +-
>  17 files changed, 610 insertions(+), 151 deletions(-)
> 
> -- 
> 2.43.0
> 

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Re: [RFC PATCH v1 04/11] riscv: Add B to hwcap

[Guodong Xu]

On Wed, Feb 25, 2026 at 7:05 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> On Sat, Feb 21, 2026 at 06:49:18PM +0800, Guodong Xu wrote:
> > Hi, Drew
> >
> > On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> > <andrew.jones@oss.qualcomm.com> wrote:
> > >
> > > Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs
> > > are all set.
> > >
> > > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > > ---
> > >  arch/riscv/include/asm/hwcap.h      | 1 +
> > >  arch/riscv/include/uapi/asm/hwcap.h | 1 +
> > >  arch/riscv/kernel/cpufeature.c      | 8 ++++++++
> > >  3 files changed, 10 insertions(+)
> >
> > I saw you chose not to add B to hwprobe in this series, per
> > your review of my patch [1]. I have a different opinion.
> >
> > As you said, FD, C, and V are all exported through both hwcap
> > and hwprobe. Adding B to hwprobe too keeps things consistent,
> > users can query all the single-letter extensions from one
> > interface without needing to know that B is missing in hwprobe
> > and that they'd have to check Zba/Zbb/Zbs to infer B support.
> >
> > Relying on the rva23u64 base bit to imply B also doesn't cover
> > chips that implement B without being rva23u64 compliant. Eg. my
> > patchset [2] adds support for existing (non-rva23u64) SoCs.
> >
>
> I think we need to come up with some sort of policy as to what goes to
> hwprobe and what doesn't. IMO, hwcap is easy. If RISC-V defines a single
> letter extension, such as V or B, then we should add it to hwcap. However,

When we export an extension through hwcap but it cannot
be queried through hwprobe, we create an inconsistency:
the same extension is discoverable through one interface
but not the other.

The current kernel already exposes other single-letter
extensions through both interfaces:

  F+D: RISCV_HWPROBE_IMA_FD + COMPAT_HWCAP_ISA_F/_D
  C:   RISCV_HWPROBE_IMA_C  + COMPAT_HWCAP_ISA_C
  V:   RISCV_HWPROBE_IMA_V  + COMPAT_HWCAP_ISA_V

(I/M/A are folded into RISCV_HWPROBE_BASE_BEHAVIOR_IMA,
so they are a separate case.)

F, D, C, and V are consistent between hwcap and hwprobe.
Why should B be different?

> for hwprobe, we can go two ways:
>
>  1. Add every extension, including 'bundle' extensions, which are nothing
>  more than an alias for a collection of extensions. This includes single
>  letter bundle extensions like B.
>
>  2. Add only unique extensions, i.e. no purely bundle extensions get
>  added.
>
> If we go with (2), then userspace will need to use the base behaviors
> (profiles) in order to get any sort of bundling, but I think most people
> agree that userspace will target profiles, so (2) seems sufficient. I'm


Looking at existing code, cpufeature.c follows option (2)
for bundle extensions. Zk has no hwprobe bit. The
community settled on this in 2023 [1], and I respect
that decision.

The kernel has two families of bundles today: the Zk
series (Zk, Zkn, Zks) and the Zvk series (Zvkn, Zvknc,
Zvkng, Zvks, Zvksc, Zvksg). All use
__RISCV_ISA_EXT_BUNDLE(). Two things to note:

1) They are all multi-letter extensions.
2) Bundle extensions have no valid ext id, so userspace
cannot query them through hwprobe. To determine
"Zk" support, a user must check all 8 sub-extensions
individually.

B is different.

In your patch and mine, we both define B as a superset,
not a bundle:

+ __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B,
riscv_b_exts),

From a spec perspective, B adds no new functionality
beyond Zba + Zbb + Zbs. The only thing B adds is a misa
bit (m-mode CSR 0x301, not visible to S-mode or U-mode).
So functionally it looks like a bundle.

But can we change B to __RISCV_ISA_EXT_BUNDLE()? I do
not think so. A bundle has id = RISCV_ISA_EXT_INVALID,
which means no bit in the ISA bitmap. The isa2hwcap[]
mapping in riscv_fill_hwcap() requires a valid ext id
to set COMPAT_HWCAP_ISA_B into elf_hwcap. Without it,
AT_HWCAP support for B breaks, and we would need a
special hack. That is unnecessary complexity.

The existing Zk/Zvk bundles work as bundles because they
are multi-letter extensions with no AT_HWCAP presence.
B lives in both worlds.

[1] https://lore.kernel.org/all/20231012-darkness-neutron-fc1843ff05ff@spud/

> not sure about applications that won't target profiles but will want to
> check for bundle extensions rather than individual extensions. Should we
> take on the maintenance burden of adding each bundle extension to hwprobe
> for those? In particular, I'm not sure about B, because it's already
> available independently of a base behavior (profile) through hwcap.
>

In summary, my comments are:

1. F, D, C, and V are detectable from both hwcap and
   hwprobe. B should follow the same pattern. Dropping
   B from hwprobe while keeping it in hwcap creates a
   gap that will confuse users.

2. B is functionally a bundle (the misa B bit at 0x301
   is m-mode only, not visible to S-mode or U-mode),
   yet we declare it as __RISCV_ISA_EXT_SUPERSET()
   because it needs a valid ext id for AT_HWCAP. I
   suggest we document this with a comment in
   cpufeature.c:

+ /*
+  * B is functionally a bundle (Zba + Zbb + Zbs,
+  * no additional instructions). We use SUPERSET
+  * instead of BUNDLE because B needs a valid ext
+  * id for isa2hwcap[] to set COMPAT_HWCAP_ISA_B.
+  */
+   __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),

3. Should we also document in .rst or (in cpufeature.c) about when to use
_BUNDLE() and when to use _SUPERSET(), and what's the implication when
using them, to echo what you stated above "... Add only unique
extensions, i.e. no purely bundle extensions getadded."

BR,
Guodong

> Thanks,
> drew

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Re: [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Guodong Xu]

Hi, Drew

On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> Provide a bit to conveniently determine when RVA23U64 is supported.
> While it's already possible to determine RVA23U64 support with five
> hwprobe calls and four prctl calls it would be error-prone to require
> anything (and we presume eventually almost everything) that needs to
> check for RVA23U64 support to all implement those calls and specific
> checks. And, while RVA23U64 is the IMA base with mandated extensions,
> most software will consider it a new base. For these reasons, add
> the RVA23U64 bit as a base behavior bit.
>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> ---
>  Documentation/arch/riscv/hwprobe.rst          |  8 +++
>  arch/riscv/include/uapi/asm/hwprobe.h         |  3 +-
>  arch/riscv/kernel/sys_hwprobe.c               | 72 +++++++++++++++++++
>  .../selftests/riscv/hwprobe/which-cpus.c      |  2 +-
>  4 files changed, 83 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 97226b7c5936..6d915e7ba58a 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -67,6 +67,14 @@ The following keys are defined:
>        programs (it may still be executed in userspace via a
>        kernel-controlled mechanism such as the vDSO).
>
> +  * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64`: Support for all mandatory
> +    extensions of RVA23U64, as defined in the RISC-V Profiles specification
> +    starting from commit b1d80660 ("Updated to ratified state.")
> +
> +    The RVA23U64 base is based upon the IMA base and therefore IMA extension
> +    keys (e.g. :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`:) may be used to probe
> +    optional extensions.
> +
>  * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
>    that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
>    base system behavior.
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index fed9ea6fd2b5..72d2a4d0b733 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -21,7 +21,8 @@ struct riscv_hwprobe {
>  #define RISCV_HWPROBE_KEY_MARCHID      1
>  #define RISCV_HWPROBE_KEY_MIMPID       2
>  #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR        3
> -#define                RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
> +#define                RISCV_HWPROBE_BASE_BEHAVIOR_IMA         (1 << 0)
> +#define                RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64    (1 << 1)
>  #define RISCV_HWPROBE_KEY_IMA_EXT_0    4
>  #define                RISCV_HWPROBE_IMA_FD            (1 << 0)
>  #define                RISCV_HWPROBE_IMA_C             (1 << 1)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 31d222301bf0..4b9981b15ebe 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -23,6 +23,7 @@
>  #include <asm/vendor_extensions/thead_hwprobe.h>
>  #include <vdso/vsyscall.h>
>
> +extern bool riscv_have_user_pmlen_7;
>
>  #define EXT_KEY(isa_arg, ext, pv, missing)                                     \
>         do {                                                                            \
> @@ -222,6 +223,75 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext)
>         return (pair.value & ext);
>  }
>
> +#define HWPROBE_EXT0_RVA23U64 (                                        \
> +       /* IMA is always supported */                           \
> +       RISCV_HWPROBE_IMA_FD                            |       \
> +       RISCV_HWPROBE_IMA_C                             |       \
> +       /* B is Zba, Zbb and Zbs */                             \
> +       RISCV_HWPROBE_EXT_ZBA                           |       \
> +       RISCV_HWPROBE_EXT_ZBB                           |       \
> +       RISCV_HWPROBE_EXT_ZBS                           |       \
> +       /* ZICSR is always supported */                         \

About Zicsr always?
It is not rigorous compared to the other extensions that are checked
explicitly.

With the deprecated 'riscv,isa' DT string (ACPI doesn't do this),
"i" implies zicsr (along with zicntr, zifencei, zihpm). But with
'riscv,isa-extensions', zicsr must be listed explicitly, it is not
automatically derived from "i". (see cputfeature.c)

BTW, this also serves as an example where:
 - RISCV_ISA_EXT_ZICSR exists, (your patch 10 checked it)
 - but no corresponding hwprobe export RISCV_HWPROBE_EXT_ZICSR.

So, as I suggested, it's better we detect rva23u64 as a combination of
RISCV_ISA_EXT_...; instead of using RISCV_HWPROBE_EXT_...

> +       RISCV_HWPROBE_EXT_ZICNTR                        |       \
> +       RISCV_HWPROBE_EXT_ZIHPM                         |       \
> +       /* ZICCIF is in EXT1 */                                 \
> +       /* ZICCRSE is in EXT1 */                                \
> +       /* ZICCAMOA is in EXT1 */                               \
> +       RISCV_HWPROBE_EXT_ZICCLSM                       |       \
> +       /* ZA64RS is in EXT1 */                                 \
> +       RISCV_HWPROBE_EXT_ZIHINTPAUSE                   |       \
> +       /* ZIC64B (check block sizes are 64b) */                \
> +       RISCV_HWPROBE_EXT_ZICBOM                        |       \
> +       RISCV_HWPROBE_EXT_ZICBOP                        |       \
> +       RISCV_HWPROBE_EXT_ZICBOZ                        |       \
> +       RISCV_HWPROBE_EXT_ZFHMIN                        |       \
> +       RISCV_HWPROBE_EXT_ZKT                           |       \
> +       RISCV_HWPROBE_IMA_V                             |       \
> +       RISCV_HWPROBE_EXT_ZVFHMIN                       |       \
> +       RISCV_HWPROBE_EXT_ZVBB                          |       \
> +       RISCV_HWPROBE_EXT_ZVKT                          |       \
> +       RISCV_HWPROBE_EXT_ZIHINTNTL                     |       \
> +       RISCV_HWPROBE_EXT_ZICOND                        |       \
> +       RISCV_HWPROBE_EXT_ZIMOP                         |       \
> +       RISCV_HWPROBE_EXT_ZCMOP                         |       \
> +       RISCV_HWPROBE_EXT_ZCB                           |       \
> +       RISCV_HWPROBE_EXT_ZFA                           |       \
> +       RISCV_HWPROBE_EXT_ZAWRS                         |       \
> +       RISCV_HWPROBE_EXT_SUPM /* (check PMLEN=7 support) */    \
> +)
> +
> +#define HWPROBE_EXT1_RVA23U64 (                                        \
> +       RISCV_HWPROBE_EXT_ZICCIF                        |       \
> +       RISCV_HWPROBE_EXT_ZICCRSE                       |       \
> +       RISCV_HWPROBE_EXT_ZICCAMOA                      |       \
> +       RISCV_HWPROBE_EXT_ZA64RS                                \
> +)
> +
> +static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
> +{
> +       struct riscv_hwprobe pair;
> +
> +       if (!IS_ENABLED(CONFIG_64BIT))
> +               return false;
> +
> +       /* Additional mandates for Zic64b and Supm */
> +       if (riscv_cbom_block_size != 64 ||
> +           riscv_cbop_block_size != 64 ||
> +           riscv_cboz_block_size != 64 ||
> +           !riscv_have_user_pmlen_7)
> +               return false;
> +
> +       hwprobe_isa_ext0(&pair, cpus);
> +       if ((pair.value & HWPROBE_EXT0_RVA23U64) != HWPROBE_EXT0_RVA23U64)
> +               return false;
> +
> +       hwprobe_isa_ext1(&pair, cpus);
> +       if ((pair.value & HWPROBE_EXT1_RVA23U64) != HWPROBE_EXT1_RVA23U64)
> +               return false;
> +
> +       return true;
> +}

For record purpose, I double checked the above list and function:
all 33 mandatory extensions required by RVA23U64 are checked in this
patch, none missing.

BR,
Guodong

> +
>  #if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
>  static u64 hwprobe_misaligned(const struct cpumask *cpus)
>  {
> @@ -312,6 +382,8 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>          */
>         case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
>                 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
> +               if (hwprobe_has_rva23u64(cpus))
> +                       pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64;
>                 break;
>
>         case RISCV_HWPROBE_KEY_IMA_EXT_0:
> diff --git a/tools/testing/selftests/riscv/hwprobe/which-cpus.c b/tools/testing/selftests/riscv/hwprobe/which-cpus.c
> index 587feb198c04..f8c797b1d0fd 100644
> --- a/tools/testing/selftests/riscv/hwprobe/which-cpus.c
> +++ b/tools/testing/selftests/riscv/hwprobe/which-cpus.c
> @@ -105,7 +105,7 @@ int main(int argc, char **argv)
>         pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR, };
>         rc = riscv_hwprobe(pairs, 1, 0, NULL, 0);
>         assert(rc == 0 && pairs[0].key == RISCV_HWPROBE_KEY_BASE_BEHAVIOR &&
> -              pairs[0].value == RISCV_HWPROBE_BASE_BEHAVIOR_IMA);
> +              (pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA));
>
>         pairs[0] = (struct riscv_hwprobe){ .key = RISCV_HWPROBE_KEY_IMA_EXT_0, };
>         rc = riscv_hwprobe(pairs, 1, 0, NULL, 0);
> --
> 2.43.0
>

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Re: [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Guodong Xu]

On Wed, Feb 25, 2026 at 8:03 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> On Sat, Feb 21, 2026 at 06:51:25PM +0800, Guodong Xu wrote:
> > Hi, Drew
> >
> > On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> > <andrew.jones@oss.qualcomm.com> wrote:
> > >
> > > Provide a bit to conveniently determine when RVA23U64 is supported.
> > > While it's already possible to determine RVA23U64 support with five
> > > hwprobe calls and four prctl calls it would be error-prone to require
> > > anything (and we presume eventually almost everything) that needs to
> > > check for RVA23U64 support to all implement those calls and specific
> > > checks. And, while RVA23U64 is the IMA base with mandated extensions,
> > > most software will consider it a new base. For these reasons, add
> > > the RVA23U64 bit as a base behavior bit.
> > >
> > > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > > ---
> > >
> > > +#define HWPROBE_EXT0_RVA23U64 (                                        \
> > > +       /* IMA is always supported */                           \
> > > +       RISCV_HWPROBE_IMA_FD                            |       \
> > > +       RISCV_HWPROBE_IMA_C                             |       \
> > > +       /* B is Zba, Zbb and Zbs */                             \
> > > +       RISCV_HWPROBE_EXT_ZBA                           |       \
> > > +       RISCV_HWPROBE_EXT_ZBB                           |       \
> > > +       RISCV_HWPROBE_EXT_ZBS                           |       \
> > > +       /* ZICSR is always supported */                         \
> > > +       RISCV_HWPROBE_EXT_ZICNTR                        |       \
> > > +       RISCV_HWPROBE_EXT_ZIHPM                         |       \
> > > +       /* ZICCIF is in EXT1 */                                 \
> > > +       /* ZICCRSE is in EXT1 */                                \
> > > +       /* ZICCAMOA is in EXT1 */                               \
> > > +       RISCV_HWPROBE_EXT_ZICCLSM                       |       \
> > > +       /* ZA64RS is in EXT1 */                                 \
> > > +       RISCV_HWPROBE_EXT_ZIHINTPAUSE                   |       \
> > > +       /* ZIC64B (check block sizes are 64b) */                \
> > > +       RISCV_HWPROBE_EXT_ZICBOM                        |       \
> > > +       RISCV_HWPROBE_EXT_ZICBOP                        |       \
> > > +       RISCV_HWPROBE_EXT_ZICBOZ                        |       \
> > > +       RISCV_HWPROBE_EXT_ZFHMIN                        |       \
> > > +       RISCV_HWPROBE_EXT_ZKT                           |       \
> > > +       RISCV_HWPROBE_IMA_V                             |       \
> > > +       RISCV_HWPROBE_EXT_ZVFHMIN                       |       \
> > > +       RISCV_HWPROBE_EXT_ZVBB                          |       \
> > > +       RISCV_HWPROBE_EXT_ZVKT                          |       \
> > > +       RISCV_HWPROBE_EXT_ZIHINTNTL                     |       \
> > > +       RISCV_HWPROBE_EXT_ZICOND                        |       \
> > > +       RISCV_HWPROBE_EXT_ZIMOP                         |       \
> > > +       RISCV_HWPROBE_EXT_ZCMOP                         |       \
> > > +       RISCV_HWPROBE_EXT_ZCB                           |       \
> > > +       RISCV_HWPROBE_EXT_ZFA                           |       \
> > > +       RISCV_HWPROBE_EXT_ZAWRS                         |       \
> > > +       RISCV_HWPROBE_EXT_SUPM /* (check PMLEN=7 support) */    \
> > > +)
> > > +
> > > +#define HWPROBE_EXT1_RVA23U64 (                                        \
> > > +       RISCV_HWPROBE_EXT_ZICCIF                        |       \
> > > +       RISCV_HWPROBE_EXT_ZICCRSE                       |       \
> > > +       RISCV_HWPROBE_EXT_ZICCAMOA                      |       \
> > > +       RISCV_HWPROBE_EXT_ZA64RS                                \
> > > +)
> > > +
> > > +static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
> > > +{
> > > +       struct riscv_hwprobe pair;
> > > +
> > > +       if (!IS_ENABLED(CONFIG_64BIT))
> > > +               return false;
> > > +
> > > +       /* Additional mandates for Zic64b and Supm */
> > > +       if (riscv_cbom_block_size != 64 ||
> > > +           riscv_cbop_block_size != 64 ||
> > > +           riscv_cboz_block_size != 64 ||
> > > +           !riscv_have_user_pmlen_7)
> > > +               return false;
> > > +
> > > +       hwprobe_isa_ext0(&pair, cpus);
> > > +       if ((pair.value & HWPROBE_EXT0_RVA23U64) != HWPROBE_EXT0_RVA23U64)
> > > +               return false;
> > > +
> > > +       hwprobe_isa_ext1(&pair, cpus);
> > > +       if ((pair.value & HWPROBE_EXT1_RVA23U64) != HWPROBE_EXT1_RVA23U64)
> > > +               return false;
> > > +
> > > +       return true;
> > > +}
> > > +
> > >  #if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
> > >  static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > >  {
> > > @@ -312,6 +382,8 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> > >          */
> > >         case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
> > >                 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
> > > +               if (hwprobe_has_rva23u64(cpus))
> > > +                       pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64;
> >
> > There are two separate implementations of RVA23U64 detection in
> > your patchset:
> > 1. In this patch: hwprobe_has_rva23u64(), which checks against
> > RISCV_HWPROBE_EXT_* bits.
> > 2. In [Patch 10/11]: riscv_set_isa_bases(), which checks against
> > RISCV_ISA_EXT_*.
> >
> > I'm not sure I fully understand your reasoning behind this
> > duplication (it's too obvious for me not to doubt myself).
>
> We purposely use hwprobe bits in hwprobe since we want to ensure
> consistency. We use the isa bits everywhere else as that's the
> typical place to check.
>
> > At
> > least for now, I think the hwprobe version is not good from an
> > architecture viewpoint.
> >
> > My logic is this: RVA23U64 is a hardware implementation feature.
> > It exists no matter whether you export its sub-components (those
> > mandatory extensions required by RVA23 Profile) through hwprobe or
> > not. Profile conformance vs. per-extension export should stay
> > independent.
> >
> > DT/ACPI -> RISCV_ISA_EXT_*: these are ground truth.
> > RISCV_HWPROBE_EXT_*: these are a filtered subset.
> >
> > We shouldn't be pushed to export (hwprobe) an extension just
> > to make the RVA23U64 calculation correct. The criteria for
> > exporting an extension through hwprobe should be based on
> > whether there is a userspace consumer who needs it
> > individually.
>
> I agree with the "only publish stuff in hwprobe that users care about"
> approach and we do have precedent for not publishing extensions covered
> by the base already (I, M, and A are not individually in hwprobe --
> although they are in hwcap).
>
> For this series I could drop any extensions that people are unlikely to

I am not sure I understand you correctly. If any of the HWPROBE_EXT_ id
is dropped, that will make your check in hwprobe_has_rva23u64() fail.

And that will cause a mismatch, where /proc/cpuinfo (ie.
riscv_set_isa_bases()) reports 'rva23u64', but hwprobe reports
no 'rva23u64'.

Is that what you intend, or do you mean something different?

> care about individually from hwprobe. Anyway, they can always be added

In my patchset [1] cover letter, I explained that I prefer not to export
via hwprobe Za64rs and Ziccamoa. Because, unlike others such as Zicclsm
and Ziccif,  I didn't see any user space usage of Za64rs and Ziccamoa.

But again, removing them from hwprobe will cause a rva23u64 report
mismatch.

[1]: https://lore.kernel.org/all/20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com/
BR,
Guodong

> later when needed. I was fond of my hwprobe consistency selftest though...
>
> Thanks,
> drew

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Re: [RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output

[Guodong Xu]

On Wed, Feb 25, 2026 at 8:08 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> On Sat, Feb 21, 2026 at 06:52:19PM +0800, Guodong Xu wrote:
> > On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> > <andrew.jones@oss.qualcomm.com> wrote:
> > >
> > > Output the rva23(u|s)64 ISA bases that the ISA extensions provide on
> > > new 'isa bases' lines both for the LCD of all harts and per hart, as
> > > shown in the example output below when booting qemu with
> > > -cpu rva23s64,sv39=on,pmp=on:
> > >
> > > processor       : 0
> > > hart            : 4
> > > isa bases       : rv64ima rva23u64
> > > isa             : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> > > mmu             : sv39
> > > mvendorid       : 0x0
> > > marchid         : 0x0
> > > mimpid          : 0x0
> > > hart isa bases  : rv64ima rva23u64
> > > hart isa        : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> > >
> > > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > > ---
> > > +       /* RVA23S64 */
> > > +       set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
> > > +       /* TODO: Ss1p13 */
> > > +       /* Svbare, Sv39 -- assumed */
> > > +       set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
> > > +       /* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */
> >
> > For this,
> >
> > > +       set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
> > > +       set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
> > > +       set_bit(RISCV_ISA_EXT_SVNAPOT, ext_mask);
> > > +       set_bit(RISCV_ISA_EXT_SSTC, ext_mask);
> > > +       set_bit(RISCV_ISA_EXT_SSCOFPMF, ext_mask);
> > > +       set_bit(RISCV_ISA_EXT_SSNPM, ext_mask);
> > > +       /* TODO: Ssu64xl */
> > > +       /* TODO: Sha = Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa */

Hi, drew

About 'Sha', your reading of the profile/spec, do you prefer to define
Sha as a _BUNDLE or as a _SUPERSET() which has its own id?

I defined it as _SUPERSET() in my patch 8/8 [1], but with today's code
review, I guess bundle is a better fit. What do you think?

BTW, Sha = H + 7 others. It includes H.

BR,
Guodong

> >
> > And this, these TODOs, I'd be happy if my patches 7 and 8 [1] can be
> > useful here.
> >
> > Link: https://lore.kernel.org/all/20260207-isa-ext-parse-export-v1-7-a64d3a8bc20a@riscstar.com/
> > [1]
>
> Absolutely!
>
> Thanks,
> drew

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Re: [RFC PATCH v1 04/11] riscv: Add B to hwcap

[Andrew Jones]

On Fri, Mar 06, 2026 at 10:17:19AM +0800, Guodong Xu wrote:
> On Wed, Feb 25, 2026 at 7:05 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > On Sat, Feb 21, 2026 at 06:49:18PM +0800, Guodong Xu wrote:
> > > Hi, Drew
> > >
> > > On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> > > <andrew.jones@oss.qualcomm.com> wrote:
> > > >
> > > > Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs
> > > > are all set.
> > > >
> > > > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > > > ---
> > > >  arch/riscv/include/asm/hwcap.h      | 1 +
> > > >  arch/riscv/include/uapi/asm/hwcap.h | 1 +
> > > >  arch/riscv/kernel/cpufeature.c      | 8 ++++++++
> > > >  3 files changed, 10 insertions(+)
> > >
> > > I saw you chose not to add B to hwprobe in this series, per
> > > your review of my patch [1]. I have a different opinion.
> > >
> > > As you said, FD, C, and V are all exported through both hwcap
> > > and hwprobe. Adding B to hwprobe too keeps things consistent,
> > > users can query all the single-letter extensions from one
> > > interface without needing to know that B is missing in hwprobe
> > > and that they'd have to check Zba/Zbb/Zbs to infer B support.
> > >
> > > Relying on the rva23u64 base bit to imply B also doesn't cover
> > > chips that implement B without being rva23u64 compliant. Eg. my
> > > patchset [2] adds support for existing (non-rva23u64) SoCs.
> > >
> >
> > I think we need to come up with some sort of policy as to what goes to
> > hwprobe and what doesn't. IMO, hwcap is easy. If RISC-V defines a single
> > letter extension, such as V or B, then we should add it to hwcap. However,
> 
> When we export an extension through hwcap but it cannot
> be queried through hwprobe, we create an inconsistency:
> the same extension is discoverable through one interface
> but not the other.
> 
> The current kernel already exposes other single-letter
> extensions through both interfaces:
> 
>   F+D: RISCV_HWPROBE_IMA_FD + COMPAT_HWCAP_ISA_F/_D
>   C:   RISCV_HWPROBE_IMA_C  + COMPAT_HWCAP_ISA_C
>   V:   RISCV_HWPROBE_IMA_V  + COMPAT_HWCAP_ISA_V
> 
> (I/M/A are folded into RISCV_HWPROBE_BASE_BEHAVIOR_IMA,
> so they are a separate case.)
> 
> F, D, C, and V are consistent between hwcap and hwprobe.
> Why should B be different?

Ok, you've sold me. The obvious advantage to applications is that they
don't need to know anything about hwcap at all. hwprobe can be a one-
stop shop.

> 
> > for hwprobe, we can go two ways:
> >
> >  1. Add every extension, including 'bundle' extensions, which are nothing
> >  more than an alias for a collection of extensions. This includes single
> >  letter bundle extensions like B.
> >
> >  2. Add only unique extensions, i.e. no purely bundle extensions get
> >  added.
> >
> > If we go with (2), then userspace will need to use the base behaviors
> > (profiles) in order to get any sort of bundling, but I think most people
> > agree that userspace will target profiles, so (2) seems sufficient. I'm
> 
> 
> Looking at existing code, cpufeature.c follows option (2)
> for bundle extensions. Zk has no hwprobe bit. The
> community settled on this in 2023 [1], and I respect
> that decision.
> 
> The kernel has two families of bundles today: the Zk
> series (Zk, Zkn, Zks) and the Zvk series (Zvkn, Zvknc,
> Zvkng, Zvks, Zvksc, Zvksg). All use
> __RISCV_ISA_EXT_BUNDLE(). Two things to note:
> 
> 1) They are all multi-letter extensions.
> 2) Bundle extensions have no valid ext id, so userspace
> cannot query them through hwprobe. To determine
> "Zk" support, a user must check all 8 sub-extensions
> individually.
> 
> B is different.
> 
> In your patch and mine, we both define B as a superset,
> not a bundle:
> 
> + __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B,
> riscv_b_exts),
> 
> From a spec perspective, B adds no new functionality
> beyond Zba + Zbb + Zbs. The only thing B adds is a misa
> bit (m-mode CSR 0x301, not visible to S-mode or U-mode).
> So functionally it looks like a bundle.
> 
> But can we change B to __RISCV_ISA_EXT_BUNDLE()? I do
> not think so. A bundle has id = RISCV_ISA_EXT_INVALID,
> which means no bit in the ISA bitmap. The isa2hwcap[]
> mapping in riscv_fill_hwcap() requires a valid ext id
> to set COMPAT_HWCAP_ISA_B into elf_hwcap. Without it,
> AT_HWCAP support for B breaks, and we would need a
> special hack. That is unnecessary complexity.
> 
> The existing Zk/Zvk bundles work as bundles because they
> are multi-letter extensions with no AT_HWCAP presence.
> B lives in both worlds.
> 
> [1] https://lore.kernel.org/all/20231012-darkness-neutron-fc1843ff05ff@spud/
> 
> > not sure about applications that won't target profiles but will want to
> > check for bundle extensions rather than individual extensions. Should we
> > take on the maintenance burden of adding each bundle extension to hwprobe
> > for those? In particular, I'm not sure about B, because it's already
> > available independently of a base behavior (profile) through hwcap.
> >
> 
> In summary, my comments are:
> 
> 1. F, D, C, and V are detectable from both hwcap and
>    hwprobe. B should follow the same pattern. Dropping
>    B from hwprobe while keeping it in hwcap creates a
>    gap that will confuse users.
> 
> 2. B is functionally a bundle (the misa B bit at 0x301
>    is m-mode only, not visible to S-mode or U-mode),
>    yet we declare it as __RISCV_ISA_EXT_SUPERSET()
>    because it needs a valid ext id for AT_HWCAP. I
>    suggest we document this with a comment in
>    cpufeature.c:
> 
> + /*
> +  * B is functionally a bundle (Zba + Zbb + Zbs,
> +  * no additional instructions). We use SUPERSET
> +  * instead of BUNDLE because B needs a valid ext
> +  * id for isa2hwcap[] to set COMPAT_HWCAP_ISA_B.
> +  */
> +   __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),

Looks good.

> 
> 3. Should we also document in .rst or (in cpufeature.c) about when to use
> _BUNDLE() and when to use _SUPERSET(), and what's the implication when
> using them, to echo what you stated above "... Add only unique
> extensions, i.e. no purely bundle extensions getadded."

We're probably OK with the comments already in cpufeature.h

/* Used to declare pure "lasso" extension (Zk for instance) */
BUNDLE...
/* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
SUPERSET...

And your proposed comment above B will also help explain things.

Thanks,
drew

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Re: [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Andrew Jones]

On Fri, Mar 06, 2026 at 08:29:24PM +0800, Guodong Xu wrote:
> On Wed, Feb 25, 2026 at 8:03 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > On Sat, Feb 21, 2026 at 06:51:25PM +0800, Guodong Xu wrote:
> > > Hi, Drew
> > >
> > > On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> > > <andrew.jones@oss.qualcomm.com> wrote:
> > > >
> > > > Provide a bit to conveniently determine when RVA23U64 is supported.
> > > > While it's already possible to determine RVA23U64 support with five
> > > > hwprobe calls and four prctl calls it would be error-prone to require
> > > > anything (and we presume eventually almost everything) that needs to
> > > > check for RVA23U64 support to all implement those calls and specific
> > > > checks. And, while RVA23U64 is the IMA base with mandated extensions,
> > > > most software will consider it a new base. For these reasons, add
> > > > the RVA23U64 bit as a base behavior bit.
> > > >
> > > > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > > > ---
> > > >
> > > > +#define HWPROBE_EXT0_RVA23U64 (                                        \
> > > > +       /* IMA is always supported */                           \
> > > > +       RISCV_HWPROBE_IMA_FD                            |       \
> > > > +       RISCV_HWPROBE_IMA_C                             |       \
> > > > +       /* B is Zba, Zbb and Zbs */                             \
> > > > +       RISCV_HWPROBE_EXT_ZBA                           |       \
> > > > +       RISCV_HWPROBE_EXT_ZBB                           |       \
> > > > +       RISCV_HWPROBE_EXT_ZBS                           |       \
> > > > +       /* ZICSR is always supported */                         \
> > > > +       RISCV_HWPROBE_EXT_ZICNTR                        |       \
> > > > +       RISCV_HWPROBE_EXT_ZIHPM                         |       \
> > > > +       /* ZICCIF is in EXT1 */                                 \
> > > > +       /* ZICCRSE is in EXT1 */                                \
> > > > +       /* ZICCAMOA is in EXT1 */                               \
> > > > +       RISCV_HWPROBE_EXT_ZICCLSM                       |       \
> > > > +       /* ZA64RS is in EXT1 */                                 \
> > > > +       RISCV_HWPROBE_EXT_ZIHINTPAUSE                   |       \
> > > > +       /* ZIC64B (check block sizes are 64b) */                \
> > > > +       RISCV_HWPROBE_EXT_ZICBOM                        |       \
> > > > +       RISCV_HWPROBE_EXT_ZICBOP                        |       \
> > > > +       RISCV_HWPROBE_EXT_ZICBOZ                        |       \
> > > > +       RISCV_HWPROBE_EXT_ZFHMIN                        |       \
> > > > +       RISCV_HWPROBE_EXT_ZKT                           |       \
> > > > +       RISCV_HWPROBE_IMA_V                             |       \
> > > > +       RISCV_HWPROBE_EXT_ZVFHMIN                       |       \
> > > > +       RISCV_HWPROBE_EXT_ZVBB                          |       \
> > > > +       RISCV_HWPROBE_EXT_ZVKT                          |       \
> > > > +       RISCV_HWPROBE_EXT_ZIHINTNTL                     |       \
> > > > +       RISCV_HWPROBE_EXT_ZICOND                        |       \
> > > > +       RISCV_HWPROBE_EXT_ZIMOP                         |       \
> > > > +       RISCV_HWPROBE_EXT_ZCMOP                         |       \
> > > > +       RISCV_HWPROBE_EXT_ZCB                           |       \
> > > > +       RISCV_HWPROBE_EXT_ZFA                           |       \
> > > > +       RISCV_HWPROBE_EXT_ZAWRS                         |       \
> > > > +       RISCV_HWPROBE_EXT_SUPM /* (check PMLEN=7 support) */    \
> > > > +)
> > > > +
> > > > +#define HWPROBE_EXT1_RVA23U64 (                                        \
> > > > +       RISCV_HWPROBE_EXT_ZICCIF                        |       \
> > > > +       RISCV_HWPROBE_EXT_ZICCRSE                       |       \
> > > > +       RISCV_HWPROBE_EXT_ZICCAMOA                      |       \
> > > > +       RISCV_HWPROBE_EXT_ZA64RS                                \
> > > > +)
> > > > +
> > > > +static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
> > > > +{
> > > > +       struct riscv_hwprobe pair;
> > > > +
> > > > +       if (!IS_ENABLED(CONFIG_64BIT))
> > > > +               return false;
> > > > +
> > > > +       /* Additional mandates for Zic64b and Supm */
> > > > +       if (riscv_cbom_block_size != 64 ||
> > > > +           riscv_cbop_block_size != 64 ||
> > > > +           riscv_cboz_block_size != 64 ||
> > > > +           !riscv_have_user_pmlen_7)
> > > > +               return false;
> > > > +
> > > > +       hwprobe_isa_ext0(&pair, cpus);
> > > > +       if ((pair.value & HWPROBE_EXT0_RVA23U64) != HWPROBE_EXT0_RVA23U64)
> > > > +               return false;
> > > > +
> > > > +       hwprobe_isa_ext1(&pair, cpus);
> > > > +       if ((pair.value & HWPROBE_EXT1_RVA23U64) != HWPROBE_EXT1_RVA23U64)
> > > > +               return false;
> > > > +
> > > > +       return true;
> > > > +}
> > > > +
> > > >  #if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
> > > >  static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > > >  {
> > > > @@ -312,6 +382,8 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> > > >          */
> > > >         case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
> > > >                 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
> > > > +               if (hwprobe_has_rva23u64(cpus))
> > > > +                       pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64;
> > >
> > > There are two separate implementations of RVA23U64 detection in
> > > your patchset:
> > > 1. In this patch: hwprobe_has_rva23u64(), which checks against
> > > RISCV_HWPROBE_EXT_* bits.
> > > 2. In [Patch 10/11]: riscv_set_isa_bases(), which checks against
> > > RISCV_ISA_EXT_*.
> > >
> > > I'm not sure I fully understand your reasoning behind this
> > > duplication (it's too obvious for me not to doubt myself).
> >
> > We purposely use hwprobe bits in hwprobe since we want to ensure
> > consistency. We use the isa bits everywhere else as that's the
> > typical place to check.
> >
> > > At
> > > least for now, I think the hwprobe version is not good from an
> > > architecture viewpoint.
> > >
> > > My logic is this: RVA23U64 is a hardware implementation feature.
> > > It exists no matter whether you export its sub-components (those
> > > mandatory extensions required by RVA23 Profile) through hwprobe or
> > > not. Profile conformance vs. per-extension export should stay
> > > independent.
> > >
> > > DT/ACPI -> RISCV_ISA_EXT_*: these are ground truth.
> > > RISCV_HWPROBE_EXT_*: these are a filtered subset.
> > >
> > > We shouldn't be pushed to export (hwprobe) an extension just
> > > to make the RVA23U64 calculation correct. The criteria for
> > > exporting an extension through hwprobe should be based on
> > > whether there is a userspace consumer who needs it
> > > individually.
> >
> > I agree with the "only publish stuff in hwprobe that users care about"
> > approach and we do have precedent for not publishing extensions covered
> > by the base already (I, M, and A are not individually in hwprobe --
> > although they are in hwcap).
> >
> > For this series I could drop any extensions that people are unlikely to
> 
> I am not sure I understand you correctly. If any of the HWPROBE_EXT_ id
> is dropped, that will make your check in hwprobe_has_rva23u64() fail.
> 
> And that will cause a mismatch, where /proc/cpuinfo (ie.
> riscv_set_isa_bases()) reports 'rva23u64', but hwprobe reports
> no 'rva23u64'.
> 
> Is that what you intend, or do you mean something different?

The implementation of hwprobe_has_rva23u64() would have to change and all
my consistency stuff, including the selftest, would be dropped.

Thanks,
drew

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Re: [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior

[Andrew Jones]

On Fri, Mar 06, 2026 at 08:08:38PM +0800, Guodong Xu wrote:
> Hi, Drew
> 
> On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > Provide a bit to conveniently determine when RVA23U64 is supported.
> > While it's already possible to determine RVA23U64 support with five
> > hwprobe calls and four prctl calls it would be error-prone to require
> > anything (and we presume eventually almost everything) that needs to
> > check for RVA23U64 support to all implement those calls and specific
> > checks. And, while RVA23U64 is the IMA base with mandated extensions,
> > most software will consider it a new base. For these reasons, add
> > the RVA23U64 bit as a base behavior bit.
> >
> > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > ---
> >  Documentation/arch/riscv/hwprobe.rst          |  8 +++
> >  arch/riscv/include/uapi/asm/hwprobe.h         |  3 +-
> >  arch/riscv/kernel/sys_hwprobe.c               | 72 +++++++++++++++++++
> >  .../selftests/riscv/hwprobe/which-cpus.c      |  2 +-
> >  4 files changed, 83 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index 97226b7c5936..6d915e7ba58a 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -67,6 +67,14 @@ The following keys are defined:
> >        programs (it may still be executed in userspace via a
> >        kernel-controlled mechanism such as the vDSO).
> >
> > +  * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64`: Support for all mandatory
> > +    extensions of RVA23U64, as defined in the RISC-V Profiles specification
> > +    starting from commit b1d80660 ("Updated to ratified state.")
> > +
> > +    The RVA23U64 base is based upon the IMA base and therefore IMA extension
> > +    keys (e.g. :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`:) may be used to probe
> > +    optional extensions.
> > +
> >  * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
> >    that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
> >    base system behavior.
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index fed9ea6fd2b5..72d2a4d0b733 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -21,7 +21,8 @@ struct riscv_hwprobe {
> >  #define RISCV_HWPROBE_KEY_MARCHID      1
> >  #define RISCV_HWPROBE_KEY_MIMPID       2
> >  #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR        3
> > -#define                RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
> > +#define                RISCV_HWPROBE_BASE_BEHAVIOR_IMA         (1 << 0)
> > +#define                RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64    (1 << 1)
> >  #define RISCV_HWPROBE_KEY_IMA_EXT_0    4
> >  #define                RISCV_HWPROBE_IMA_FD            (1 << 0)
> >  #define                RISCV_HWPROBE_IMA_C             (1 << 1)
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index 31d222301bf0..4b9981b15ebe 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -23,6 +23,7 @@
> >  #include <asm/vendor_extensions/thead_hwprobe.h>
> >  #include <vdso/vsyscall.h>
> >
> > +extern bool riscv_have_user_pmlen_7;
> >
> >  #define EXT_KEY(isa_arg, ext, pv, missing)                                     \
> >         do {                                                                            \
> > @@ -222,6 +223,75 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext)
> >         return (pair.value & ext);
> >  }
> >
> > +#define HWPROBE_EXT0_RVA23U64 (                                        \
> > +       /* IMA is always supported */                           \
> > +       RISCV_HWPROBE_IMA_FD                            |       \
> > +       RISCV_HWPROBE_IMA_C                             |       \
> > +       /* B is Zba, Zbb and Zbs */                             \
> > +       RISCV_HWPROBE_EXT_ZBA                           |       \
> > +       RISCV_HWPROBE_EXT_ZBB                           |       \
> > +       RISCV_HWPROBE_EXT_ZBS                           |       \
> > +       /* ZICSR is always supported */                         \
> 
> About Zicsr always?
> It is not rigorous compared to the other extensions that are checked
> explicitly.
> 
> With the deprecated 'riscv,isa' DT string (ACPI doesn't do this),
> "i" implies zicsr (along with zicntr, zifencei, zihpm). But with
> 'riscv,isa-extensions', zicsr must be listed explicitly, it is not
> automatically derived from "i". (see cputfeature.c)
> 
> BTW, this also serves as an example where:
>  - RISCV_ISA_EXT_ZICSR exists, (your patch 10 checked it)
>  - but no corresponding hwprobe export RISCV_HWPROBE_EXT_ZICSR.
> 
> So, as I suggested, it's better we detect rva23u64 as a combination of
> RISCV_ISA_EXT_...; instead of using RISCV_HWPROBE_EXT_...

Indeed, zicsr makes a good case for that.

> 
> > +       RISCV_HWPROBE_EXT_ZICNTR                        |       \
> > +       RISCV_HWPROBE_EXT_ZIHPM                         |       \
> > +       /* ZICCIF is in EXT1 */                                 \
> > +       /* ZICCRSE is in EXT1 */                                \
> > +       /* ZICCAMOA is in EXT1 */                               \
> > +       RISCV_HWPROBE_EXT_ZICCLSM                       |       \
> > +       /* ZA64RS is in EXT1 */                                 \
> > +       RISCV_HWPROBE_EXT_ZIHINTPAUSE                   |       \
> > +       /* ZIC64B (check block sizes are 64b) */                \
> > +       RISCV_HWPROBE_EXT_ZICBOM                        |       \
> > +       RISCV_HWPROBE_EXT_ZICBOP                        |       \
> > +       RISCV_HWPROBE_EXT_ZICBOZ                        |       \
> > +       RISCV_HWPROBE_EXT_ZFHMIN                        |       \
> > +       RISCV_HWPROBE_EXT_ZKT                           |       \
> > +       RISCV_HWPROBE_IMA_V                             |       \
> > +       RISCV_HWPROBE_EXT_ZVFHMIN                       |       \
> > +       RISCV_HWPROBE_EXT_ZVBB                          |       \
> > +       RISCV_HWPROBE_EXT_ZVKT                          |       \
> > +       RISCV_HWPROBE_EXT_ZIHINTNTL                     |       \
> > +       RISCV_HWPROBE_EXT_ZICOND                        |       \
> > +       RISCV_HWPROBE_EXT_ZIMOP                         |       \
> > +       RISCV_HWPROBE_EXT_ZCMOP                         |       \
> > +       RISCV_HWPROBE_EXT_ZCB                           |       \
> > +       RISCV_HWPROBE_EXT_ZFA                           |       \
> > +       RISCV_HWPROBE_EXT_ZAWRS                         |       \
> > +       RISCV_HWPROBE_EXT_SUPM /* (check PMLEN=7 support) */    \
> > +)
> > +
> > +#define HWPROBE_EXT1_RVA23U64 (                                        \
> > +       RISCV_HWPROBE_EXT_ZICCIF                        |       \
> > +       RISCV_HWPROBE_EXT_ZICCRSE                       |       \
> > +       RISCV_HWPROBE_EXT_ZICCAMOA                      |       \
> > +       RISCV_HWPROBE_EXT_ZA64RS                                \
> > +)
> > +
> > +static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
> > +{
> > +       struct riscv_hwprobe pair;
> > +
> > +       if (!IS_ENABLED(CONFIG_64BIT))
> > +               return false;
> > +
> > +       /* Additional mandates for Zic64b and Supm */
> > +       if (riscv_cbom_block_size != 64 ||
> > +           riscv_cbop_block_size != 64 ||
> > +           riscv_cboz_block_size != 64 ||
> > +           !riscv_have_user_pmlen_7)
> > +               return false;
> > +
> > +       hwprobe_isa_ext0(&pair, cpus);
> > +       if ((pair.value & HWPROBE_EXT0_RVA23U64) != HWPROBE_EXT0_RVA23U64)
> > +               return false;
> > +
> > +       hwprobe_isa_ext1(&pair, cpus);
> > +       if ((pair.value & HWPROBE_EXT1_RVA23U64) != HWPROBE_EXT1_RVA23U64)
> > +               return false;
> > +
> > +       return true;
> > +}
> 
> For record purpose, I double checked the above list and function:
> all 33 mandatory extensions required by RVA23U64 are checked in this
> patch, none missing.

Thanks!
drew

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Re: [RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output

[Andrew Jones]

On Fri, Mar 06, 2026 at 08:47:42PM +0800, Guodong Xu wrote:
> On Wed, Feb 25, 2026 at 8:08 AM Andrew Jones
> <andrew.jones@oss.qualcomm.com> wrote:
> >
> > On Sat, Feb 21, 2026 at 06:52:19PM +0800, Guodong Xu wrote:
> > > On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> > > <andrew.jones@oss.qualcomm.com> wrote:
> > > >
> > > > Output the rva23(u|s)64 ISA bases that the ISA extensions provide on
> > > > new 'isa bases' lines both for the LCD of all harts and per hart, as
> > > > shown in the example output below when booting qemu with
> > > > -cpu rva23s64,sv39=on,pmp=on:
> > > >
> > > > processor       : 0
> > > > hart            : 4
> > > > isa bases       : rv64ima rva23u64
> > > > isa             : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> > > > mmu             : sv39
> > > > mvendorid       : 0x0
> > > > marchid         : 0x0
> > > > mimpid          : 0x0
> > > > hart isa bases  : rv64ima rva23u64
> > > > hart isa        : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> > > >
> > > > Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> > > > ---
> > > > +       /* RVA23S64 */
> > > > +       set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
> > > > +       /* TODO: Ss1p13 */
> > > > +       /* Svbare, Sv39 -- assumed */
> > > > +       set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
> > > > +       /* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */
> > >
> > > For this,
> > >
> > > > +       set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SVNAPOT, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SSTC, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SSCOFPMF, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SSNPM, ext_mask);
> > > > +       /* TODO: Ssu64xl */
> > > > +       /* TODO: Sha = Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa */
> 
> Hi, drew
> 
> About 'Sha', your reading of the profile/spec, do you prefer to define
> Sha as a _BUNDLE or as a _SUPERSET() which has its own id?
> 
> I defined it as _SUPERSET() in my patch 8/8 [1], but with today's code
> review, I guess bundle is a better fit. What do you think?
> 
> BTW, Sha = H + 7 others. It includes H.

I agree a bundle is more suitable for Sha.

Thanks,
drew

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Re: [RFC PATCH v1 04/11] riscv: Add B to hwcap

[Conor Dooley]

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On Fri, Mar 06, 2026 at 12:27:50PM -0600, Andrew Jones wrote:
> On Fri, Mar 06, 2026 at 10:17:19AM +0800, Guodong Xu wrote:

> > + /*
> > +  * B is functionally a bundle (Zba + Zbb + Zbs,
> > +  * no additional instructions). We use SUPERSET
> > +  * instead of BUNDLE because B needs a valid ext
> > +  * id for isa2hwcap[] to set COMPAT_HWCAP_ISA_B.

What's the actual rationale for it working like that?
Why shouldn't bundles appear in cpuinfo etc, I forget entirely why we
did it this way. Feels like it'd be easier for users, no?

2023 me might disagree, but 2026 me doesn't see the value in hiding these
extensions. All I can think of was me being very negative, and hedging
against bad software checking for zkn and not checking for the subsets,
and breaking if the dt listed the entire subset but not zkn. That, or
not wanting to implement code that looked for subset extensions and
populated the relevant bundle if the bundle itself was missing but all
components were there.

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Re: [RFC PATCH v1 04/11] riscv: Add B to hwcap

[Andrew Jones]

On Fri, Mar 06, 2026 at 06:50:20PM +0000, Conor Dooley wrote:
> On Fri, Mar 06, 2026 at 12:27:50PM -0600, Andrew Jones wrote:
> > On Fri, Mar 06, 2026 at 10:17:19AM +0800, Guodong Xu wrote:
> 
> > > + /*
> > > +  * B is functionally a bundle (Zba + Zbb + Zbs,
> > > +  * no additional instructions). We use SUPERSET
> > > +  * instead of BUNDLE because B needs a valid ext
> > > +  * id for isa2hwcap[] to set COMPAT_HWCAP_ISA_B.
> 
> What's the actual rationale for it working like that?
> Why shouldn't bundles appear in cpuinfo etc, I forget entirely why we
> did it this way. Feels like it'd be easier for users, no?
> 
> 2023 me might disagree, but 2026 me doesn't see the value in hiding these
> extensions. All I can think of was me being very negative, and hedging
> against bad software checking for zkn and not checking for the subsets,
> and breaking if the dt listed the entire subset but not zkn. That, or
> not wanting to implement code that looked for subset extensions and
> populated the relevant bundle if the bundle itself was missing but all
> components were there.

I also can't remember and the 2026 me doesn't want to google 2023 me's
thoughts. I think we may have opted not to publish bundles because we
didn't believe publishing them would help reduce much confusion, as the
concept of a bundle itself was a bit confusing...

Thanks,
drew

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