[PATCH 0/4] ASoC: wm8994/midas_wm1811: fix codec clocking issues

[PATCH 0/4] ASoC: wm8994/midas_wm1811: fix codec clocking issues

[Marek Szyprowski]

Hi All,

This patchset fixes a few issues in the WM8994/WM1811 codec clocking
code, which show up on the Exynos4412 Trats2 board. On that board the
codec AIF1 and SYSCLK run from MCLK2 (the 32768Hz clock provided by the
PMIC) when idle, and from FLL1 (fed by MCLK1, a fixed 24MHz clock) when
a stream is active.

The symptoms are the codec flooding the kernel log with FIFO error
interrupts every 10ms once any digital path is powered up, for example
by the mixer state restored by alsactl, and FLL1 failing to lock:

 wm8994-codec wm8994-codec: Timed out waiting for FLL lock
 wm8994-codec wm8994-codec: FIFO error
 wm8994-codec wm8994-codec: FIFO error
 ...

Both issues disappear when booting with clk_ignore_unused, or after the
WLAN/Bluetooth drivers enable the shared 32kHz clock. This went
unnoticed during the initial Midas audio contribution probably because
the WLAN/Bluetooth drivers kept their clocks enabled that time. Several
bugs contribute to this:

1. aif_mclk_set() never enables MCLK2 for an AIF clocked from it, due
   to a missing shift of the AIFnCLK_SRC field value, so the codec runs
   from a stopped clock until another user enables it.

2. The AIFnCLK rate ratio saved when SYSCLK drops to 32kHz gets
   overwritten on each subsequent clock reconfiguration done in the low
   SYSCLK mode, so AIF1 ends up at 128fs instead of 256fs.

3. wm8994_set_dai_sysclk() passes the AIF index instead of the MCLK
   index to wm8994_set_mclk_rate(), so the rate of MCLK1 is reported for
   MCLK2 and the low SYSCLK handling is skipped.

4. The midas_wm1811 machine driver starts FLL1 at 11.2896MHz when no
   stream is active, while AIF1 keeps the configuration of the last
   stream (or the 48kHz reset default), which needs 12.288MHz.

Patches have been developed with LLM assistance and have been tested on
the real Trats2 board. The built-in speaker as well as headphones jack
provide proper audio now.

Best regards
Marek Szyprowski, PhD
Samsung R&D Institute Poland


Marek Szyprowski (4):
  ASoC: wm8994: fix MCLK gating for AIF clocks sourced from MCLK2
  ASoC: wm8994: don't lose the AIF clock ratio when staying at 32kHz
    SYSCLK
  ASoC: wm8994: fix MCLK index used for setting MCLK rate
  ASoC: samsung: midas_wm1811: run FLL1 at the AIF1 configured rate when
    idle

 sound/soc/codecs/wm8994.c        | 126 +++++++++++++++----------------
 sound/soc/codecs/wm8994.h        |   1 +
 sound/soc/samsung/midas_wm1811.c |  14 +++-
 3 files changed, 71 insertions(+), 70 deletions(-)

-- 
2.43.0

[PATCH 1/4] ASoC: wm8994: fix MCLK gating for AIF clocks sourced from MCLK2

[Marek Szyprowski]

aif_mclk_set() masks the AIFnCLK_SRC field of the AIFn clocking
register, but compares the result with unshifted field values. The
MCLK2 source (0x08) therefore never matches, so MCLK2 is never enabled
for an AIF clocked from it, and the AIF relies on other users of that
clock to keep it running.

On the Exynos4412 Trats2 board, AIF1 and SYSCLK run from MCLK2, the
32768Hz PMIC clock, while the codec is idle. That clock is shared with
the WLAN and Bluetooth chips, which enable it only once their drivers
are loaded. Until then the codec runs from a stopped clock: FLL1 fails
to lock when configured from that state, and the codec floods the
kernel log with FIFO error interrupts once a digital path is powered
up:

 wm8994-codec wm8994-codec: Timed out waiting for FLL lock
 wm8994-codec wm8994-codec: FIFO error

Booting with clk_ignore_unused, which keeps that clock running from
the bootloader, makes both issues disappear.

Fixing just the comparison is not enough. The AIF clock source can
be changed while the AIF clock is running, for example the Midas
machine driver switches AIF1 between MCLK2 and FLL1 while AIF1CLK is
kept enabled for jack detection. Looking up the clock again on disable
can then release a different MCLK than the one enabled, leaking the
enable count of one clock and underflowing the other.

Shift the field value before decoding it, and remember which MCLK has
been enabled for each AIF, so that the same clock is released on
disable. While at it, report the MCLK number 1-based in the error
message.

Fixes: 001b83d395ab ("ASoC: wm8994: Add support for MCLKn clock gating")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 sound/soc/codecs/wm8994.c | 28 ++++++++++++++++++----------
 sound/soc/codecs/wm8994.h |  1 +
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index c65a7769a9d2..e21adcaf3477 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -1059,13 +1059,24 @@ static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enabl
 	unsigned int offset, val, clk_idx;
 	int ret;
 
+	/*
+	 * The AIF clock source may be changed while the AIF clock is
+	 * running, so release the MCLK which has been enabled for it
+	 * instead of the one currently selected.
+	 */
+	if (!enable) {
+		clk_disable_unprepare(wm8994->aif_mclk[aif]);
+		wm8994->aif_mclk[aif] = NULL;
+		return 0;
+	}
+
 	if (aif)
 		offset = 4;
 	else
 		offset = 0;
 
 	val = snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1 + offset);
-	val &= WM8994_AIF1CLK_SRC_MASK;
+	val = (val & WM8994_AIF1CLK_SRC_MASK) >> WM8994_AIF1CLK_SRC_SHIFT;
 
 	switch (val) {
 	case 0:
@@ -1078,16 +1089,13 @@ static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enabl
 		return 0;
 	}
 
-	if (enable) {
-		ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
-		if (ret < 0) {
-			dev_err(component->dev,	"Failed to enable MCLK%d\n",
-				clk_idx);
-			return ret;
-		}
-	} else {
-		clk_disable_unprepare(wm8994->mclk[clk_idx].clk);
+	ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
+	if (ret < 0) {
+		dev_err(component->dev,	"Failed to enable MCLK%d\n",
+			clk_idx + 1);
+		return ret;
 	}
+	wm8994->aif_mclk[aif] = wm8994->mclk[clk_idx].clk;
 
 	return 0;
 }
diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h
index b28398aa9e48..5b22cfab317e 100644
--- a/sound/soc/codecs/wm8994.h
+++ b/sound/soc/codecs/wm8994.h
@@ -81,6 +81,7 @@ struct wm8994_priv {
 	struct wm_hubs_data hubs;
 	struct wm8994 *wm8994;
 	struct clk_bulk_data mclk[WM8994_NUM_MCLK];
+	struct clk *aif_mclk[2];
 	int sysclk[2];
 	int sysclk_rate[2];
 	int mclk_rate[2];
-- 
2.43.0

[PATCH 2/4] ASoC: wm8994: don't lose the AIF clock ratio when staying at 32kHz SYSCLK

[Marek Szyprowski]

When SYSCLK drops below 50kHz, the AIFnCLK rate ratio is saved and
temporarily lowered to 128fs for accessory detection, then restored
once SYSCLK gets fast enough again. The ratio is however saved again
on each clock reconfiguration done while SYSCLK is still slow, which
overwrites the original ratio with the 128fs one.

This happens on the Exynos4412 Trats2 board, which set MCLK2 as SYSCLK
twice during the card probe and then configure FLL1 while still running
from MCLK2. Once SYSCLK is switched to FLL1, the 128fs ratio is
"restored", so AIF1 is left configured for 48kHz at 128fs while being
clocked at 256fs. If any digital path is powered up before a stream
reconfigures the AIF, the codec raises FIFO error interrupts every
10ms, flooding the kernel log:

 wm8994-codec wm8994-codec: FIFO error

Save the original ratio only when entering the low SYSCLK mode. While
at it, move the code duplicated in _wm8994_set_fll() and
wm8994_set_dai_sysclk() to a common helper.

Fixes: 6730049a4763 ("ASoC: wm8994: Lower AIFnCLK divisor when dropping to 32kHz")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 sound/soc/codecs/wm8994.c | 94 +++++++++++++++++----------------------
 1 file changed, 40 insertions(+), 54 deletions(-)

diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index e21adcaf3477..e4ea9d41107b 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -2207,6 +2207,44 @@ static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
 	return 0;
 }
 
+/*
+ * If SYSCLK is less than 50kHz adjust AIFnCLK dividers for detection,
+ * restoring the original ones once SYSCLK is fast enough again.
+ */
+static void wm8994_update_aif_clk_rate(struct snd_soc_component *component)
+{
+	struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
+
+	if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
+		/* Don't overwrite the saved dividers with the 128fs ones */
+		if (!wm8994->aifdiv[0]) {
+			dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
+
+			wm8994->aifdiv[0] = snd_soc_component_read(component,
+								   WM8994_AIF1_RATE)
+				& WM8994_AIF1CLK_RATE_MASK;
+			wm8994->aifdiv[1] = snd_soc_component_read(component,
+								   WM8994_AIF2_RATE)
+				& WM8994_AIF1CLK_RATE_MASK;
+		}
+
+		snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
+				    WM8994_AIF1CLK_RATE_MASK, 0x1);
+		snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
+				    WM8994_AIF2CLK_RATE_MASK, 0x1);
+	} else if (wm8994->aifdiv[0]) {
+		snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
+				    WM8994_AIF1CLK_RATE_MASK,
+				    wm8994->aifdiv[0]);
+		snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
+				    WM8994_AIF2CLK_RATE_MASK,
+				    wm8994->aifdiv[1]);
+
+		wm8994->aifdiv[0] = 0;
+		wm8994->aifdiv[1] = 0;
+	}
+}
+
 static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src,
 			  unsigned int freq_in, unsigned int freq_out)
 {
@@ -2441,33 +2479,7 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src,
 
 	configure_clock(component);
 
-	/*
-	 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
-	 * for detection.
-	 */
-	if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
-		dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
-
-		wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
-			& WM8994_AIF1CLK_RATE_MASK;
-		wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
-			& WM8994_AIF1CLK_RATE_MASK;
-
-		snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
-				    WM8994_AIF1CLK_RATE_MASK, 0x1);
-		snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
-				    WM8994_AIF2CLK_RATE_MASK, 0x1);
-	} else if (wm8994->aifdiv[0]) {
-		snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
-				    WM8994_AIF1CLK_RATE_MASK,
-				    wm8994->aifdiv[0]);
-		snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
-				    WM8994_AIF2CLK_RATE_MASK,
-				    wm8994->aifdiv[1]);
-
-		wm8994->aifdiv[0] = 0;
-		wm8994->aifdiv[1] = 0;
-	}
+	wm8994_update_aif_clk_rate(component);
 
 	return 0;
 }
@@ -2585,33 +2597,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
 
 	configure_clock(component);
 
-	/*
-	 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
-	 * for detection.
-	 */
-	if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
-		dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
-
-		wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
-			& WM8994_AIF1CLK_RATE_MASK;
-		wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
-			& WM8994_AIF1CLK_RATE_MASK;
-
-		snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
-				    WM8994_AIF1CLK_RATE_MASK, 0x1);
-		snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
-				    WM8994_AIF2CLK_RATE_MASK, 0x1);
-	} else if (wm8994->aifdiv[0]) {
-		snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
-				    WM8994_AIF1CLK_RATE_MASK,
-				    wm8994->aifdiv[0]);
-		snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
-				    WM8994_AIF2CLK_RATE_MASK,
-				    wm8994->aifdiv[1]);
-
-		wm8994->aifdiv[0] = 0;
-		wm8994->aifdiv[1] = 0;
-	}
+	wm8994_update_aif_clk_rate(component);
 
 	return 0;
 }
-- 
2.43.0

[PATCH 3/4] ASoC: wm8994: fix MCLK index used for setting MCLK rate

[Marek Szyprowski]

wm8994_set_dai_sysclk() passes the AIF index (dai->id - 1) to
wm8994_set_mclk_rate(), which uses it to index the MCLK clocks and
their cached rates. As a result, selecting MCLK2 as the AIF1 clock
source sets and reads back the rate of MCLK1 instead, and the rate
of MCLK1 is then stored as the MCLK2 rate.

On the Exynos4412 Trats2 board, where MCLK1 is a fixed 24MHz clock and
MCLK2 a 32768Hz clock used when the codec is idle, this gives:

 wm8994-codec wm8994-codec: AIF1 using MCLK2 at 24000000Hz

so the driver assumes a 12MHz SYSCLK while it actually runs at 32kHz.
This skips the 128fs AIF clock ratio setup for low SYSCLK rates and
makes the mic detection rate configuration use the wrong clock rate.

Pass the MCLK index matching the selected clock source instead.

Fixes: 419e2f508336 ("ASoC: wm8994: Add support for setting MCLK clock rate")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 sound/soc/codecs/wm8994.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index e4ea9d41107b..8adb3de546dd 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -2539,7 +2539,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
 	case WM8994_SYSCLK_MCLK1:
 		wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
 
-		ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
+		ret = wm8994_set_mclk_rate(wm8994, WM8994_MCLK1, &freq);
 		if (ret < 0)
 			return ret;
 
@@ -2552,7 +2552,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
 		/* TODO: Set GPIO AF */
 		wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
 
-		ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
+		ret = wm8994_set_mclk_rate(wm8994, WM8994_MCLK2, &freq);
 		if (ret < 0)
 			return ret;
 
-- 
2.43.0

[PATCH 4/4] ASoC: samsung: midas_wm1811: run FLL1 at the AIF1 configured rate when idle

[Marek Szyprowski]

When the codec is brought up without an active stream, for example
because the mixer state restored by alsactl powers up a digital path,
midas_start_fll1() sets FLL1 to the default 11.2896MHz rate. The
codec's AIF1 however keeps the configuration of the last stream, or its
reset default of 48kHz at 256fs before the first stream, which needs
a 12.288MHz AIF1 clock. The digital paths then run with AIF1 clocked
at a rate not matching its configuration.

Remember the FLL1 rate requested by the last hw_params() call, which
matches the AIF1 configuration kept in the codec, and use it when no
specific rate is requested. Change the default rate used before the
first stream to 12.288MHz, matching the codec's default AIF1
configuration.

Fixes: fd0ea9cd9698 ("ASoC: samsung: Add sound support for Midas boards")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 sound/soc/samsung/midas_wm1811.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/sound/soc/samsung/midas_wm1811.c b/sound/soc/samsung/midas_wm1811.c
index d43af5069baf..11466dd3539e 100644
--- a/sound/soc/samsung/midas_wm1811.c
+++ b/sound/soc/samsung/midas_wm1811.c
@@ -25,7 +25,8 @@
  */
 #define MCLK1_RATE 24000000U
 #define MCLK2_RATE 32768U
-#define DEFAULT_FLL1_RATE 11289600U
+/* Matches the codec's default AIF1 configuration: 48kHz, 256fs */
+#define DEFAULT_FLL1_RATE 12288000U
 
 struct midas_priv {
 	struct gpio_desc *gpio_fm_sel;
@@ -34,6 +35,7 @@ struct midas_priv {
 	struct gpio_desc *gpio_headset_key;
 	struct iio_channel *adc_headset_detect;
 	unsigned int fll1_rate;
+	unsigned int aif1clk_rate;
 
 	struct snd_soc_jack headset_jack;
 };
@@ -171,11 +173,12 @@ static int midas_start_fll1(struct snd_soc_pcm_runtime *rtd, unsigned int rate)
 	if (!rate)
 		rate = priv->fll1_rate;
 	/*
-	 * If no new rate is requested, set FLL1 to a sane default for jack
-	 * detection.
+	 * If no new rate is requested, set FLL1 to the rate the codec's AIF1
+	 * is currently configured for, as its digital paths can be powered
+	 * up without an active stream.
 	 */
 	if (!rate)
-		rate = DEFAULT_FLL1_RATE;
+		rate = priv->aif1clk_rate ?: DEFAULT_FLL1_RATE;
 
 	if (rate != priv->fll1_rate && priv->fll1_rate) {
 		/* while reconfiguring, switch to MCLK2 for SYSCLK */
@@ -241,6 +244,7 @@ static int midas_aif1_hw_params(struct snd_pcm_substream *substream,
 				struct snd_pcm_hw_params *params)
 {
 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+	struct midas_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 	unsigned int pll_out;
 
 	/* AIF1CLK should be at least 3MHz for "optimal performance" */
@@ -249,6 +253,8 @@ static int midas_aif1_hw_params(struct snd_pcm_substream *substream,
 	else
 		pll_out = params_rate(params) * 256;
 
+	priv->aif1clk_rate = pll_out;
+
 	return midas_start_fll1(rtd, pll_out);
 }
 
-- 
2.43.0

Re: [PATCH 3/4] ASoC: wm8994: fix MCLK index used for setting MCLK rate

[Charles Keepax]

On Wed, Oct 21, 2026 at 12:17:44PM +0200, Marek Szyprowski wrote:
> wm8994_set_dai_sysclk() passes the AIF index (dai->id - 1) to
> wm8994_set_mclk_rate(), which uses it to index the MCLK clocks and
> their cached rates. As a result, selecting MCLK2 as the AIF1 clock
> source sets and reads back the rate of MCLK1 instead, and the rate
> of MCLK1 is then stored as the MCLK2 rate.
> 
> On the Exynos4412 Trats2 board, where MCLK1 is a fixed 24MHz clock and
> MCLK2 a 32768Hz clock used when the codec is idle, this gives:
> 
>  wm8994-codec wm8994-codec: AIF1 using MCLK2 at 24000000Hz
> 
> so the driver assumes a 12MHz SYSCLK while it actually runs at 32kHz.
> This skips the 128fs AIF clock ratio setup for low SYSCLK rates and
> makes the mic detection rate configuration use the wrong clock rate.
> 
> Pass the MCLK index matching the selected clock source instead.
> 
> Fixes: 419e2f508336 ("ASoC: wm8994: Add support for setting MCLK clock rate")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---

Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>

Thanks,
Charles

Re: [PATCH 2/4] ASoC: wm8994: don't lose the AIF clock ratio when staying at 32kHz SYSCLK

[Charles Keepax]

On Wed, Oct 21, 2026 at 12:17:43PM +0200, Marek Szyprowski wrote:
> When SYSCLK drops below 50kHz, the AIFnCLK rate ratio is saved and
> temporarily lowered to 128fs for accessory detection, then restored
> once SYSCLK gets fast enough again. The ratio is however saved again
> on each clock reconfiguration done while SYSCLK is still slow, which
> overwrites the original ratio with the 128fs one.
> 
> This happens on the Exynos4412 Trats2 board, which set MCLK2 as SYSCLK
> twice during the card probe and then configure FLL1 while still running
> from MCLK2. Once SYSCLK is switched to FLL1, the 128fs ratio is
> "restored", so AIF1 is left configured for 48kHz at 128fs while being
> clocked at 256fs. If any digital path is powered up before a stream
> reconfigures the AIF, the codec raises FIFO error interrupts every
> 10ms, flooding the kernel log:
> 
>  wm8994-codec wm8994-codec: FIFO error
> 
> Save the original ratio only when entering the low SYSCLK mode. While
> at it, move the code duplicated in _wm8994_set_fll() and
> wm8994_set_dai_sysclk() to a common helper.
> 
> Fixes: 6730049a4763 ("ASoC: wm8994: Lower AIFnCLK divisor when dropping to 32kHz")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---

Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>

Thanks,
Charles

Re: [PATCH 1/4] ASoC: wm8994: fix MCLK gating for AIF clocks sourced from MCLK2

[Charles Keepax]

On Wed, Oct 21, 2026 at 12:17:42PM +0200, Marek Szyprowski wrote:
> aif_mclk_set() masks the AIFnCLK_SRC field of the AIFn clocking
> register, but compares the result with unshifted field values. The
> MCLK2 source (0x08) therefore never matches, so MCLK2 is never enabled
> for an AIF clocked from it, and the AIF relies on other users of that
> clock to keep it running.
> 
> On the Exynos4412 Trats2 board, AIF1 and SYSCLK run from MCLK2, the
> 32768Hz PMIC clock, while the codec is idle. That clock is shared with
> the WLAN and Bluetooth chips, which enable it only once their drivers
> are loaded. Until then the codec runs from a stopped clock: FLL1 fails
> to lock when configured from that state, and the codec floods the
> kernel log with FIFO error interrupts once a digital path is powered
> up:
> 
>  wm8994-codec wm8994-codec: Timed out waiting for FLL lock
>  wm8994-codec wm8994-codec: FIFO error
> 
> Booting with clk_ignore_unused, which keeps that clock running from
> the bootloader, makes both issues disappear.
> 
> Fixing just the comparison is not enough. The AIF clock source can
> be changed while the AIF clock is running, for example the Midas
> machine driver switches AIF1 between MCLK2 and FLL1 while AIF1CLK is
> kept enabled for jack detection. Looking up the clock again on disable
> can then release a different MCLK than the one enabled, leaking the
> enable count of one clock and underflowing the other.
> 
> Shift the field value before decoding it, and remember which MCLK has
> been enabled for each AIF, so that the same clock is released on
> disable. While at it, report the MCLK number 1-based in the error
> message.
> 
> Fixes: 001b83d395ab ("ASoC: wm8994: Add support for MCLKn clock gating")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---

Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>

Thanks,
Charles

RE: [PATCH 1/4] ASoC: wm8994: fix MCLK gating for AIF clocks sourced from MCLK2

[Sylwester Nawrocki]

> -----Original Message-----
> From: Marek Szyprowski <m.szyprowski@samsung.com>
> Sent: środa, 21 października 2026 12:18
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>; Liam Girdwood
> <lgirdwood@gmail.com>; Mark Brown <broonie@kernel.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Charles Keepax
> <ckeepax@opensource.cirrus.com>; Krzysztof Kozlowski <krzk@kernel.org>;
> Simon Shields <simon@lineageos.org>; Artur Weber
> <aweber.kernel@gmail.com>; patches@opensource.cirrus.com; linux-
> sound@vger.kernel.org
> Subject: [PATCH 1/4] ASoC: wm8994: fix MCLK gating for AIF clocks sourced
> from MCLK2
> 
> aif_mclk_set() masks the AIFnCLK_SRC field of the AIFn clocking
> register, but compares the result with unshifted field values. The
> MCLK2 source (0x08) therefore never matches, so MCLK2 is never enabled
> for an AIF clocked from it, and the AIF relies on other users of that
> clock to keep it running.
> 
> On the Exynos4412 Trats2 board, AIF1 and SYSCLK run from MCLK2, the
> 32768Hz PMIC clock, while the codec is idle. That clock is shared with
> the WLAN and Bluetooth chips, which enable it only once their drivers
> are loaded. Until then the codec runs from a stopped clock: FLL1 fails
> to lock when configured from that state, and the codec floods the
> kernel log with FIFO error interrupts once a digital path is powered
> up:
> 
>  wm8994-codec wm8994-codec: Timed out waiting for FLL lock
>  wm8994-codec wm8994-codec: FIFO error
> 
> Booting with clk_ignore_unused, which keeps that clock running from
> the bootloader, makes both issues disappear.
> 
> Fixing just the comparison is not enough. The AIF clock source can
> be changed while the AIF clock is running, for example the Midas
> machine driver switches AIF1 between MCLK2 and FLL1 while AIF1CLK is
> kept enabled for jack detection. Looking up the clock again on disable
> can then release a different MCLK than the one enabled, leaking the
> enable count of one clock and underflowing the other.
> 
> Shift the field value before decoding it, and remember which MCLK has
> been enabled for each AIF, so that the same clock is released on
> disable. While at it, report the MCLK number 1-based in the error
> message.
> 
> Fixes: 001b83d395ab ("ASoC: wm8994: Add support for MCLKn clock
> gating")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

RE: [PATCH 2/4] ASoC: wm8994: don't lose the AIF clock ratio when staying at 32kHz SYSCLK

[Sylwester Nawrocki]

> -----Original Message-----
> From: Marek Szyprowski <m.szyprowski@samsung.com>
> Sent: środa, 21 października 2026 12:18
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>; Liam Girdwood
> <lgirdwood@gmail.com>; Mark Brown <broonie@kernel.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Charles Keepax
> <ckeepax@opensource.cirrus.com>; Krzysztof Kozlowski <krzk@kernel.org>;
> Simon Shields <simon@lineageos.org>; Artur Weber
> <aweber.kernel@gmail.com>; patches@opensource.cirrus.com; linux-
> sound@vger.kernel.org
> Subject: [PATCH 2/4] ASoC: wm8994: don't lose the AIF clock ratio when
> staying at 32kHz SYSCLK
> 
> When SYSCLK drops below 50kHz, the AIFnCLK rate ratio is saved and
> temporarily lowered to 128fs for accessory detection, then restored
> once SYSCLK gets fast enough again. The ratio is however saved again
> on each clock reconfiguration done while SYSCLK is still slow, which
> overwrites the original ratio with the 128fs one.
> 
> This happens on the Exynos4412 Trats2 board, which set MCLK2 as SYSCLK
> twice during the card probe and then configure FLL1 while still running
> from MCLK2. Once SYSCLK is switched to FLL1, the 128fs ratio is
> "restored", so AIF1 is left configured for 48kHz at 128fs while being
> clocked at 256fs. If any digital path is powered up before a stream
> reconfigures the AIF, the codec raises FIFO error interrupts every
> 10ms, flooding the kernel log:
> 
>  wm8994-codec wm8994-codec: FIFO error
> 
> Save the original ratio only when entering the low SYSCLK mode. While
> at it, move the code duplicated in _wm8994_set_fll() and
> wm8994_set_dai_sysclk() to a common helper.
> 
> Fixes: 6730049a4763 ("ASoC: wm8994: Lower AIFnCLK divisor when
> dropping to 32kHz")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

RE: [PATCH 3/4] ASoC: wm8994: fix MCLK index used for setting MCLK rate

[Sylwester Nawrocki]

> -----Original Message-----
> From: Marek Szyprowski <m.szyprowski@samsung.com>
> Sent: środa, 21 października 2026 12:18
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>; Liam Girdwood
> <lgirdwood@gmail.com>; Mark Brown <broonie@kernel.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Charles Keepax
> <ckeepax@opensource.cirrus.com>; Krzysztof Kozlowski <krzk@kernel.org>;
> Simon Shields <simon@lineageos.org>; Artur Weber
> <aweber.kernel@gmail.com>; patches@opensource.cirrus.com; linux-
> sound@vger.kernel.org
> Subject: [PATCH 3/4] ASoC: wm8994: fix MCLK index used for setting MCLK
> rate
> 
> wm8994_set_dai_sysclk() passes the AIF index (dai->id - 1) to
> wm8994_set_mclk_rate(), which uses it to index the MCLK clocks and
> their cached rates. As a result, selecting MCLK2 as the AIF1 clock
> source sets and reads back the rate of MCLK1 instead, and the rate
> of MCLK1 is then stored as the MCLK2 rate.
> 
> On the Exynos4412 Trats2 board, where MCLK1 is a fixed 24MHz clock and
> MCLK2 a 32768Hz clock used when the codec is idle, this gives:
> 
>  wm8994-codec wm8994-codec: AIF1 using MCLK2 at 24000000Hz
> 
> so the driver assumes a 12MHz SYSCLK while it actually runs at 32kHz.
> This skips the 128fs AIF clock ratio setup for low SYSCLK rates and
> makes the mic detection rate configuration use the wrong clock rate.
> 
> Pass the MCLK index matching the selected clock source instead.
> 
> Fixes: 419e2f508336 ("ASoC: wm8994: Add support for setting MCLK clock
> rate")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Re: [PATCH 1/4] ASoC: wm8994: fix MCLK gating for AIF clocks sourced from MCLK2

[Mark Brown]

> aif_mclk_set() masks the AIFnCLK_SRC field of the AIFn clocking
> register, but compares the result with unshifted field values. The
> MCLK2 source (0x08) therefore never matches, so MCLK2 is never enabled
> for an AIF clocked from it, and the AIF relies on other users of that
> clock to keep it running.
> 
> On the Exynos4412 Trats2 board, AIF1 and SYSCLK run from MCLK2, the
> 32768Hz PMIC clock, while the codec is idle. That clock is shared with
> the WLAN and Bluetooth chips, which enable it only once their drivers
> are loaded. Until then the codec runs from a stopped clock: FLL1 fails
> to lock when configured from that state, and the codec floods the
> kernel log with FIFO error interrupts once a digital path is powered
> up:
> 
>  wm8994-codec wm8994-codec: Timed out waiting for FLL lock
>  wm8994-codec wm8994-codec: FIFO error
> 
> Booting with clk_ignore_unused, which keeps that clock running from
> the bootloader, makes both issues disappear.
> 
> Fixing just the comparison is not enough. The AIF clock source can
> be changed while the AIF clock is running, for example the Midas
> machine driver switches AIF1 between MCLK2 and FLL1 while AIF1CLK is
> kept enabled for jack detection. Looking up the clock again on disable
> can then release a different MCLK than the one enabled, leaking the
> enable count of one clock and underflowing the other.
> 
> Shift the field value before decoding it, and remember which MCLK has
> been enabled for each AIF, so that the same clock is released on
> disable. While at it, report the MCLK number 1-based in the error
> message.
> 
> Fixes: 001b83d395ab ("ASoC: wm8994: Add support for MCLKn clock gating")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  sound/soc/codecs/wm8994.c | 28 ++++++++++++++++++----------
>  sound/soc/codecs/wm8994.h |  1 +
>  2 files changed, 19 insertions(+), 10 deletions(-)
>
> diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
> index c65a7769a9d25..e21adcaf34770 100644
> --- a/sound/soc/codecs/wm8994.c
> +++ b/sound/soc/codecs/wm8994.c
> @@ -1059,13 +1059,24 @@ static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enabl
>  	unsigned int offset, val, clk_idx;
>  	int ret;
>  
> +	/*
> +	 * The AIF clock source may be changed while the AIF clock is
> +	 * running, so release the MCLK which has been enabled for it
> +	 * instead of the one currently selected.
> +	 */
> +	if (!enable) {
> +		clk_disable_unprepare(wm8994->aif_mclk[aif]);
> +		wm8994->aif_mclk[aif] = NULL;
> +		return 0;
> +	}
> +
>  	if (aif)
>  		offset = 4;
>  	else
>  		offset = 0;
>  
>  	val = snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1 + offset);
> -	val &= WM8994_AIF1CLK_SRC_MASK;
> +	val = (val & WM8994_AIF1CLK_SRC_MASK) >> WM8994_AIF1CLK_SRC_SHIFT;
>  
>  	switch (val) {
>  	case 0:
> @@ -1078,16 +1089,13 @@ static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enabl
>  		return 0;
>  	}
>  
> -	if (enable) {
> -		ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
> -		if (ret < 0) {
> -			dev_err(component->dev,	"Failed to enable MCLK%d\n",
> -				clk_idx);
> -			return ret;
> -		}
> -	} else {
> -		clk_disable_unprepare(wm8994->mclk[clk_idx].clk);
> +	ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
> +	if (ret < 0) {
> +		dev_err(component->dev,	"Failed to enable MCLK%d\n",
> +			clk_idx + 1);
> +		return ret;
>  	}
> +	wm8994->aif_mclk[aif] = wm8994->mclk[clk_idx].clk;

We could also have changes from configure_aif_clock() while the clock is
up.

-- 
Mark Brown <broonie@kernel.org>

RE: [PATCH 4/4] ASoC: samsung: midas_wm1811: run FLL1 at the AIF1 configured rate when idle

[Sylwester Nawrocki]

> -----Original Message-----
> From: Marek Szyprowski <m.szyprowski@samsung.com>
[...]
> Subject: [PATCH 4/4] ASoC: samsung: midas_wm1811: run FLL1 at the AIF1
> configured rate when idle
> 
> When the codec is brought up without an active stream, for example
> because the mixer state restored by alsactl powers up a digital path,
> midas_start_fll1() sets FLL1 to the default 11.2896MHz rate. The
> codec's AIF1 however keeps the configuration of the last stream, or its
> reset default of 48kHz at 256fs before the first stream, which needs
> a 12.288MHz AIF1 clock. The digital paths then run with AIF1 clocked
> at a rate not matching its configuration.
> 
> Remember the FLL1 rate requested by the last hw_params() call, which
> matches the AIF1 configuration kept in the codec, and use it when no
> specific rate is requested. Change the default rate used before the
> first stream to 12.288MHz, matching the codec's default AIF1
> configuration.
> 
> Fixes: fd0ea9cd9698 ("ASoC: samsung: Add sound support for Midas
> boards")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>