From: Andi Kleen <andi@firstfloor.org>
To: peterz@infradead.org
Cc: eranian@google.com, linux-kernel@vger.kernel.org,
Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 4/9] perf: Add cycles to branch_info
Date: Sun, 10 May 2015 12:22:42 -0700 [thread overview]
Message-ID: <1431285767-27027-5-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1431285767-27027-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
Skylake supports reporting the time in cycles a branch in the LBR
took, to give a rough indication of the basic block performance.
Export the cycle information in the branch_info structure.
This can be done by just reusing some currently zero padding.
This is just the generic header change. The architecture
still needs to fill it in.
There's no attempt to convert to real time, as we really
want cycles here.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
include/uapi/linux/perf_event.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 309211b..9ef489e 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -904,6 +904,7 @@ union perf_mem_data_src {
*
* in_tx: running in a hardware transaction
* abort: aborting a hardware transaction
+ * cycles: cycles from last branch (or 0 if not supported)
*/
struct perf_branch_entry {
__u64 from;
@@ -912,7 +913,8 @@ struct perf_branch_entry {
predicted:1,/* target predicted */
in_tx:1, /* in transaction */
abort:1, /* transaction abort */
- reserved:60;
+ cycles:16, /* cycle count to last branch */
+ reserved:44;
};
#endif /* _UAPI_LINUX_PERF_EVENT_H */
--
1.9.3
next prev parent reply other threads:[~2015-05-10 19:22 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-10 19:22 perf: Add basic Skylake PMU support v2 Andi Kleen
2015-05-10 19:22 ` [PATCH 1/9] x86: Add a native_perf_sched_clock_from_tsc Andi Kleen
2015-08-04 8:55 ` [tip:perf/core] perf/x86: Add a native_perf_sched_clock_from_tsc( ) tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
2015-08-04 8:56 ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Andi Kleen
2015-08-04 8:56 ` [tip:perf/core] x86: Add new MSRs and MSR bits used for Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` Andi Kleen [this message]
2015-08-04 8:57 ` [tip:perf/core] perf: Add cycles to branch_info tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 5/9] x86, perf: Add support for LBRv5 Andi Kleen
2015-08-04 8:57 ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 6/9] x86, perf: Add Skylake support Andi Kleen
2015-08-04 8:59 ` [tip:perf/core] perf/x86/intel: Add Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 7/9] x86, perf: Handle new arch perfmon v4 status bits Andi Kleen
2015-08-04 8:57 ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 8/9] x86, perf: Optimize v4 LBR unfreezing Andi Kleen
2015-08-04 8:58 ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 9/9] x86, perf: Move PMU ACK after LBR read Andi Kleen
2015-05-11 16:23 ` Peter Zijlstra
2015-05-11 16:32 ` Stephane Eranian
2015-05-11 16:36 ` Peter Zijlstra
2015-05-11 16:43 ` Stephane Eranian
2015-05-11 16:48 ` Andi Kleen
2015-08-04 8:58 ` [tip:perf/core] perf/x86/intel: Move PMU ACK to " tip-bot for Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2015-05-07 22:56 perf: Add basic Skylake PMU support Andi Kleen
2015-05-07 22:56 ` [PATCH 4/9] perf: Add cycles to branch_info Andi Kleen
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