From: Andi Kleen <andi@firstfloor.org>
To: peterz@infradead.org
Cc: eranian@google.com, linux-kernel@vger.kernel.org,
Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 8/9] x86, perf: Optimize v4 LBR unfreezing
Date: Sun, 10 May 2015 12:22:46 -0700 [thread overview]
Message-ID: <1431285767-27027-9-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1431285767-27027-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
In Arch perfmon v4 the GLOBAL_STATUS reset automatically unfreezes
LBRs. So no need to do it manually in the LBR code. Add a check
to skip it.
v2: Move test up to beginning of function.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel_lbr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 6c48c97..ae54ea9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -139,6 +139,13 @@ static void __intel_pmu_lbr_enable(bool pmi)
u64 debugctl, lbr_select = 0, orig_debugctl;
/*
+ * No need to unfreeze manually, as v4 can do that as part
+ * of the GLOBAL_STATUS ack.
+ */
+ if (pmi && x86_pmu.version >= 4)
+ return;
+
+ /*
* No need to reprogram LBR_SELECT in a PMI, as it
* did not change.
*/
--
1.9.3
next prev parent reply other threads:[~2015-05-10 19:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-10 19:22 perf: Add basic Skylake PMU support v2 Andi Kleen
2015-05-10 19:22 ` [PATCH 1/9] x86: Add a native_perf_sched_clock_from_tsc Andi Kleen
2015-08-04 8:55 ` [tip:perf/core] perf/x86: Add a native_perf_sched_clock_from_tsc( ) tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
2015-08-04 8:56 ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Andi Kleen
2015-08-04 8:56 ` [tip:perf/core] x86: Add new MSRs and MSR bits used for Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 4/9] perf: Add cycles to branch_info Andi Kleen
2015-08-04 8:57 ` [tip:perf/core] " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 5/9] x86, perf: Add support for LBRv5 Andi Kleen
2015-08-04 8:57 ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 6/9] x86, perf: Add Skylake support Andi Kleen
2015-08-04 8:59 ` [tip:perf/core] perf/x86/intel: Add Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 7/9] x86, perf: Handle new arch perfmon v4 status bits Andi Kleen
2015-08-04 8:57 ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` Andi Kleen [this message]
2015-08-04 8:58 ` [tip:perf/core] perf/x86/intel/lbr: Optimize v4 LBR unfreezing tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 9/9] x86, perf: Move PMU ACK after LBR read Andi Kleen
2015-05-11 16:23 ` Peter Zijlstra
2015-05-11 16:32 ` Stephane Eranian
2015-05-11 16:36 ` Peter Zijlstra
2015-05-11 16:43 ` Stephane Eranian
2015-05-11 16:48 ` Andi Kleen
2015-08-04 8:58 ` [tip:perf/core] perf/x86/intel: Move PMU ACK to " tip-bot for Andi Kleen
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