From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: eranian@google.com, linux-kernel@vger.kernel.org,
Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 9/9] x86, perf: Move PMU ACK after LBR read
Date: Mon, 11 May 2015 18:23:54 +0200 [thread overview]
Message-ID: <20150511162354.GA21418@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1431285767-27027-10-git-send-email-andi@firstfloor.org>
On Sun, May 10, 2015 at 12:22:47PM -0700, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> With Arch Perfmon v4 the PMU ack unfreezes the LBRs. So we need to do
> the PMU ack after the LBR reading, otherwise the LBRs would be polluted by the
> PMI handler.
Hmm, we should move these last three patches before the SKL enablement
patch no, otherwise things will misbehave -- say a bisection lands in
between.
/me shuffles patches.
> This is a minimal change. In principle the ACK could be moved much later.
Right, so the more complete change would be to use the new and improved
FREEZE_ON_PMI and reenable both the LBRs and the CTRs with the
STATUS_RESET MSR, right?
Does it make sense to have a new handle_irq() routine for that?
next prev parent reply other threads:[~2015-05-11 16:24 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-10 19:22 perf: Add basic Skylake PMU support v2 Andi Kleen
2015-05-10 19:22 ` [PATCH 1/9] x86: Add a native_perf_sched_clock_from_tsc Andi Kleen
2015-08-04 8:55 ` [tip:perf/core] perf/x86: Add a native_perf_sched_clock_from_tsc( ) tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
2015-08-04 8:56 ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Andi Kleen
2015-08-04 8:56 ` [tip:perf/core] x86: Add new MSRs and MSR bits used for Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 4/9] perf: Add cycles to branch_info Andi Kleen
2015-08-04 8:57 ` [tip:perf/core] " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 5/9] x86, perf: Add support for LBRv5 Andi Kleen
2015-08-04 8:57 ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 6/9] x86, perf: Add Skylake support Andi Kleen
2015-08-04 8:59 ` [tip:perf/core] perf/x86/intel: Add Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 7/9] x86, perf: Handle new arch perfmon v4 status bits Andi Kleen
2015-08-04 8:57 ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 8/9] x86, perf: Optimize v4 LBR unfreezing Andi Kleen
2015-08-04 8:58 ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 9/9] x86, perf: Move PMU ACK after LBR read Andi Kleen
2015-05-11 16:23 ` Peter Zijlstra [this message]
2015-05-11 16:32 ` Stephane Eranian
2015-05-11 16:36 ` Peter Zijlstra
2015-05-11 16:43 ` Stephane Eranian
2015-05-11 16:48 ` Andi Kleen
2015-08-04 8:58 ` [tip:perf/core] perf/x86/intel: Move PMU ACK to " tip-bot for Andi Kleen
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