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From: tip-bot for Andi Kleen <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, torvalds@linux-foundation.org,
	tglx@linutronix.de, mingo@kernel.org, ak@linux.intel.com,
	hpa@zytor.com, peterz@infradead.org
Subject: [tip:perf/core] perf/x86: Add a native_perf_sched_clock_from_tsc( )
Date: Tue, 4 Aug 2015 01:55:58 -0700	[thread overview]
Message-ID: <tip-a94cab2376cb35f236be14e2833cef63a8762a31@git.kernel.org> (raw)
In-Reply-To: <1431285767-27027-2-git-send-email-andi@firstfloor.org>

Commit-ID:  a94cab2376cb35f236be14e2833cef63a8762a31
Gitweb:     http://git.kernel.org/tip/a94cab2376cb35f236be14e2833cef63a8762a31
Author:     Andi Kleen <ak@linux.intel.com>
AuthorDate: Sun, 10 May 2015 12:22:39 -0700
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 4 Aug 2015 10:16:55 +0200

perf/x86: Add a native_perf_sched_clock_from_tsc()

PEBSv3 has a raw TSC time stamp in its memory buffer that
later needs to to be converted to perf_clock.

Add a native_sched_clock_from_tsc() that works the same
as native_sched_clock(), but starts with an already given
TSC value.

Paravirt is ignored, it will just get the native clock.
But there isn't a para virtualized PEBS anyway.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1431285767-27027-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/include/asm/tsc.h | 1 +
 arch/x86/kernel/tsc.c      | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 94605c0..aad56eb 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -51,6 +51,7 @@ extern int unsynchronized_tsc(void);
 extern int check_tsc_unstable(void);
 extern int check_tsc_disabled(void);
 extern unsigned long native_calibrate_tsc(void);
+extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
 
 extern int tsc_clocksource_reliable;
 
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 7437b41..88e9a38 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -296,6 +296,14 @@ u64 native_sched_clock(void)
 	return cycles_2_ns(tsc_now);
 }
 
+/*
+ * Generate a sched_clock if you already have a TSC value.
+ */
+u64 native_sched_clock_from_tsc(u64 tsc)
+{
+	return cycles_2_ns(tsc);
+}
+
 /* We need to define a real function for sched_clock, to override the
    weak default version */
 #ifdef CONFIG_PARAVIRT

  reply	other threads:[~2015-08-04  8:57 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-10 19:22 perf: Add basic Skylake PMU support v2 Andi Kleen
2015-05-10 19:22 ` [PATCH 1/9] x86: Add a native_perf_sched_clock_from_tsc Andi Kleen
2015-08-04  8:55   ` tip-bot for Andi Kleen [this message]
2015-05-10 19:22 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
2015-08-04  8:56   ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Andi Kleen
2015-08-04  8:56   ` [tip:perf/core] x86: Add new MSRs and MSR bits used for Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 4/9] perf: Add cycles to branch_info Andi Kleen
2015-08-04  8:57   ` [tip:perf/core] " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 5/9] x86, perf: Add support for LBRv5 Andi Kleen
2015-08-04  8:57   ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 6/9] x86, perf: Add Skylake support Andi Kleen
2015-08-04  8:59   ` [tip:perf/core] perf/x86/intel: Add Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 7/9] x86, perf: Handle new arch perfmon v4 status bits Andi Kleen
2015-08-04  8:57   ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 8/9] x86, perf: Optimize v4 LBR unfreezing Andi Kleen
2015-08-04  8:58   ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 9/9] x86, perf: Move PMU ACK after LBR read Andi Kleen
2015-05-11 16:23   ` Peter Zijlstra
2015-05-11 16:32     ` Stephane Eranian
2015-05-11 16:36       ` Peter Zijlstra
2015-05-11 16:43         ` Stephane Eranian
2015-05-11 16:48           ` Andi Kleen
2015-08-04  8:58   ` [tip:perf/core] perf/x86/intel: Move PMU ACK to " tip-bot for Andi Kleen

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