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From: tip-bot for Andi Kleen <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: mingo@kernel.org, tglx@linutronix.de, ak@linux.intel.com,
	linux-kernel@vger.kernel.org, peterz@infradead.org,
	hpa@zytor.com, torvalds@linux-foundation.org
Subject: [tip:perf/core] perf/x86/intel/lbr: Optimize v4 LBR unfreezing
Date: Tue, 4 Aug 2015 01:58:44 -0700	[thread overview]
Message-ID: <tip-425507fa5f321bb5ce1b5eb57a9586e0cf0b9802@git.kernel.org> (raw)
In-Reply-To: <1431285767-27027-9-git-send-email-andi@firstfloor.org>

Commit-ID:  425507fa5f321bb5ce1b5eb57a9586e0cf0b9802
Gitweb:     http://git.kernel.org/tip/425507fa5f321bb5ce1b5eb57a9586e0cf0b9802
Author:     Andi Kleen <ak@linux.intel.com>
AuthorDate: Sun, 10 May 2015 12:22:46 -0700
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 4 Aug 2015 10:16:58 +0200

perf/x86/intel/lbr: Optimize v4 LBR unfreezing

In Arch perfmon v4 the GLOBAL_STATUS reset automatically unfreezes
LBRs. So no need to do it manually in the LBR code. Add a check
to skip it.

v2: Move test up to beginning of function.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1431285767-27027-9-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/perf_event_intel_lbr.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 2fb5737..769a42f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -141,6 +141,13 @@ static void __intel_pmu_lbr_enable(bool pmi)
 	u64 debugctl, lbr_select = 0, orig_debugctl;
 
 	/*
+	 * No need to unfreeze manually, as v4 can do that as part
+	 * of the GLOBAL_STATUS ack.
+	 */
+	if (pmi && x86_pmu.version >= 4)
+		return;
+
+	/*
 	 * No need to reprogram LBR_SELECT in a PMI, as it
 	 * did not change.
 	 */

  reply	other threads:[~2015-08-04  8:59 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-10 19:22 perf: Add basic Skylake PMU support v2 Andi Kleen
2015-05-10 19:22 ` [PATCH 1/9] x86: Add a native_perf_sched_clock_from_tsc Andi Kleen
2015-08-04  8:55   ` [tip:perf/core] perf/x86: Add a native_perf_sched_clock_from_tsc( ) tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
2015-08-04  8:56   ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Andi Kleen
2015-08-04  8:56   ` [tip:perf/core] x86: Add new MSRs and MSR bits used for Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 4/9] perf: Add cycles to branch_info Andi Kleen
2015-08-04  8:57   ` [tip:perf/core] " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 5/9] x86, perf: Add support for LBRv5 Andi Kleen
2015-08-04  8:57   ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 6/9] x86, perf: Add Skylake support Andi Kleen
2015-08-04  8:59   ` [tip:perf/core] perf/x86/intel: Add Intel Skylake PMU support tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 7/9] x86, perf: Handle new arch perfmon v4 status bits Andi Kleen
2015-08-04  8:57   ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen
2015-05-10 19:22 ` [PATCH 8/9] x86, perf: Optimize v4 LBR unfreezing Andi Kleen
2015-08-04  8:58   ` tip-bot for Andi Kleen [this message]
2015-05-10 19:22 ` [PATCH 9/9] x86, perf: Move PMU ACK after LBR read Andi Kleen
2015-05-11 16:23   ` Peter Zijlstra
2015-05-11 16:32     ` Stephane Eranian
2015-05-11 16:36       ` Peter Zijlstra
2015-05-11 16:43         ` Stephane Eranian
2015-05-11 16:48           ` Andi Kleen
2015-08-04  8:58   ` [tip:perf/core] perf/x86/intel: Move PMU ACK to " tip-bot for Andi Kleen

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