* [PATCH 1/3] pwm: lpss: Add support for multiple PWMs
@ 2015-10-20 13:53 Mika Westerberg
2015-10-20 13:53 ` [PATCH 2/3] pwm: lpss: Support all four PWMs on Intel Broxton Mika Westerberg
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Mika Westerberg @ 2015-10-20 13:53 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-pwm, Mika Westerberg, Qipeng Zha, Huiquan Zhong,
linux-kernel
New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI)
device. Each PWM has 1k of register space allocated from the parent device.
Add support for this.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
drivers/pwm/pwm-lpss.c | 48 +++++++++++++++++++++++++++---------------------
drivers/pwm/pwm-lpss.h | 1 +
2 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index e9798253a16f..e7392bdfdd18 100644
--- a/drivers/pwm/pwm-lpss.c
+++ b/drivers/pwm/pwm-lpss.c
@@ -29,6 +29,9 @@
#define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION)
#define NSECS_PER_SEC 1000000000UL
+/* Size of each PWM register space if multiple */
+#define PWM_SIZE 0x400
+
struct pwm_lpss_chip {
struct pwm_chip chip;
void __iomem *regs;
@@ -37,13 +40,15 @@ struct pwm_lpss_chip {
/* BayTrail */
const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
- .clk_rate = 25000000
+ .clk_rate = 25000000,
+ .npwm = 1,
};
EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
/* Braswell */
const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
- .clk_rate = 19200000
+ .clk_rate = 19200000,
+ .npwm = 1,
};
EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
@@ -52,6 +57,20 @@ static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
return container_of(chip, struct pwm_lpss_chip, chip);
}
+static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
+{
+ struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
+
+ return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
+}
+
+static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
+{
+ struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
+
+ writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
+}
+
static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
{
@@ -79,38 +98,30 @@ static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
duty_ns = 1;
on_time_div = 255 - (255 * duty_ns / period_ns);
- ctrl = readl(lpwm->regs + PWM);
+ ctrl = pwm_lpss_read(pwm);
ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
ctrl |= on_time_div;
/* request PWM to update on next cycle */
ctrl |= PWM_SW_UPDATE;
- writel(ctrl, lpwm->regs + PWM);
+ pwm_lpss_write(pwm, ctrl);
return 0;
}
static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
- struct pwm_lpss_chip *lpwm = to_lpwm(chip);
- u32 ctrl;
-
- ctrl = readl(lpwm->regs + PWM);
- writel(ctrl | PWM_ENABLE, lpwm->regs + PWM);
-
+ pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
return 0;
}
static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
- struct pwm_lpss_chip *lpwm = to_lpwm(chip);
- u32 ctrl;
-
- ctrl = readl(lpwm->regs + PWM);
- writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
+ pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
}
static const struct pwm_ops pwm_lpss_ops = {
+ .free = pwm_lpss_disable,
.config = pwm_lpss_config,
.enable = pwm_lpss_enable,
.disable = pwm_lpss_disable,
@@ -135,7 +146,7 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
lpwm->chip.dev = dev;
lpwm->chip.ops = &pwm_lpss_ops;
lpwm->chip.base = -1;
- lpwm->chip.npwm = 1;
+ lpwm->chip.npwm = info->npwm;
ret = pwmchip_add(&lpwm->chip);
if (ret) {
@@ -149,11 +160,6 @@ EXPORT_SYMBOL_GPL(pwm_lpss_probe);
int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
{
- u32 ctrl;
-
- ctrl = readl(lpwm->regs + PWM);
- writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
-
return pwmchip_remove(&lpwm->chip);
}
EXPORT_SYMBOL_GPL(pwm_lpss_remove);
diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
index aa041bb1b67d..ef2419f47c57 100644
--- a/drivers/pwm/pwm-lpss.h
+++ b/drivers/pwm/pwm-lpss.h
@@ -20,6 +20,7 @@ struct pwm_lpss_chip;
struct pwm_lpss_boardinfo {
unsigned long clk_rate;
+ size_t npwm;
};
extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
--
2.6.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] pwm: lpss: Support all four PWMs on Intel Broxton
2015-10-20 13:53 [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
@ 2015-10-20 13:53 ` Mika Westerberg
2015-10-20 13:53 ` [PATCH 3/3] pwm: lpss: Add more Intel Broxton IDs Mika Westerberg
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Mika Westerberg @ 2015-10-20 13:53 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-pwm, Mika Westerberg, Qipeng Zha, Huiquan Zhong,
linux-kernel
Intel Broxton has similar PWM than Intel Braswell but instead of one it has
four PWMs included in one PCI/ACPI device. This patch adds support for all
the four PWMs and changes the PCI part of the driver to use
'pwm_lpss_bxt_info' instead.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
drivers/pwm/pwm-lpss-pci.c | 4 ++--
drivers/pwm/pwm-lpss.c | 7 +++++++
drivers/pwm/pwm-lpss.h | 1 +
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-lpss-pci.c b/drivers/pwm/pwm-lpss-pci.c
index 45042c1b2046..6432a0b97701 100644
--- a/drivers/pwm/pwm-lpss-pci.c
+++ b/drivers/pwm/pwm-lpss-pci.c
@@ -44,10 +44,10 @@ static void pwm_lpss_remove_pci(struct pci_dev *pdev)
}
static const struct pci_device_id pwm_lpss_pci_ids[] = {
- { PCI_VDEVICE(INTEL, 0x0ac8), (unsigned long)&pwm_lpss_bsw_info},
+ { PCI_VDEVICE(INTEL, 0x0ac8), (unsigned long)&pwm_lpss_bxt_info},
{ PCI_VDEVICE(INTEL, 0x0f08), (unsigned long)&pwm_lpss_byt_info},
{ PCI_VDEVICE(INTEL, 0x0f09), (unsigned long)&pwm_lpss_byt_info},
- { PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)&pwm_lpss_bsw_info},
+ { PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)&pwm_lpss_bxt_info},
{ PCI_VDEVICE(INTEL, 0x2288), (unsigned long)&pwm_lpss_bsw_info},
{ PCI_VDEVICE(INTEL, 0x2289), (unsigned long)&pwm_lpss_bsw_info},
{ },
diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index e7392bdfdd18..df03b50f20dd 100644
--- a/drivers/pwm/pwm-lpss.c
+++ b/drivers/pwm/pwm-lpss.c
@@ -52,6 +52,13 @@ const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
};
EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
+/* Broxton */
+const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
+ .clk_rate = 19200000,
+ .npwm = 4,
+};
+EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
+
static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
{
return container_of(chip, struct pwm_lpss_chip, chip);
diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
index ef2419f47c57..b8001d6a3e00 100644
--- a/drivers/pwm/pwm-lpss.h
+++ b/drivers/pwm/pwm-lpss.h
@@ -25,6 +25,7 @@ struct pwm_lpss_boardinfo {
extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;
+extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info;
struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
const struct pwm_lpss_boardinfo *info);
--
2.6.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] pwm: lpss: Add more Intel Broxton IDs
2015-10-20 13:53 [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
2015-10-20 13:53 ` [PATCH 2/3] pwm: lpss: Support all four PWMs on Intel Broxton Mika Westerberg
@ 2015-10-20 13:53 ` Mika Westerberg
2015-11-06 9:15 ` [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
2015-11-06 13:29 ` Thierry Reding
3 siblings, 0 replies; 6+ messages in thread
From: Mika Westerberg @ 2015-10-20 13:53 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-pwm, Mika Westerberg, Qipeng Zha, Huiquan Zhong,
linux-kernel
Add more Intel Broxton ACPI and PCI IDs to the driver supported devices
list.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
drivers/pwm/pwm-lpss-pci.c | 1 +
drivers/pwm/pwm-lpss-platform.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/pwm/pwm-lpss-pci.c b/drivers/pwm/pwm-lpss-pci.c
index 6432a0b97701..c15bc6d00f1a 100644
--- a/drivers/pwm/pwm-lpss-pci.c
+++ b/drivers/pwm/pwm-lpss-pci.c
@@ -50,6 +50,7 @@ static const struct pci_device_id pwm_lpss_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)&pwm_lpss_bxt_info},
{ PCI_VDEVICE(INTEL, 0x2288), (unsigned long)&pwm_lpss_bsw_info},
{ PCI_VDEVICE(INTEL, 0x2289), (unsigned long)&pwm_lpss_bsw_info},
+ { PCI_VDEVICE(INTEL, 0x5ac8), (unsigned long)&pwm_lpss_bxt_info},
{ },
};
MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids);
diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c
index 18a9c880a76d..a914aacf6757 100644
--- a/drivers/pwm/pwm-lpss-platform.c
+++ b/drivers/pwm/pwm-lpss-platform.c
@@ -49,6 +49,7 @@ static int pwm_lpss_remove_platform(struct platform_device *pdev)
static const struct acpi_device_id pwm_lpss_acpi_match[] = {
{ "80860F09", (unsigned long)&pwm_lpss_byt_info },
{ "80862288", (unsigned long)&pwm_lpss_bsw_info },
+ { "80865AC8", (unsigned long)&pwm_lpss_bxt_info },
{ },
};
MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match);
--
2.6.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/3] pwm: lpss: Add support for multiple PWMs
2015-10-20 13:53 [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
2015-10-20 13:53 ` [PATCH 2/3] pwm: lpss: Support all four PWMs on Intel Broxton Mika Westerberg
2015-10-20 13:53 ` [PATCH 3/3] pwm: lpss: Add more Intel Broxton IDs Mika Westerberg
@ 2015-11-06 9:15 ` Mika Westerberg
2015-11-06 13:29 ` Thierry Reding
3 siblings, 0 replies; 6+ messages in thread
From: Mika Westerberg @ 2015-11-06 9:15 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-pwm, Qipeng Zha, Huiquan Zhong, linux-kernel
On Tue, Oct 20, 2015 at 04:53:05PM +0300, Mika Westerberg wrote:
> New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI)
> device. Each PWM has 1k of register space allocated from the parent device.
> Add support for this.
Hi Thierry,
Are you going to pick these up to PWM tree?
Thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] pwm: lpss: Add support for multiple PWMs
2015-10-20 13:53 [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
` (2 preceding siblings ...)
2015-11-06 9:15 ` [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
@ 2015-11-06 13:29 ` Thierry Reding
2015-11-06 13:36 ` Mika Westerberg
3 siblings, 1 reply; 6+ messages in thread
From: Thierry Reding @ 2015-11-06 13:29 UTC (permalink / raw)
To: Mika Westerberg; +Cc: linux-pwm, Qipeng Zha, Huiquan Zhong, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 980 bytes --]
On Tue, Oct 20, 2015 at 04:53:05PM +0300, Mika Westerberg wrote:
> New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI)
> device. Each PWM has 1k of register space allocated from the parent device.
> Add support for this.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> ---
> drivers/pwm/pwm-lpss.c | 48 +++++++++++++++++++++++++++---------------------
> drivers/pwm/pwm-lpss.h | 1 +
> 2 files changed, 28 insertions(+), 21 deletions(-)
Applied all three patches, with a minor cleanup, see below.
> diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
> index aa041bb1b67d..ef2419f47c57 100644
> --- a/drivers/pwm/pwm-lpss.h
> +++ b/drivers/pwm/pwm-lpss.h
> @@ -20,6 +20,7 @@ struct pwm_lpss_chip;
>
> struct pwm_lpss_boardinfo {
> unsigned long clk_rate;
> + size_t npwm;
> };
I changed the type of npwm to unsigned int to match the definition of
the pwm_chip.npwm field.
Thanks,
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/3] pwm: lpss: Add support for multiple PWMs
2015-11-06 13:29 ` Thierry Reding
@ 2015-11-06 13:36 ` Mika Westerberg
0 siblings, 0 replies; 6+ messages in thread
From: Mika Westerberg @ 2015-11-06 13:36 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-pwm, Qipeng Zha, Huiquan Zhong, linux-kernel
On Fri, Nov 06, 2015 at 02:29:53PM +0100, Thierry Reding wrote:
> On Tue, Oct 20, 2015 at 04:53:05PM +0300, Mika Westerberg wrote:
> > New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI)
> > device. Each PWM has 1k of register space allocated from the parent device.
> > Add support for this.
> >
> > Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> > ---
> > drivers/pwm/pwm-lpss.c | 48 +++++++++++++++++++++++++++---------------------
> > drivers/pwm/pwm-lpss.h | 1 +
> > 2 files changed, 28 insertions(+), 21 deletions(-)
>
> Applied all three patches, with a minor cleanup, see below.
>
> > diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
> > index aa041bb1b67d..ef2419f47c57 100644
> > --- a/drivers/pwm/pwm-lpss.h
> > +++ b/drivers/pwm/pwm-lpss.h
> > @@ -20,6 +20,7 @@ struct pwm_lpss_chip;
> >
> > struct pwm_lpss_boardinfo {
> > unsigned long clk_rate;
> > + size_t npwm;
> > };
>
> I changed the type of npwm to unsigned int to match the definition of
> the pwm_chip.npwm field.
Thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-11-06 13:36 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2015-10-20 13:53 [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
2015-10-20 13:53 ` [PATCH 2/3] pwm: lpss: Support all four PWMs on Intel Broxton Mika Westerberg
2015-10-20 13:53 ` [PATCH 3/3] pwm: lpss: Add more Intel Broxton IDs Mika Westerberg
2015-11-06 9:15 ` [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Mika Westerberg
2015-11-06 13:29 ` Thierry Reding
2015-11-06 13:36 ` Mika Westerberg
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