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From: "Rafael J. Wysocki" <rjw@sisk.pl>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@elte.hu>,
	Arjan van de Veen <arjan@infradead.org>,
	Andreas Herrmann <andreas.herrmann3@amd.com>,
	"Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [patch 0/6] AMD C1E aware idle support
Date: Thu, 12 Jun 2008 14:31:23 +0200	[thread overview]
Message-ID: <200806121431.24305.rjw@sisk.pl> (raw)
In-Reply-To: <20080610171639.551369443@linutronix.de>

On Thursday, 12 of June 2008, Thomas Gleixner wrote:
> AMD CPUs with C1E support are currently excluded from high resolution
> timers and NOHZ support. The reason is that C1E is a BIOS controlled
> C3 power state which switches off TSC and the local APIC timer. The
> ACPI C-State control manages the TSC/local APIC timer wreckage, but
> this does not include the C1 based ("halt" instruction) C1E mode. The
> BIOS/SMM controlled C1E state works on most systems even without
> enabling ACPI C-State control.
> 
> The fact that a system has C1E support enabled is advertised in a MSR,
> but the time during boot when the C1E bit is set by the BIOS varies:
> 
> 1) Boot CPU has already C1E bit set
> 2) Secondary CPU sets C1E bit
> 3) C1E bit is set after ACPI C-State query
> 
> Case #1 and #2 are covered by the current implementation, but case #3
> results in a complete system lockup due to missing timer
> interrupts. The current solution is to disable the local APIC timer
> and use the PIT in broadcast mode. This restricts the C1E enabled
> systems to periodic timer mode.
> 
> The following patch series implements a C1E aware idle function which
> also covers the late C1E enablement (case #3):
> 
> The function is selected during boot for CPUs which have possibly C1E
> support. The function checks the MSR which contains the C1E active
> bits before executing the halt instruction. When one of the C1E active
> bits is set, it makes the system C1E aware by enabling the timer
> broadcast mechanism for all CPUs. For high resolution timer and/or
> nohz enabled systems it calls the oneshot timer broadcast mechanism
> before executing the halt instruction. This is the same mechanism
> which is used in the ACPI C-State control for C2/C3 power states.
> 
> On my C1E affected X2 box these patches reduce the wakeups/sec down to
> 20 according to powertop.
> 
> The patches work fine on systems which are not affected by the dreaded
> ATI chipset timer wreckage. On those which have the problem, the box
> needs help from the keyboard to continue working.
> 
> The x86 changes for .27 contain a complete overhaul of the affected
> code, but this is out of scope for this patchset.
> 
> For those who are interested to test those patches on top of 2.6.26-rc
> I extracted a patch and added it to the c1e series. It's available
> from:
> 
> http://www.kernel.org/pub/linux/kernel/people/tglx/c1e/2.6.26-rc5-c1e-patches.tar.gz
> or
> http://www.kernel.org/pub/linux/kernel/people/tglx/c1e/2.6.26-rc5-c1e-patches.tar.bz2

I guess the x86-next-apic-timer-fixes.patch is a combination of all patches in
this series.  Is that correct?

Thanks,
Rafael

  parent reply	other threads:[~2008-06-12 12:30 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-06-12 10:28 [patch 0/6] AMD C1E aware idle support Thomas Gleixner
2008-06-12 10:28 ` [patch 1/6] x86: simplify idle selection Thomas Gleixner
2008-06-12 10:28 ` [patch 2/6] x86: cleanup C1E enabled detection Thomas Gleixner
2008-06-12 10:28 ` [patch 3/6] x86: use cpuinfo to check for interrupt pending message msr Thomas Gleixner
2008-06-13  6:55   ` Andreas Herrmann
2008-06-13 12:38     ` Thomas Gleixner
2008-06-13 14:28       ` Andreas Herrmann
2008-06-12 10:28 ` [patch 4/6] x86: use cpuid to check MWAIT support for C1 Thomas Gleixner
2008-06-12 10:28 ` [patch 5/6] x86: move more common idle functions/variables to process.c Thomas Gleixner
2008-06-12 10:29 ` [patch 6/6] x86: add c1e aware idle function Thomas Gleixner
2008-06-13  0:55   ` Andrew Morton
2008-06-13  6:02     ` Thomas Gleixner
2008-06-13  7:28       ` Andrew Morton
2008-06-18 19:21   ` Pavel Machek
2008-06-18 20:26     ` Rafael J. Wysocki
2008-06-18 21:58       ` Thomas Gleixner
2008-06-18 22:04         ` Rafael J. Wysocki
2008-06-18 22:17           ` Thomas Gleixner
2008-06-18 22:27             ` Rafael J. Wysocki
2008-06-12 12:31 ` Rafael J. Wysocki [this message]
2008-06-12 12:32   ` [patch 0/6] AMD C1E aware idle support Ingo Molnar
     [not found]     ` <200806131118.31160.rjw@sisk.pl>
2008-06-13 11:52       ` Rafael J. Wysocki
2008-06-12 13:09   ` Thomas Gleixner
2008-06-12 14:24 ` Andreas Herrmann
2008-06-12 15:48   ` Thomas Gleixner
2008-06-14 21:27 ` Maciej W. Rozycki
2008-06-18 22:47 ` Len Brown
2008-07-04 14:35   ` Andreas Herrmann
2008-07-04 15:18     ` [PATCH] x86: emphasize that c1e aware idle stuff is AMD specific Andreas Herrmann
2008-08-05 17:42     ` [patch 0/6] AMD C1E aware idle support Pavel Machek
2008-08-06 13:21       ` Andreas Herrmann

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