From: "Rafael J. Wysocki" <rjw@sisk.pl>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Pavel Machek <pavel@suse.cz>, LKML <linux-kernel@vger.kernel.org>,
Ingo Molnar <mingo@elte.hu>,
Arjan van de Veen <arjan@infradead.org>,
Andreas Herrmann <andreas.herrmann3@amd.com>
Subject: Re: [patch 6/6] x86: add c1e aware idle function
Date: Thu, 19 Jun 2008 00:27:39 +0200 [thread overview]
Message-ID: <200806190027.39749.rjw@sisk.pl> (raw)
In-Reply-To: <alpine.LFD.1.10.0806190012420.3395@apollo.tec.linutronix.de>
On Thursday, 19 of June 2008, Thomas Gleixner wrote:
> On Thu, 19 Jun 2008, Rafael J. Wysocki wrote:
> > On Wednesday, 18 of June 2008, Thomas Gleixner wrote:
> > > On Wed, 18 Jun 2008, Rafael J. Wysocki wrote:
> > > > On Wednesday, 18 of June 2008, Pavel Machek wrote:
> > > > > On Thu 2008-06-12 10:29:00, Thomas Gleixner wrote:
> > > > > > C1E on AMD machines is like C3 but without control from the OS. Up to
> > > > > > now we disabled the local apic timer for those machines as it stops
> > > > > > when the CPU goes into C1E. This excludes those machines from high
> > > > > > resolution timers / dynamic ticks, which hurts especially the X2 based
> > > > > > laptops.
> > > > > >
> > > > > > The current boot time C1E detection has another more serious flaw:
> > > > > > some BIOSes do not enable C1E until the ACPI processor module is
> > > > > > loaded. This causes systems to stop working after that point.
> > > > > >
> > > > > > To work nicely with C1E enabled machines we use a separate idle
> > > > > > function, which checks on idle entry whether C1E was enabled in the
> > > > > > Interrupt Pending Message MSR. This allows us to do timer broadcasting
> > > > >
> > > > > Entering idle is quite a common operation, and reading MSR is quite
> > > > > slow. Is it possible to do better here?
> > > > >
> > > > > What happens if ACPI BIOS toggles MSR on all cpus *while* we are
> > > > > entering idle? This seems inherently racy...
> > >
> > > Well, on most of the machines we see the C1E bit on the first idle
> > > entry either on CPU0 or on CPU1.
> > >
> > > I know of exactly one machine which has the C1E thing enabled late
> > > when the ACPI stuff runs.
> > >
> > > > Yes, and that fits the picture I'm observing on the nx6325 (see the
> > > > "linux-next: Tree for June 13: IO APIC breakage on HP nx6325" thread).
> > >
> > > Hmm, when is the C1E detected on current mainline ? Does the boot CPU
> > > have it or is it when the second CPU comes up ?
> >
> > How can I check that?
>
> When the boot cpu has it then it prints:
>
> "Disabling APIC timer"
It does that.
> when the secondary CPU has it then it prints:
>
> "AMD C1E detected late. Force timer broadcast."
>
> Current mainline does not check for the late ACPI case so I'm pretty
> sure that on your box it is detected during early boot way before we
> can switch to highres/dyntick.
Yes, that's the case.
Thanks,
Rafael
next prev parent reply other threads:[~2008-06-18 22:26 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-06-12 10:28 [patch 0/6] AMD C1E aware idle support Thomas Gleixner
2008-06-12 10:28 ` [patch 1/6] x86: simplify idle selection Thomas Gleixner
2008-06-12 10:28 ` [patch 2/6] x86: cleanup C1E enabled detection Thomas Gleixner
2008-06-12 10:28 ` [patch 3/6] x86: use cpuinfo to check for interrupt pending message msr Thomas Gleixner
2008-06-13 6:55 ` Andreas Herrmann
2008-06-13 12:38 ` Thomas Gleixner
2008-06-13 14:28 ` Andreas Herrmann
2008-06-12 10:28 ` [patch 4/6] x86: use cpuid to check MWAIT support for C1 Thomas Gleixner
2008-06-12 10:28 ` [patch 5/6] x86: move more common idle functions/variables to process.c Thomas Gleixner
2008-06-12 10:29 ` [patch 6/6] x86: add c1e aware idle function Thomas Gleixner
2008-06-13 0:55 ` Andrew Morton
2008-06-13 6:02 ` Thomas Gleixner
2008-06-13 7:28 ` Andrew Morton
2008-06-18 19:21 ` Pavel Machek
2008-06-18 20:26 ` Rafael J. Wysocki
2008-06-18 21:58 ` Thomas Gleixner
2008-06-18 22:04 ` Rafael J. Wysocki
2008-06-18 22:17 ` Thomas Gleixner
2008-06-18 22:27 ` Rafael J. Wysocki [this message]
2008-06-12 12:31 ` [patch 0/6] AMD C1E aware idle support Rafael J. Wysocki
2008-06-12 12:32 ` Ingo Molnar
[not found] ` <200806131118.31160.rjw@sisk.pl>
2008-06-13 11:52 ` Rafael J. Wysocki
2008-06-12 13:09 ` Thomas Gleixner
2008-06-12 14:24 ` Andreas Herrmann
2008-06-12 15:48 ` Thomas Gleixner
2008-06-14 21:27 ` Maciej W. Rozycki
2008-06-18 22:47 ` Len Brown
2008-07-04 14:35 ` Andreas Herrmann
2008-07-04 15:18 ` [PATCH] x86: emphasize that c1e aware idle stuff is AMD specific Andreas Herrmann
2008-08-05 17:42 ` [patch 0/6] AMD C1E aware idle support Pavel Machek
2008-08-06 13:21 ` Andreas Herrmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=200806190027.39749.rjw@sisk.pl \
--to=rjw@sisk.pl \
--cc=andreas.herrmann3@amd.com \
--cc=arjan@infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@elte.hu \
--cc=pavel@suse.cz \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox