Re: [patch 0/6] AMD C1E aware idle support

[Andreas Herrmann <andreas.herrmann3@amd.com>]

On Tue, Aug 05, 2008 at 07:42:18PM +0200, Pavel Machek wrote:
> > > > AMD CPUs with C1E support are currently excluded from high resolution
> > > > timers and NOHZ support. The reason is that C1E is a BIOS controlled
> > > > C3 power state which switches off TSC and the local APIC timer. The
> > > > ACPI C-State control manages the TSC/local APIC timer wreckage, but
> > > > this does not include the C1 based ("halt" instruction) C1E mode. The
> > > > BIOS/SMM controlled C1E state works on most systems even without
> > > > enabling ACPI C-State control.
> > > 
> > > What a mess.
> 
> Yep, seems like AMD is breaking C1 semantics. Is it even valid from
> ACPI spec point of view?
>
> > > What is the measured power savings that justifies this effort?
> > 
> > IMHO the power savings are not that important when such a kernel runs
> > on bare metal:
> 
> Ok, so maybe we should disable C1E to work around its misdesign?

Disabling C1E is not an option. It saves the most power when you have
a multicore AMD CPU. Neither C2 nor C3 are declared here. AMD C1E is
hardware level power management if all cores are in the C1 state.

If you disable C1E and use a NOHZ kernel your power consumption is
higher than using C1E with a periodic timer (say 250 HZ).

> It would be certainly nice to have noc1e command line option...

The sane way to disable it is in the BIOS -- if your BIOS provides
such an option.
Thomas pointed already out that C1E might be enabled later during
boot. So you would have to reset the respective bits whenever you
enter idle. This is ugly and what would be the benefit of this?


Andreas