[PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Chaohong Guo]

Consolidate all magic numbers of hygon CPUs into a header file,
The macros describe the family/model numbers of hygon CPUs.

Signed-off-by: Chaohong Guo <guochaohong@open-hieco.net>
Co-developed-by: Zhiquan Li <lizhiquan@open-hieco.net>
Signed-off-by: Zhiquan Li <lizhiquan@open-hieco.net>
---
 arch/x86/include/asm/cpu_device_id.h   |  2 ++
 arch/x86/include/asm/processor-hygon.h | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 arch/x86/include/asm/processor-hygon.h

diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h
index c62d8fae52c3..447837d15f87 100644
--- a/arch/x86/include/asm/cpu_device_id.h
+++ b/arch/x86/include/asm/cpu_device_id.h
@@ -44,6 +44,8 @@
 #include <asm/intel-family.h>
 /* And the X86_VENDOR_* ones */
 #include <asm/processor.h>
+/* Hygon HFM model defines */
+#include <asm/processor-hygon.h>
 
 /* Centaur FAM6 models */
 #define X86_CENTAUR_FAM6_C7_A		0xa
diff --git a/arch/x86/include/asm/processor-hygon.h b/arch/x86/include/asm/processor-hygon.h
new file mode 100644
index 000000000000..08150e3ea379
--- /dev/null
+++ b/arch/x86/include/asm/processor-hygon.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * The helpers to support Hygon CPU specific code path.
+ */
+
+#ifndef _ASM_X86_PROCESSOR_HYGON_H
+#define _ASM_X86_PROCESSOR_HYGON_H
+
+#include <asm/processor.h>
+
+#define	HFM(_family, _model)	VFM_MAKE(X86_VENDOR_HYGON, _family, _model)
+
+#define	HYGON_F18_M04		HFM(0x18, 4)
+#define	HYGON_F18_M06		HFM(0x18, 6)
+#define	HYGON_F18_M07		HFM(0x18, 7)
+
+
+#define	HYGON_7447V		HYGON_F18_M07
+
+#endif /*  _ASM_X86_PROCESSOR_HYGON_H */
-- 
2.18.2

[PATCH 2/2] sched/numa: Apply remote socket distance averaging for Hygon 7447V

[Chaohong Guo]

On Intel GNR/CWF platforms with SNC3 enabled, the patch:
commit 4d6dd05d07d0 ("sched/topology: Fix sched domain build error
for GNR, CWF in SNC-3 mode") introduced the use of averaged distances
to remote‑socket nodes when constructing scheduling domains. This
helped group remote‑socket NUMA  nodes into the same scheduling group,
 improving load‑balancing decisions

Hygon 7447V (model 7) can contain up to six dies per package. When NPS
(NUMA per socket) is enabled, each package exposes six NUMA nodes. We
observe the same issue as on GNR/CWF: the current domain construction
incorrectly merges nodes from different sockets at higher NUMA levels,
leading to suboptimal remote‑socket CPU selection during load balancing.

The following diagram illustrates the node topology (two packages, six
nodes each):

             package 0                        package 1

           ----------------------------------------------
           |            --------------------            |
           |            |                  |            |
        ------       -------             ------       ------
        |  0  |------|  3  |             | 6  |-------| 9  |
        ------       -------             -----        -----
           |            |                  |            |
        -------      -------             -----        ------
        |  5  |------|  2  |             | 11 |-------| 8  |
        -------      -------             -----        -----
           |            |                  |            |
        -------      -------             -----        ------
        |  4  |------|  1  |             | 10 |-------| 7  |
        ------       -------             -----        ------
           |            |                  |            |
           |            --------------------            |
           ----------------------------------------------

From the perspective of CPUs in node 0, sched domains:
  numa-level 1 : [0]  [3] [5]
  numa-level 2:  [0, 3, 5], [2], [4]
  numa-level 3:  [0, 2, 3, 4, 5], [1, 2, 3, 4, 5]
  numa-level 4:  [0-5], [9]
  numa-level 5:  [0-5, 9], [6], [8]
  numa-level 6:  [0-6, 8, 9], [7], [11]
  numa-level 7:  [0-9], [2-11]

NUMA level 5-7， nodes in different socket are grouped together,which
caused CPUs in remote socket are chosen while load balancing.

For better perfornace, we do the same as Intel is doing on intel GNR/CWF.

Signed-off-by: Chaohong Guo <guochaohong@open-hieco.net>
Co-developed-by: Zhiquan Li <lizhiquan@open-hieco.net>
Signed-off-by: Zhiquan Li <lizhiquan@open-hieco.net>
--
2.18.2
---
 arch/x86/kernel/smpboot.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index cb999feb66b0..c2131277763a 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -678,6 +678,7 @@ int arch_sched_node_distance(int from, int to)
 	switch (boot_cpu_data.x86_vfm) {
 	case INTEL_GRANITERAPIDS_X:
 	case INTEL_ATOM_DARKMONT_X:
+	case HYGON_7447V:
 		if (topology_max_packages() == 1 ||
 		    topology_num_nodes_per_package() < 3)
 			return d;
-- 
2.18.2

Re: [PATCH 2/2] sched/numa: Apply remote socket distance averaging for Hygon 7447V

[Ingo Molnar]

* Chaohong Guo <guochaohong@open-hieco.net> wrote:

> The following diagram illustrates the node topology (two packages, six
> nodes each):
> 
>              package 0                        package 1
> 
>            ----------------------------------------------
>            |            --------------------            |
>            |            |                  |            |
>         ------       -------             ------       ------
>         |  0  |------|  3  |             | 6  |-------| 9  |
>         ------       -------             -----        -----
>            |            |                  |            |
>         -------      -------             -----        ------
>         |  5  |------|  2  |             | 11 |-------| 8  |
>         -------      -------             -----        -----
>            |            |                  |            |
>         -------      -------             -----        ------
>         |  4  |------|  1  |             | 10 |-------| 7  |
>         ------       -------             -----        ------
>            |            |                  |            |
>            |            --------------------            |
>            ----------------------------------------------
> 
> From the perspective of CPUs in node 0, sched domains:
>   numa-level 1 : [0]  [3] [5]
>   numa-level 2:  [0, 3, 5], [2], [4]
>   numa-level 3:  [0, 2, 3, 4, 5], [1, 2, 3, 4, 5]
>   numa-level 4:  [0-5], [9]
>   numa-level 5:  [0-5, 9], [6], [8]
>   numa-level 6:  [0-6, 8, 9], [7], [11]
>   numa-level 7:  [0-9], [2-11]
> 
> NUMA level 5-7， nodes in different socket are grouped together,which
> caused CPUs in remote socket are chosen while load balancing.
> 
> For better perfornace, we do the same as Intel is doing on intel GNR/CWF.

Could you please include the before/after sched domains topology
in the changelog. Looks good otherwise.

Thanks,

	Ingo

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Peter Zijlstra]

On Mon, Aug 03, 2026 at 01:12:47PM +0800, Chaohong Guo wrote:
> Consolidate all magic numbers of hygon CPUs into a header file,
> The macros describe the family/model numbers of hygon CPUs.
> 
> Signed-off-by: Chaohong Guo <guochaohong@open-hieco.net>
> Co-developed-by: Zhiquan Li <lizhiquan@open-hieco.net>
> Signed-off-by: Zhiquan Li <lizhiquan@open-hieco.net>
> ---
>  arch/x86/include/asm/cpu_device_id.h   |  2 ++
>  arch/x86/include/asm/processor-hygon.h | 20 ++++++++++++++++++++
>  2 files changed, 22 insertions(+)
>  create mode 100644 arch/x86/include/asm/processor-hygon.h
> 
> diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h
> index c62d8fae52c3..447837d15f87 100644
> --- a/arch/x86/include/asm/cpu_device_id.h
> +++ b/arch/x86/include/asm/cpu_device_id.h
> @@ -44,6 +44,8 @@
>  #include <asm/intel-family.h>
>  /* And the X86_VENDOR_* ones */
>  #include <asm/processor.h>
> +/* Hygon HFM model defines */
> +#include <asm/processor-hygon.h>

I'll take these, but Boris, should I rename this to hygon-family.h to
match intel-family.h ?

>  
>  /* Centaur FAM6 models */
>  #define X86_CENTAUR_FAM6_C7_A		0xa
> diff --git a/arch/x86/include/asm/processor-hygon.h b/arch/x86/include/asm/processor-hygon.h
> new file mode 100644
> index 000000000000..08150e3ea379
> --- /dev/null
> +++ b/arch/x86/include/asm/processor-hygon.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * The helpers to support Hygon CPU specific code path.
> + */
> +
> +#ifndef _ASM_X86_PROCESSOR_HYGON_H
> +#define _ASM_X86_PROCESSOR_HYGON_H
> +
> +#include <asm/processor.h>
> +
> +#define	HFM(_family, _model)	VFM_MAKE(X86_VENDOR_HYGON, _family, _model)
> +
> +#define	HYGON_F18_M04		HFM(0x18, 4)
> +#define	HYGON_F18_M06		HFM(0x18, 6)
> +#define	HYGON_F18_M07		HFM(0x18, 7)
> +
> +
> +#define	HYGON_7447V		HYGON_F18_M07
> +
> +#endif /*  _ASM_X86_PROCESSOR_HYGON_H */
> -- 
> 2.18.2
> 

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Borislav Petkov]

On Mon, Aug 03, 2026 at 08:10:22AM +0200, Peter Zijlstra wrote:
> On Mon, Aug 03, 2026 at 01:12:47PM +0800, Chaohong Guo wrote:
> > Consolidate all magic numbers of hygon CPUs into a header file,
> > The macros describe the family/model numbers of hygon CPUs.
> > 
> > Signed-off-by: Chaohong Guo <guochaohong@open-hieco.net>
> > Co-developed-by: Zhiquan Li <lizhiquan@open-hieco.net>
> > Signed-off-by: Zhiquan Li <lizhiquan@open-hieco.net>
> > ---
> >  arch/x86/include/asm/cpu_device_id.h   |  2 ++
> >  arch/x86/include/asm/processor-hygon.h | 20 ++++++++++++++++++++
> >  2 files changed, 22 insertions(+)
> >  create mode 100644 arch/x86/include/asm/processor-hygon.h
> > 
> > diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h
> > index c62d8fae52c3..447837d15f87 100644
> > --- a/arch/x86/include/asm/cpu_device_id.h
> > +++ b/arch/x86/include/asm/cpu_device_id.h
> > @@ -44,6 +44,8 @@
> >  #include <asm/intel-family.h>
> >  /* And the X86_VENDOR_* ones */
> >  #include <asm/processor.h>
> > +/* Hygon HFM model defines */
> > +#include <asm/processor-hygon.h>
> 
> I'll take these, but Boris, should I rename this to hygon-family.h to
> match intel-family.h ?

Yah, the defines are called _ASM_X86_INTEL_FAMILY_H there so this better copy
them respectively.

Also, SOB order is wrong. In the other patch too.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Ingo Molnar]

* Chaohong Guo <guochaohong@open-hieco.net> wrote:

> Consolidate all magic numbers of hygon CPUs into a header file,
> The macros describe the family/model numbers of hygon CPUs.

> +#define	HFM(_family, _model)	VFM_MAKE(X86_VENDOR_HYGON, _family, _model)
> +
> +#define	HYGON_F18_M04		HFM(0x18, 4)
> +#define	HYGON_F18_M06		HFM(0x18, 6)
> +#define	HYGON_F18_M07		HFM(0x18, 7)
> +
> +
> +#define	HYGON_7447V		HYGON_F18_M07

So this is a bit misleading, AFAICT "7447V" is the enterprise server
CPU variant - but there's a bunch of smaller server and desktop
CPU variants as well that are named differently:

	Model Name	Core / Thread Count	Base Clock	Target Segment
	----------      ----------------------  ----------      -------------
	7447V		96 Cores / 192 Threads	~2.6 GHz	Enterprise / Cloud Server
	7490H		96 Cores / 192 Threads	—		High-Density Server
	7490		64 Cores / 128 Threads	2.7 GHz		Enterprise Server
	7470		48 Cores /  96 Threads	—		Enterprise Server
	3490		16 Cores /  32 Threads	2.8 GHz		Desktop / Workstation
	3450E		 8 Cores /  16 Threads	3.6 GHz		Workstation / Desktop
	3450G		 8 Cores /  16 Threads	2.7 GHz		Workstation / Desktop

Assuming that this patch does the right thing for all
these smaller variants as well (does it?), shouldn't
the name be something like HYGON_4G or so, given
that the patch applies to the 4th generation Hygon
microarchitecture, not a specific server CPU configuration
such as 7447V?

Thanks,

	Ingo

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Guo Chaohong]

On 8/3/2026 2:10 PM, Peter Zijlstra wrote:
> On Mon, Aug 03, 2026 at 01:12:47PM +0800, Chaohong Guo wrote:
>> Consolidate all magic numbers of hygon CPUs into a header file,
>> The macros describe the family/model numbers of hygon CPUs.
>>
>> Signed-off-by: Chaohong Guo <guochaohong@open-hieco.net>
>> Co-developed-by: Zhiquan Li <lizhiquan@open-hieco.net>
>> Signed-off-by: Zhiquan Li <lizhiquan@open-hieco.net>
>> ---
>>   arch/x86/include/asm/cpu_device_id.h   |  2 ++
>>   arch/x86/include/asm/processor-hygon.h | 20 ++++++++++++++++++++
>>   2 files changed, 22 insertions(+)
>>   create mode 100644 arch/x86/include/asm/processor-hygon.h
>>
>> diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h
>> index c62d8fae52c3..447837d15f87 100644
>> --- a/arch/x86/include/asm/cpu_device_id.h
>> +++ b/arch/x86/include/asm/cpu_device_id.h
>> @@ -44,6 +44,8 @@
>>   #include <asm/intel-family.h>
>>   /* And the X86_VENDOR_* ones */
>>   #include <asm/processor.h>
>> +/* Hygon HFM model defines */
>> +#include <asm/processor-hygon.h>
> I'll take these, but Boris, should I rename this to hygon-family.h to
> match intel-family.h ?


I will rename it to hygon-family.h, fix the SOB order as Boris 
suggested, and then send it out.


-chaohong



>
>>   
>>   /* Centaur FAM6 models */
>>   #define X86_CENTAUR_FAM6_C7_A		0xa
>> diff --git a/arch/x86/include/asm/processor-hygon.h b/arch/x86/include/asm/processor-hygon.h
>> new file mode 100644
>> index 000000000000..08150e3ea379
>> --- /dev/null
>> +++ b/arch/x86/include/asm/processor-hygon.h
>> @@ -0,0 +1,20 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * The helpers to support Hygon CPU specific code path.
>> + */
>> +
>> +#ifndef _ASM_X86_PROCESSOR_HYGON_H
>> +#define _ASM_X86_PROCESSOR_HYGON_H
>> +
>> +#include <asm/processor.h>
>> +
>> +#define	HFM(_family, _model)	VFM_MAKE(X86_VENDOR_HYGON, _family, _model)
>> +
>> +#define	HYGON_F18_M04		HFM(0x18, 4)
>> +#define	HYGON_F18_M06		HFM(0x18, 6)
>> +#define	HYGON_F18_M07		HFM(0x18, 7)
>> +
>> +
>> +#define	HYGON_7447V		HYGON_F18_M07
>> +
>> +#endif /*  _ASM_X86_PROCESSOR_HYGON_H */
>> -- 
>> 2.18.2
>>

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Guo Chaohong]

hi, Ingo,


Hygon model 7 CPUs have either 4 or 6 dies. All 6‑die variants share the 
same interconnect topology.
The Hygon‑4G family includes several model numbers, not just model 7. 
The 3‑series CPUs are designed
for desktop/workstation use and are only available in single‑socket systems.

The following is a summary of key Hygon models:

Model Name   Cores / Threads    Clock Speed   Target Segment           
Model Number
7447V               96 / 192               ~2.6 GHz Enterprise / Cloud 
Server     7
7490H              96 / 192                —  High‑Density Server        
      7 (now 7446)
7490                 64 / 128               2.7 GHz  Enterprise Serve    
                4
7470                 48 / 96                  —  Enterprise Server      
             4

Therefore, we will restrict this patch to apply only to model 7 CPUs 
that have 6 dies on a multi‑socket
system and add sched domains topology after the change into commit 
message  in the V2 patch.


thanks
-chaohong



On 8/3/2026 2:30 PM, Ingo Molnar wrote:
> * Chaohong Guo <guochaohong@open-hieco.net> wrote:
>
>> Consolidate all magic numbers of hygon CPUs into a header file,
>> The macros describe the family/model numbers of hygon CPUs.
>> +#define	HFM(_family, _model)	VFM_MAKE(X86_VENDOR_HYGON, _family, _model)
>> +
>> +#define	HYGON_F18_M04		HFM(0x18, 4)
>> +#define	HYGON_F18_M06		HFM(0x18, 6)
>> +#define	HYGON_F18_M07		HFM(0x18, 7)
>> +
>> +
>> +#define	HYGON_7447V		HYGON_F18_M07
> So this is a bit misleading, AFAICT "7447V" is the enterprise server
> CPU variant - but there's a bunch of smaller server and desktop
> CPU variants as well that are named differently:
>
> 	Model Name	Core / Thread Count	Base Clock	Target Segment
> 	----------      ----------------------  ----------      -------------
> 	7447V		96 Cores / 192 Threads	~2.6 GHz	Enterprise / Cloud Server
> 	7490H		96 Cores / 192 Threads	—		High-Density Server
> 	7490		64 Cores / 128 Threads	2.7 GHz		Enterprise Server
> 	7470		48 Cores /  96 Threads	—		Enterprise Server
> 	3490		16 Cores /  32 Threads	2.8 GHz		Desktop / Workstation
> 	3450E		 8 Cores /  16 Threads	3.6 GHz		Workstation / Desktop
> 	3450G		 8 Cores /  16 Threads	2.7 GHz		Workstation / Desktop
>
> Assuming that this patch does the right thing for all
> these smaller variants as well (does it?), shouldn't
> the name be something like HYGON_4G or so, given
> that the patch applies to the 4th generation Hygon
> microarchitecture, not a specific server CPU configuration
> such as 7447V?
>
> Thanks,
>
> 	Ingo

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Ingo Molnar]

* Guo Chaohong <guochaohong@open-hieco.net> wrote:

> hi, Ingo,
> 
> 
> Hygon model 7 CPUs have either 4 or 6 dies. All 6‑die variants share the
> same interconnect topology.
> The Hygon‑4G family includes several model numbers, not just model 7. The
> 3‑series CPUs are designed
> for desktop/workstation use and are only available in single‑socket systems.
> 
> The following is a summary of key Hygon models:
> 
> Model Name   Cores / Threads    Clock Speed   Target Segment           Model
> Number
> 7447V               96 / 192               ~2.6 GHz Enterprise / Cloud
> Server     7
> 7490H              96 / 192                —  High‑Density Server           
>  7 (now 7446)
> 7490                 64 / 128               2.7 GHz  Enterprise Serve       
>            4
> 7470                 48 / 96                  —  Enterprise Server         
>         4
> 
> Therefore, we will restrict this patch to apply only to model 7 CPUs that
> have 6 dies on a multi‑socket
> system and add sched domains topology after the change into commit message 
> in the V2 patch.

Understood - but my point is that the "HYGON_7447V" symbol name
is inaccurate:

	+#define        HYGON_F18_M07           HFM(0x18, 7)
	+
	+#define        HYGON_7447V             HYGON_F18_M07

Note how 'HYGON_7447V' also covers 7490H/7446.

IMHO it will be less confusing if you skip the HYGON_7447V interim
symbol and just use HYGON_F18_M07 in arch_sched_node_distance(),
and add a comment that clarifies that the additional conditions
basically filter for the 7447V variant.

Or if you want a clean 7447V enumeration function, add it as
an inline function and use that in arch_sched_node_distance().

Both approaches would be acceptable.

Thanks,

	Ingo

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Ingo Molnar]

* Guo Chaohong <guochaohong@open-hieco.net> wrote:

> 
> On 8/3/2026 2:10 PM, Peter Zijlstra wrote:
> > On Mon, Aug 03, 2026 at 01:12:47PM +0800, Chaohong Guo wrote:
> > > Consolidate all magic numbers of hygon CPUs into a header file,
> > > The macros describe the family/model numbers of hygon CPUs.
> > > 
> > > Signed-off-by: Chaohong Guo <guochaohong@open-hieco.net>
> > > Co-developed-by: Zhiquan Li <lizhiquan@open-hieco.net>
> > > Signed-off-by: Zhiquan Li <lizhiquan@open-hieco.net>
> > > ---
> > >   arch/x86/include/asm/cpu_device_id.h   |  2 ++
> > >   arch/x86/include/asm/processor-hygon.h | 20 ++++++++++++++++++++
> > >   2 files changed, 22 insertions(+)
> > >   create mode 100644 arch/x86/include/asm/processor-hygon.h
> > > 
> > > diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h
> > > index c62d8fae52c3..447837d15f87 100644
> > > --- a/arch/x86/include/asm/cpu_device_id.h
> > > +++ b/arch/x86/include/asm/cpu_device_id.h
> > > @@ -44,6 +44,8 @@
> > >   #include <asm/intel-family.h>
> > >   /* And the X86_VENDOR_* ones */
> > >   #include <asm/processor.h>
> > > +/* Hygon HFM model defines */
> > > +#include <asm/processor-hygon.h>
> > I'll take these, but Boris, should I rename this to hygon-family.h to
> > match intel-family.h ?
> 
> 
> I will rename it to hygon-family.h, fix the SOB order as Boris suggested,
> and then send it out.

Please also:

 - Fix the 7447V model confusion problem I mentioned,

 - and take a good look at canonical header guard definition placement
   in existing x86 headers and use that format, not the random placement
   your patch introduces ...

Thanks,

	Ingo

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Guo Chaohong]

On 8/5/2026 1:53 AM, Ingo Molnar wrote:
> * Guo Chaohong <guochaohong@open-hieco.net> wrote:
>
>> hi, Ingo,
>>
>>
>> Hygon model 7 CPUs have either 4 or 6 dies. All 6‑die variants share the
>> same interconnect topology.
>> The Hygon‑4G family includes several model numbers, not just model 7. The
>> 3‑series CPUs are designed
>> for desktop/workstation use and are only available in single‑socket systems.
>>
>> The following is a summary of key Hygon models:
>>
>> Model Name   Cores / Threads    Clock Speed   Target Segment           Model
>> Number
>> 7447V               96 / 192               ~2.6 GHz Enterprise / Cloud
>> Server     7
>> 7490H              96 / 192                —  High‑Density Server
>>   7 (now 7446)
>> 7490                 64 / 128               2.7 GHz  Enterprise Serve
>>             4
>> 7470                 48 / 96                  —  Enterprise Server
>>          4
>>
>> Therefore, we will restrict this patch to apply only to model 7 CPUs that
>> have 6 dies on a multi‑socket
>> system and add sched domains topology after the change into commit message
>> in the V2 patch.
> Understood - but my point is that the "HYGON_7447V" symbol name
> is inaccurate:
>
> 	+#define        HYGON_F18_M07           HFM(0x18, 7)
> 	+
> 	+#define        HYGON_7447V             HYGON_F18_M07
>
> Note how 'HYGON_7447V' also covers 7490H/7446.
>
> IMHO it will be less confusing if you skip the HYGON_7447V interim
> symbol and just use HYGON_F18_M07 in arch_sched_node_distance(),
> and add a comment that clarifies that the additional conditions
> basically filter for the 7447V variant.
>
> Or if you want a clean 7447V enumeration function, add it as
> an inline function and use that in arch_sched_node_distance().
>
> Both approaches would be acceptable.

I will remove 7447V macro from the head file, and just use 
HYGON_F10_M07, and add comments in arch_sched_node_distance() like this: 
case HYGON_F18_M07: /* * Hygon model 7 CPUs have either 4 or 6 compute 
dies (aka CDD). All * 6‑die variants share the same interconnect 
topology. Apply remote * socket distance averaging if the CPU exposes 6 
dies when NPS is * enabled. */ if (topology_num_nodes_per_package() >= 
6) d = slit_cluster_distance(from, to); break;

> Thanks,
>
> 	Ingo

Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers

[Guo Chaohong]

On 8/5/2026 9:35 AM, Guo Chaohong wrote:
> 
> On 8/5/2026 1:53 AM, Ingo Molnar wrote:
>> * Guo Chaohong <guochaohong@open-hieco.net> wrote:
>>
>>> hi, Ingo,
>>>
>>>
>>> Hygon model 7 CPUs have either 4 or 6 dies. All 6‑die variants share the
>>> same interconnect topology.
>>> The Hygon‑4G family includes several model numbers, not just model 7. 
>>> The
>>> 3‑series CPUs are designed
>>> for desktop/workstation use and are only available in single‑socket 
>>> systems.
>>>
>>> The following is a summary of key Hygon models:
>>>
>>> Model Name   Cores / Threads    Clock Speed   Target Segment         
>>>   Model
>>> Number
>>> 7447V               96 / 192               ~2.6 GHz Enterprise / Cloud
>>> Server     7
>>> 7490H              96 / 192                —  High‑Density Server
>>>   7 (now 7446)
>>> 7490                 64 / 128               2.7 GHz  Enterprise Serve
>>>             4
>>> 7470                 48 / 96                  —  Enterprise Server
>>>          4
>>>
>>> Therefore, we will restrict this patch to apply only to model 7 CPUs 
>>> that
>>> have 6 dies on a multi‑socket
>>> system and add sched domains topology after the change into commit 
>>> message
>>> in the V2 patch.
>> Understood - but my point is that the "HYGON_7447V" symbol name
>> is inaccurate:
>>
>>     +#define        HYGON_F18_M07           HFM(0x18, 7)
>>     +
>>     +#define        HYGON_7447V             HYGON_F18_M07
>>
>> Note how 'HYGON_7447V' also covers 7490H/7446.
>>
>> IMHO it will be less confusing if you skip the HYGON_7447V interim
>> symbol and just use HYGON_F18_M07 in arch_sched_node_distance(),
>> and add a comment that clarifies that the additional conditions
>> basically filter for the 7447V variant.
>>
>> Or if you want a clean 7447V enumeration function, add it as
>> an inline function and use that in arch_sched_node_distance().
>>
>> Both approaches would be acceptable.
> 
> I will remove 7447V macro from the head file, and just use 
> HYGON_F10_M07, and add comments in arch_sched_node_distance() like this: 
> case HYGON_F18_M07: /* * Hygon model 7 CPUs have either 4 or 6 compute 
> dies (aka CDD). All * 6‑die variants share the same interconnect 
> topology. Apply remote * socket distance averaging if the CPU exposes 6 
> dies when NPS is * enabled. */ if (topology_num_nodes_per_package() >= 
> 6) d = slit_cluster_distance(from, to); break;
> 
>> Thanks,

sorry,  my email client has some issues.  Re-send it:

I will remove 7447V macro from the head file, and just use 
HYGON_F10_M07, and add comments in arch_sched_node_distance()
like this:

case HYGON_F18_M07:
/*
  * Hygon model 7 CPUs have either 4 or 6 compute dies (aka CDD). All
  * 6‑die variants share the same interconnect topology. Apply remote
  * socket distance averaging if the CPU exposes 6 dies when NPS is
  * enabled.
  */
   if (topology_num_nodes_per_package() >= 6)
           d = slit_cluster_distance(from, to);
   break;

>>     Ingo