[PATCH v2 16/32] hw/arm: phytium: Add Phytium E2000 control region placeholders

[Bin Meng <bin.meng@processmission.com>]

The vendor PBF accesses clock, reset, platform, security, and chip
control windows while bringing up the SoC.

Expose these windows as low-priority unimplemented regions. This
keeps the firmware-visible address map observable and allows later
device models to overlap individual windows without inventing
register semantics.

Signed-off-by: Bin Meng <bin.meng@processmission.com>

---

Changes in v2:
- Make the E2000 SoC own its placeholder regions

 include/hw/arm/phytium_e2000.h |  5 +++++
 hw/arm/phytium_e2000.c         | 25 +++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/include/hw/arm/phytium_e2000.h b/include/hw/arm/phytium_e2000.h
index 6199bb7b5c..15aa1cddd1 100644
--- a/include/hw/arm/phytium_e2000.h
+++ b/include/hw/arm/phytium_e2000.h
@@ -41,6 +41,8 @@ enum {
     PHYTIUM_E2000_UART4,
     PHYTIUM_E2000_UART5,
     PHYTIUM_E2000_UART6,
+    PHYTIUM_E2000_CLK_CTRL,
+    PHYTIUM_E2000_SYSTEM_CTRL,
     PHYTIUM_E2000_GIC_DIST,
     PHYTIUM_E2000_GIC_ITS,
     PHYTIUM_E2000_GIC_REDIST,
@@ -52,6 +54,9 @@ enum {
     PHYTIUM_E2000_GEM1,
     PHYTIUM_E2000_GEM2,
     PHYTIUM_E2000_GEM3,
+    PHYTIUM_E2000_PLATFORM_CTRL,
+    PHYTIUM_E2000_SECURITY_CTRL,
+    PHYTIUM_E2000_CHIP_CTRL,
     PHYTIUM_E2000_BOOT_IACC,
     PHYTIUM_E2000_PCIE_ECAM,
     PHYTIUM_E2000_PCIE_PIO,
diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c
index 6818d081b3..18d64aca69 100644
--- a/hw/arm/phytium_e2000.c
+++ b/hw/arm/phytium_e2000.c
@@ -68,6 +68,8 @@ const MemMapEntry phytium_e2000_memmap[] = {
     [PHYTIUM_E2000_UART4] =          { 0x28014000, 0x00001000 },
     [PHYTIUM_E2000_UART5] =          { 0x2802a000, 0x00001000 },
     [PHYTIUM_E2000_UART6] =          { 0x28032000, 0x00001000 },
+    [PHYTIUM_E2000_CLK_CTRL] =       { 0x28100000, 0x00001000 },
+    [PHYTIUM_E2000_SYSTEM_CTRL] =    { 0x30000000, 0x00001000 },
     [PHYTIUM_E2000_GIC_DIST] =       { 0x30800000, 0x00020000 },
     [PHYTIUM_E2000_GIC_ITS] =        { 0x30820000, 0x00020000 },
     [PHYTIUM_E2000_GIC_REDIST] =     { 0x30880000, 0x00080000 },
@@ -79,6 +81,9 @@ const MemMapEntry phytium_e2000_memmap[] = {
     [PHYTIUM_E2000_GEM1] =           { 0x3200e000, 0x00002000 },
     [PHYTIUM_E2000_GEM2] =           { 0x32010000, 0x00002000 },
     [PHYTIUM_E2000_GEM3] =           { 0x32012000, 0x00002000 },
+    [PHYTIUM_E2000_PLATFORM_CTRL] =  { 0x32e40000, 0x00010000 },
+    [PHYTIUM_E2000_SECURITY_CTRL] =  { 0x32f00000, 0x00001000 },
+    [PHYTIUM_E2000_CHIP_CTRL] =      { 0x33000000, 0x00010000 },
     [PHYTIUM_E2000_BOOT_IACC] =      { 0x38000000, 0x08000000 },
     [PHYTIUM_E2000_PCIE_ECAM] =      { 0x40000000, 0x10000000 },
     [PHYTIUM_E2000_PCIE_PIO] =       { 0x50000000, 0x00f00000 },
@@ -581,6 +586,17 @@ static void phytium_e2000_create_unimplemented(PhytiumE2000SoCState *s)
     phytium_e2000_create_unimplemented_region(
         s, "low-peripheral", "phytium-e2000.low-peripheral",
         PHYTIUM_E2000_LOW_PERIPH);
+    /*
+     * PBF writes clock and reset controls as part of physical SoC bring-up.
+     * QEMU derives virtual clocks and reset state elsewhere, so retaining
+     * placeholder visibility is sufficient for these write-only setup paths.
+     */
+    phytium_e2000_create_unimplemented_region(
+        s, "clock-control", "phytium-e2000.clock-control",
+        PHYTIUM_E2000_CLK_CTRL);
+    phytium_e2000_create_unimplemented_region(
+        s, "system-control", "phytium-e2000.system-control",
+        PHYTIUM_E2000_SYSTEM_CTRL);
     /*
      * PBF programs SoC-specific PCIe PHY and port controls before U-Boot
      * enumerates ECAM. Their values do not affect the generic host bridge, so
@@ -595,6 +611,15 @@ static void phytium_e2000_create_unimplemented(PhytiumE2000SoCState *s)
     phytium_e2000_create_unimplemented_region(
         s, "board-control", "phytium-e2000.board-control",
         PHYTIUM_E2000_BOARD_CTRL);
+    phytium_e2000_create_unimplemented_region(
+        s, "platform-control", "phytium-e2000.platform-control",
+        PHYTIUM_E2000_PLATFORM_CTRL);
+    phytium_e2000_create_unimplemented_region(
+        s, "security-control", "phytium-e2000.security-control",
+        PHYTIUM_E2000_SECURITY_CTRL);
+    phytium_e2000_create_unimplemented_region(
+        s, "chip-control", "phytium-e2000.chip-control",
+        PHYTIUM_E2000_CHIP_CTRL);
 }
 
 static void phytium_e2000_create_cpus(PhytiumE2000SoCState *s)
-- 
2.53.0