[PATCH v2 27/32] hw/arm: phytium: Add Phytium E2000 AHCI controllers

[Bin Meng <bin.meng@processmission.com>]

Add the two single-port sysbus AHCI controllers integrated in the E2000
SoC and route their interrupts to the GIC. Both boards expose the fixed
controller blocks, but Phytium Pi does not wire either controller to a
SATA disk and therefore rejects an IDE backend.

The physical COMe board wires its boot SSD to the second controller.
Attach its SATA backend to AHCI1 so that U-Boot and Linux observe the
same controller order as on hardware.

Signed-off-by: Bin Meng <bin.meng@processmission.com>

---

Changes in v2:
- Move AHCI controllers into the SoC and attach SATA in the machine

 include/hw/arm/phytium_e2000.h | 15 ++++++++++---
 hw/arm/phytium_e2000.c         | 39 ++++++++++++++++++++++++++++++++++
 hw/arm/phytium_e2000_machine.c | 27 +++++++++++++++++++++++
 hw/arm/Kconfig                 |  3 +++
 4 files changed, 81 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/phytium_e2000.h b/include/hw/arm/phytium_e2000.h
index baf9edd261..3d45a82811 100644
--- a/include/hw/arm/phytium_e2000.h
+++ b/include/hw/arm/phytium_e2000.h
@@ -24,9 +24,12 @@
 #define TYPE_PHYTIUM_E2000_SOC "phytium-e2000-soc"
 OBJECT_DECLARE_SIMPLE_TYPE(PhytiumE2000SoCState, PHYTIUM_E2000_SOC)
 
-#define PHYTIUM_E2000_NUM_CPUS 4
-#define PHYTIUM_E2000_NUM_MCIS 2
-#define PHYTIUM_E2000_NUM_GEMS 4
+#define PHYTIUM_E2000_NUM_CPUS        4
+#define PHYTIUM_E2000_NUM_MCIS        2
+#define PHYTIUM_E2000_NUM_GEMS        4
+#define PHYTIUM_E2000_NUM_AHCIS       2
+#define PHYTIUM_E2000_NUM_SATA_PORTS  1
+#define PHYTIUM_E2000_SATA_BOOT_AHCI  1
 
 enum {
     PHYTIUM_E2000_QSPI_DIRECT,
@@ -53,10 +56,12 @@ enum {
     PHYTIUM_E2000_BOARD_CTRL,
     PHYTIUM_E2000_XHCI0,
     PHYTIUM_E2000_XHCI1,
+    PHYTIUM_E2000_AHCI0,
     PHYTIUM_E2000_GEM0,
     PHYTIUM_E2000_GEM1,
     PHYTIUM_E2000_GEM2,
     PHYTIUM_E2000_GEM3,
+    PHYTIUM_E2000_AHCI1,
     PHYTIUM_E2000_RNG_REGS,
     PHYTIUM_E2000_PLATFORM_CTRL,
     PHYTIUM_E2000_SECURITY_CTRL,
@@ -77,6 +82,7 @@ struct PhytiumE2000SoCState {
 
     DeviceState *gic;
     PhytiumE2000QSPIState *qspi;
+    DeviceState *ahci[PHYTIUM_E2000_NUM_AHCIS];
     PhytiumE2000PBRState *pbr;
     PhytiumE2000MciState *mci[PHYTIUM_E2000_NUM_MCIS];
     CadenceGEMState *gem[PHYTIUM_E2000_NUM_GEMS];
@@ -107,5 +113,8 @@ void phytium_e2000_soc_attach_sd_card(PhytiumE2000SoCState *s,
                                       BlockBackend *blk);
 void phytium_e2000_soc_attach_qspi_flash(PhytiumE2000SoCState *s,
                                          DeviceState *flash);
+void phytium_e2000_soc_attach_sata(PhytiumE2000SoCState *s,
+                                   unsigned int index,
+                                   DriveInfo **drives);
 
 #endif
diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c
index 4ded28814e..bc3491ca27 100644
--- a/hw/arm/phytium_e2000.c
+++ b/hw/arm/phytium_e2000.c
@@ -19,6 +19,8 @@
 #include "hw/arm/phytium_e2000.h"
 #include "hw/char/pl011.h"
 #include "hw/core/qdev-properties.h"
+#include "hw/ide/ahci-sysbus.h"
+#include "hw/ide/ide-bus.h"
 #include "hw/intc/arm_gicv3_common.h"
 #include "hw/intc/arm_gicv3_its_common.h"
 #include "hw/i2c/designware_i2c.h"
@@ -85,10 +87,12 @@ const MemMapEntry phytium_e2000_memmap[] = {
     [PHYTIUM_E2000_BOARD_CTRL] =     { 0x31800000, 0x01400000 },
     [PHYTIUM_E2000_XHCI0] =          { 0x31a08000, 0x00018000 },
     [PHYTIUM_E2000_XHCI1] =          { 0x31a28000, 0x00018000 },
+    [PHYTIUM_E2000_AHCI0] =          { 0x31a40000, 0x00001000 },
     [PHYTIUM_E2000_GEM0] =           { 0x3200c000, 0x00002000 },
     [PHYTIUM_E2000_GEM1] =           { 0x3200e000, 0x00002000 },
     [PHYTIUM_E2000_GEM2] =           { 0x32010000, 0x00002000 },
     [PHYTIUM_E2000_GEM3] =           { 0x32012000, 0x00002000 },
+    [PHYTIUM_E2000_AHCI1] =          { 0x32014000, 0x00001000 },
     [PHYTIUM_E2000_RNG_REGS] =       { 0x32a36000, 0x00001000 },
     [PHYTIUM_E2000_PLATFORM_CTRL] =  { 0x32e40000, 0x00010000 },
     [PHYTIUM_E2000_SECURITY_CTRL] =  { 0x32f00000, 0x00001000 },
@@ -124,6 +128,11 @@ static const int phytium_e2000_xhci_irqmap[] = {
     [1] = 17,
 };
 
+static const int phytium_e2000_ahci_irqmap[] = {
+    [0] = 42,
+    [1] = 43,
+};
+
 static const uint8_t phytium_e2000_gem_num_queues[] = { 8, 4, 4, 4 };
 
 static const int
@@ -409,6 +418,22 @@ static void phytium_e2000_create_gem(PhytiumE2000SoCState *s, int index)
     }
 }
 
+static void phytium_e2000_create_ahci(PhytiumE2000SoCState *s, int index)
+{
+    int map_idx = index ? PHYTIUM_E2000_AHCI1 : PHYTIUM_E2000_AHCI0;
+    DeviceState *dev = qdev_new(TYPE_SYSBUS_AHCI);
+    g_autofree char *name = g_strdup_printf("ahci%d", index);
+
+    s->ahci[index] = dev;
+    object_property_add_child(OBJECT(s), name, OBJECT(dev));
+    qdev_prop_set_uint32(dev, "num-ports", PHYTIUM_E2000_NUM_SATA_PORTS);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
+        phytium_e2000_memmap[map_idx].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
+        qdev_get_gpio_in(s->gic, phytium_e2000_ahci_irqmap[index]));
+}
+
 static void phytium_e2000_create_xhci(PhytiumE2000SoCState *s, int index)
 {
     int map_idx = PHYTIUM_E2000_XHCI0 + index;
@@ -815,6 +840,17 @@ void phytium_e2000_soc_attach_qspi_flash(PhytiumE2000SoCState *s,
     qdev_connect_gpio_out_named(DEVICE(s->qspi), "cs", 0, flash_cs);
 }
 
+void phytium_e2000_soc_attach_sata(PhytiumE2000SoCState *s,
+                                   unsigned int index,
+                                   DriveInfo **drives)
+{
+    SysbusAHCIState *sysahci;
+
+    g_assert(index < ARRAY_SIZE(s->ahci));
+    sysahci = SYSBUS_AHCI(s->ahci[index]);
+    ahci_ide_create_devs(&sysahci->ahci, drives);
+}
+
 static void phytium_e2000_soc_realize(DeviceState *dev, Error **errp)
 {
     PhytiumE2000SoCState *s = PHYTIUM_E2000_SOC(dev);
@@ -851,6 +887,9 @@ static void phytium_e2000_soc_realize(DeviceState *dev, Error **errp)
     for (i = 0; i < PHYTIUM_E2000_NUM_XHCIS; i++) {
         phytium_e2000_create_xhci(s, i);
     }
+    for (i = 0; i < PHYTIUM_E2000_NUM_AHCIS; i++) {
+        phytium_e2000_create_ahci(s, i);
+    }
     for (i = 0; i < PHYTIUM_E2000_NUM_GEMS; i++) {
         phytium_e2000_create_gem(s, i);
     }
diff --git a/hw/arm/phytium_e2000_machine.c b/hw/arm/phytium_e2000_machine.c
index 5ca2922e91..9c41403ba9 100644
--- a/hw/arm/phytium_e2000_machine.c
+++ b/hw/arm/phytium_e2000_machine.c
@@ -23,6 +23,7 @@
 #include "hw/arm/phytium_e2000.h"
 #include "hw/core/boards.h"
 #include "hw/core/qdev-properties.h"
+#include "hw/ide/ide-bus.h"
 #include "qom/object.h"
 #include "target/arm/cpu-qom.h"
 
@@ -50,6 +51,7 @@ struct PhytiumE2000MachineClass {
     const char *direct_boot_dtb;
     const char *pbr_boot_mode;
     const char *qspi_flash_model;
+    bool has_sata_boot;
 };
 
 static BlockBackend *phytium_e2000_drive_blk(BlockInterfaceType type,
@@ -84,6 +86,19 @@ static void phytium_e2000_attach_qspi_flash(
     phytium_e2000_soc_attach_qspi_flash(&s->soc, flash);
 }
 
+static void phytium_e2000_attach_sata(PhytiumE2000MachineState *s)
+{
+    DriveInfo *hd[PHYTIUM_E2000_NUM_SATA_PORTS] = {};
+
+    /*
+     * The COMe boot disk is wired to the second fixed AHCI controller. U-Boot
+     * probes both controllers and exposes the only attached disk as scsi 0.
+     */
+    ide_drive_get(hd, ARRAY_SIZE(hd));
+    phytium_e2000_soc_attach_sata(&s->soc,
+                                  PHYTIUM_E2000_SATA_BOOT_AHCI, hd);
+}
+
 static void phytium_e2000_reject_legacy_firmware(
     MachineState *ms, PhytiumE2000MachineClass *pemc)
 {
@@ -217,6 +232,12 @@ static void phytium_e2000_init(MachineState *ms)
         exit(1);
     }
 
+    if (!pemc->has_sata_boot && drive_get_by_index(IF_IDE, 0)) {
+        error_report("%s does not expose a SATA boot disk; "
+                     "use if=sd,index=0", pemc->machine_name);
+        exit(1);
+    }
+
     phytium_e2000_reject_legacy_firmware(ms, pemc);
     phytium_e2000_create_ram(s);
     if (!ms->kernel_filename &&
@@ -239,6 +260,9 @@ static void phytium_e2000_init(MachineState *ms)
     if (pemc->qspi_flash_model) {
         phytium_e2000_attach_qspi_flash(s, pemc->qspi_flash_model);
     }
+    if (pemc->has_sata_boot) {
+        phytium_e2000_attach_sata(s);
+    }
 
     firmware_loaded = phytium_e2000_soc_firmware_loaded(&s->soc);
     s->bootinfo.ram_size = ms->ram_size;
@@ -315,6 +339,7 @@ static void phytium_pi_class_init(ObjectClass *oc, const void *data)
     pemc->machine_name = "phytium-pi";
     pemc->direct_boot_dtb = "phytiumpi_firefly.dtb";
     pemc->pbr_boot_mode = PHYTIUM_E2000_PBR_BOOT_MODE_SD0;
+    pemc->has_sata_boot = false;
 }
 
 static void phytium_e2000_come_class_init(ObjectClass *oc, const void *data)
@@ -324,10 +349,12 @@ static void phytium_e2000_come_class_init(ObjectClass *oc, const void *data)
         PHYTIUM_E2000_MACHINE_CLASS(oc);
 
     mc->desc = "Phytium E2000Q COMe Development Board";
+    mc->block_default_type = IF_IDE;
     pemc->machine_name = "phytium-e2000-come";
     pemc->direct_boot_dtb = "e2000q-come-board.dtb";
     pemc->pbr_boot_mode = PHYTIUM_E2000_PBR_BOOT_MODE_QSPI;
     pemc->qspi_flash_model = "gd25q128";
+    pemc->has_sata_boot = true;
 }
 
 static const TypeInfo phytium_e2000_base_info = {
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 988e8e0327..9b6a1f1d5b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -131,10 +131,13 @@ config PHYTIUM_E2000
     default y
     depends on TCG && AARCH64
     imply PCI_DEVICES
+    select AHCI_SYSBUS
     select ARM_GIC
     select CADENCE
     select DESIGNWARE_I2C
     select DW_MCI
+    select IDE_BUS
+    select IDE_DEV
     select PCI_EXPRESS
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PHYTIUM_E2000_QSPI
-- 
2.53.0