[PATCH v2 02/32] hw/arm: phytium: Add Phytium E2000 PCIe host

[Bin Meng <bin.meng@processmission.com>]

Add the E2000 GPEX host with ECAM, PIO, and 32-bit and 64-bit MMIO
windows. Connect MSI through the ITS and route the four INTx outputs
to GIC SPI 4 through 7.

The vendor device tree masks out the slot number and maps each
interrupt pin directly to the corresponding SPI. Override the GPEX
root-bus IRQ mapper so it selects an output solely by pin. Standard
PCI-to-PCI bridge swizzling remains unchanged.

Expose the SoC-specific PCIe port and PHY control apertures as
low-priority unimplemented regions. Firmware programs these windows
before enumerating ECAM, but their state does not affect the generic
host bridge.

Signed-off-by: Bin Meng <bin.meng@processmission.com>

---

Changes in v2:
- Move the PCIe host into the E2000 SoC

 include/hw/arm/phytium_e2000.h |   6 ++
 hw/arm/phytium_e2000.c         | 111 +++++++++++++++++++++++++++++++++
 hw/arm/Kconfig                 |   3 +
 3 files changed, 120 insertions(+)

diff --git a/include/hw/arm/phytium_e2000.h b/include/hw/arm/phytium_e2000.h
index 466481f629..dcb6c46272 100644
--- a/include/hw/arm/phytium_e2000.h
+++ b/include/hw/arm/phytium_e2000.h
@@ -34,9 +34,15 @@ enum {
     PHYTIUM_E2000_GIC_ITS,
     PHYTIUM_E2000_GIC_REDIST,
     PHYTIUM_E2000_BOOT_SRAM,
+    PHYTIUM_E2000_PCIE_CTRL,
+    PHYTIUM_E2000_PCIE_PHY_CTRL,
     PHYTIUM_E2000_BOARD_CTRL,
     PHYTIUM_E2000_BOOT_IACC,
+    PHYTIUM_E2000_PCIE_ECAM,
+    PHYTIUM_E2000_PCIE_PIO,
+    PHYTIUM_E2000_PCIE_MMIO,
     PHYTIUM_E2000_RAM,
+    PHYTIUM_E2000_PCIE_MMIO_HIGH,
     PHYTIUM_E2000_RAM_HIGH,
 };
 
diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c
index 8c62d0dbdb..ccfd9bad7e 100644
--- a/hw/arm/phytium_e2000.c
+++ b/hw/arm/phytium_e2000.c
@@ -22,6 +22,8 @@
 #include "hw/intc/arm_gicv3_common.h"
 #include "hw/intc/arm_gicv3_its_common.h"
 #include "hw/misc/unimp.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
 #include "qobject/qlist.h"
 #include "qom/object.h"
 #include "target/arm/cpu.h"
@@ -54,9 +56,15 @@ const MemMapEntry phytium_e2000_memmap[] = {
     [PHYTIUM_E2000_GIC_ITS] =        { 0x30820000, 0x00020000 },
     [PHYTIUM_E2000_GIC_REDIST] =     { 0x30880000, 0x00080000 },
     [PHYTIUM_E2000_BOOT_SRAM] =      { 0x30c00000, 0x00100000 },
+    [PHYTIUM_E2000_PCIE_CTRL] =      { 0x31000000, 0x00200000 },
+    [PHYTIUM_E2000_PCIE_PHY_CTRL] =  { 0x31500000, 0x00001000 },
     [PHYTIUM_E2000_BOARD_CTRL] =     { 0x31800000, 0x01400000 },
     [PHYTIUM_E2000_BOOT_IACC] =      { 0x38000000, 0x08000000 },
+    [PHYTIUM_E2000_PCIE_ECAM] =      { 0x40000000, 0x10000000 },
+    [PHYTIUM_E2000_PCIE_PIO] =       { 0x50000000, 0x00f00000 },
+    [PHYTIUM_E2000_PCIE_MMIO] =      { 0x58000000, 0x28000000 },
     [PHYTIUM_E2000_RAM] =            { 0x80000000, 0x80000000 },
+    [PHYTIUM_E2000_PCIE_MMIO_HIGH] = { 0x1000000000ULL, 0x1000000000ULL },
     [PHYTIUM_E2000_RAM_HIGH] =       { 0x2000000000ULL, 0x180000000ULL },
 };
 
@@ -70,6 +78,13 @@ static const int phytium_e2000_uart_irqmap[] = {
     [6] = 107,
 };
 
+static const int phytium_e2000_pcie_irqmap[PCI_NUM_PINS] = {
+    [0] = 4,
+    [1] = 5,
+    [2] = 6,
+    [3] = 7,
+};
+
 typedef enum PhytiumE2000CPUModel {
     PHYTIUM_E2000_CPU_FTC310,
     PHYTIUM_E2000_CPU_FTC664,
@@ -275,6 +290,90 @@ static void phytium_e2000_create_unimplemented_region(
                             phytium_e2000_memmap[map_idx].base, -1000);
 }
 
+/* The vendor DT maps root-bus INTx solely by pin */
+static int phytium_e2000_pcie_map_irq(PCIDevice *pdev, int pin)
+{
+    return pin;
+}
+
+static void phytium_e2000_create_pcie(PhytiumE2000SoCState *s)
+{
+    DeviceState *dev = qdev_new(TYPE_GPEX_HOST);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    MemoryRegion *ecam_alias;
+    MemoryRegion *ecam_reg;
+    MemoryRegion *mmio_alias;
+    MemoryRegion *mmio_high_alias;
+    MemoryRegion *mmio_reg;
+    int i;
+
+    object_property_add_child(OBJECT(s), "pcie", OBJECT(dev));
+
+    /*
+     * GPEX owns generic ECAM, PIO, and MMIO containers. The aliases below
+     * place those containers at the E2000 physical windows that U-Boot scans
+     * and that the SDK device tree publishes to Linux.
+     *
+     * The MMIO container is indexed by PCI bus address, so each alias uses
+     * the physical window base as its source offset to preserve a 1:1 mapping
+     * between CPU and PCI addresses.
+     */
+    qdev_prop_set_uint64(dev, PCI_HOST_ECAM_BASE,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_ECAM].base);
+    qdev_prop_set_uint64(dev, PCI_HOST_ECAM_SIZE,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_ECAM].size);
+    qdev_prop_set_uint64(dev, PCI_HOST_PIO_BASE,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_PIO].base);
+    qdev_prop_set_uint64(dev, PCI_HOST_PIO_SIZE,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_PIO].size);
+    qdev_prop_set_uint64(dev, PCI_HOST_BELOW_4G_MMIO_BASE,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO].base);
+    qdev_prop_set_uint64(dev, PCI_HOST_BELOW_4G_MMIO_SIZE,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO].size);
+    qdev_prop_set_uint64(dev, PCI_HOST_ABOVE_4G_MMIO_BASE,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO_HIGH].base);
+    qdev_prop_set_uint64(dev, PCI_HOST_ABOVE_4G_MMIO_SIZE,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO_HIGH].size);
+
+    sysbus_realize_and_unref(sbd, &error_fatal);
+    pci_bus_map_irqs(PCI_HOST_BRIDGE(dev)->bus,
+                     phytium_e2000_pcie_map_irq);
+
+    ecam_alias = g_new0(MemoryRegion, 1);
+    ecam_reg = sysbus_mmio_get_region(sbd, 0);
+    memory_region_init_alias(ecam_alias, OBJECT(dev), "phytium-pcie-ecam",
+        ecam_reg, 0, phytium_e2000_memmap[PHYTIUM_E2000_PCIE_ECAM].size);
+    memory_region_add_subregion(get_system_memory(),
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_ECAM].base, ecam_alias);
+
+    mmio_alias = g_new0(MemoryRegion, 1);
+    mmio_reg = sysbus_mmio_get_region(sbd, 1);
+    memory_region_init_alias(mmio_alias, OBJECT(dev), "phytium-pcie-mmio",
+        mmio_reg,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO].base,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO].size);
+    memory_region_add_subregion(get_system_memory(),
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO].base,
+        mmio_alias);
+
+    mmio_high_alias = g_new0(MemoryRegion, 1);
+    memory_region_init_alias(mmio_high_alias, OBJECT(dev),
+        "phytium-pcie-mmio-high", mmio_reg,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO_HIGH].base,
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO_HIGH].size);
+    memory_region_add_subregion(get_system_memory(),
+        phytium_e2000_memmap[PHYTIUM_E2000_PCIE_MMIO_HIGH].base,
+        mmio_high_alias);
+
+    sysbus_mmio_map(sbd, 2, phytium_e2000_memmap[PHYTIUM_E2000_PCIE_PIO].base);
+
+    for (i = 0; i < PCI_NUM_PINS; i++) {
+        sysbus_connect_irq(sbd, i,
+            qdev_get_gpio_in(s->gic, phytium_e2000_pcie_irqmap[i]));
+        gpex_set_irq_num(GPEX_HOST(dev), i, phytium_e2000_pcie_irqmap[i]);
+    }
+}
+
 static void phytium_e2000_create_unimplemented(PhytiumE2000SoCState *s)
 {
     /*
@@ -285,6 +384,17 @@ static void phytium_e2000_create_unimplemented(PhytiumE2000SoCState *s)
     phytium_e2000_create_unimplemented_region(
         s, "low-peripheral", "phytium-e2000.low-peripheral",
         PHYTIUM_E2000_LOW_PERIPH);
+    /*
+     * PBF programs SoC-specific PCIe PHY and port controls before U-Boot
+     * enumerates ECAM. Their values do not affect the generic host bridge, so
+     * keep this control aperture visible without inventing register behavior.
+     */
+    phytium_e2000_create_unimplemented_region(
+        s, "pcie-control", "phytium-e2000.pcie-control",
+        PHYTIUM_E2000_PCIE_CTRL);
+    phytium_e2000_create_unimplemented_region(
+        s, "pcie-phy-control", "phytium-e2000.pcie-phy-control",
+        PHYTIUM_E2000_PCIE_PHY_CTRL);
     phytium_e2000_create_unimplemented_region(
         s, "board-control", "phytium-e2000.board-control",
         PHYTIUM_E2000_BOARD_CTRL);
@@ -369,6 +479,7 @@ static void phytium_e2000_soc_realize(DeviceState *dev, Error **errp)
     for (i = 0; i < PHYTIUM_E2000_NUM_UARTS; i++) {
         phytium_e2000_create_uart(s, i);
     }
+    phytium_e2000_create_pcie(s);
 }
 
 static void phytium_e2000_soc_class_init(ObjectClass *oc, const void *data)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 05676534c2..7bc85f4f9f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -130,7 +130,10 @@ config PHYTIUM_E2000
     bool
     default y
     depends on TCG && AARCH64
+    imply PCI_DEVICES
     select ARM_GIC
+    select PCI_EXPRESS
+    select PCI_EXPRESS_GENERIC_BRIDGE
     select PL011
     select UNIMP
 
-- 
2.53.0