* [U-Boot] [PATCH 0/2] am33xx/am437x u-boot DDR init fixes
@ 2016-07-21 11:28 Russ Dill
2016-07-21 11:28 ` [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement Russ Dill
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Russ Dill @ 2016-07-21 11:28 UTC (permalink / raw)
To: u-boot
This patch set fixes a small pair of DDR init issues on am33xx and
am437x platforms. These issue lead an L3 noc error on am437x
platforms that is reported once the kernel boots.
Russ Dill (2):
ARM: am33xx: Fix DDR init delay placement
ARM: am33xx: Always inhibit init/refresh during DDR phy init
arch/arm/cpu/armv7/am33xx/ddr.c | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
--
2.8.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement
2016-07-21 11:28 [U-Boot] [PATCH 0/2] am33xx/am437x u-boot DDR init fixes Russ Dill
@ 2016-07-21 11:28 ` Russ Dill
2016-07-22 13:42 ` Tom Rini
2016-07-26 2:32 ` [U-Boot] [U-Boot, " Tom Rini
2016-07-21 11:28 ` [U-Boot] [PATCH 2/2] ARM: am33xx: Always inhibit init/refresh during DDR phy init Russ Dill
2016-07-22 13:42 ` [U-Boot] [PATCH 0/2] am33xx/am437x u-boot DDR init fixes Tom Rini
2 siblings, 2 replies; 9+ messages in thread
From: Russ Dill @ 2016-07-21 11:28 UTC (permalink / raw)
To: u-boot
The delay needs to be before the write to ref_ctrl register
which initiates refreshes. An improper initialization sequence
generates an L3 noc error.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
---
arch/arm/cpu/armv7/am33xx/ddr.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 888cf1f..ef1fc4d 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -120,12 +120,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+
+ /* Wait 1ms because of L3 timeout error */
+ udelay(1000);
+
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
/* Perform hardware leveling for DDR3 */
if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
- udelay(1000);
writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
--
2.8.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement
2016-07-21 11:28 ` [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement Russ Dill
@ 2016-07-22 13:42 ` Tom Rini
2016-07-26 2:32 ` [U-Boot] [U-Boot, " Tom Rini
1 sibling, 0 replies; 9+ messages in thread
From: Tom Rini @ 2016-07-22 13:42 UTC (permalink / raw)
To: u-boot
On Thu, Jul 21, 2016 at 04:28:31AM -0700, Russ Dill wrote:
> The delay needs to be before the write to ref_ctrl register
> which initiates refreshes. An improper initialization sequence
> generates an L3 noc error.
>
> Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [U-Boot, 1/2] ARM: am33xx: Fix DDR init delay placement
2016-07-21 11:28 ` [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement Russ Dill
2016-07-22 13:42 ` Tom Rini
@ 2016-07-26 2:32 ` Tom Rini
1 sibling, 0 replies; 9+ messages in thread
From: Tom Rini @ 2016-07-26 2:32 UTC (permalink / raw)
To: u-boot
On Thu, Jul 21, 2016 at 04:28:31AM -0700, Russ Dill wrote:
> The delay needs to be before the write to ref_ctrl register
> which initiates refreshes. An improper initialization sequence
> generates an L3 noc error.
>
> Signed-off-by: Russ Dill <Russ.Dill@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] ARM: am33xx: Always inhibit init/refresh during DDR phy init
2016-07-21 11:28 [U-Boot] [PATCH 0/2] am33xx/am437x u-boot DDR init fixes Russ Dill
2016-07-21 11:28 ` [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement Russ Dill
@ 2016-07-21 11:28 ` Russ Dill
2016-07-22 13:42 ` Tom Rini
2016-07-26 2:32 ` [U-Boot] [U-Boot, " Tom Rini
2016-07-22 13:42 ` [U-Boot] [PATCH 0/2] am33xx/am437x u-boot DDR init fixes Tom Rini
2 siblings, 2 replies; 9+ messages in thread
From: Russ Dill @ 2016-07-21 11:28 UTC (permalink / raw)
To: u-boot
A couple of commits have modified the am33xx/am437x ddr2/ddr3
initialization path to fix certain issues, but have had the side effect
of causing L3 noc errors during initialization. The two commits are:
69b918 "am33xx,ddr3: fix ddr3 sdram configuration"
fc46ba "arm: am437x: Enable hardware leveling for EMIF"
The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all
platforms. This delays initialization and refresh until a later stage.
The 500us timer can be programmed for platforms that require it
and for platforms that don't require it. It is currently hardcoded
for 400MHz systems. For systems with a higher memory frequency
this needs to be a larger value, and for systems with a lower
memory frequency this can be a lower value. This can be
considered a separate issue and corrected in a later commit.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
---
arch/arm/cpu/armv7/am33xx/ddr.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index ef1fc4d..6acf30c 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -292,19 +292,14 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
/*
- * Disable initialization and refreshes for now until we
- * finish programming EMIF regs.
- * Also set time between rising edge of DDR_RESET to rising
- * edge of DDR_CKE to > 500us per memory spec.
+ * Disable initialization and refreshes for now until we finish
+ * programming EMIF regs and set time between rising edge of
+ * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
+ * We currently hardcode a value based on a max expected frequency
+ * of 400MHz.
*/
-#ifndef CONFIG_AM43XX
- setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
- EMIF_REG_INITREF_DIS_MASK);
-#endif
- if (regs->zq_config)
- /* Set time between rising edge of DDR_RESET to rising
- * edge of DDR_CKE to > 500us per memory spec. */
- writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
+ &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);
--
2.8.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 2/2] ARM: am33xx: Always inhibit init/refresh during DDR phy init
2016-07-21 11:28 ` [U-Boot] [PATCH 2/2] ARM: am33xx: Always inhibit init/refresh during DDR phy init Russ Dill
@ 2016-07-22 13:42 ` Tom Rini
2016-07-26 2:32 ` [U-Boot] [U-Boot, " Tom Rini
1 sibling, 0 replies; 9+ messages in thread
From: Tom Rini @ 2016-07-22 13:42 UTC (permalink / raw)
To: u-boot
On Thu, Jul 21, 2016 at 04:28:32AM -0700, Russ Dill wrote:
> A couple of commits have modified the am33xx/am437x ddr2/ddr3
> initialization path to fix certain issues, but have had the side effect
> of causing L3 noc errors during initialization. The two commits are:
>
> 69b918 "am33xx,ddr3: fix ddr3 sdram configuration"
> fc46ba "arm: am437x: Enable hardware leveling for EMIF"
>
> The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all
> platforms. This delays initialization and refresh until a later stage.
> The 500us timer can be programmed for platforms that require it
> and for platforms that don't require it. It is currently hardcoded
> for 400MHz systems. For systems with a higher memory frequency
> this needs to be a larger value, and for systems with a lower
> memory frequency this can be a lower value. This can be
> considered a separate issue and corrected in a later commit.
>
> Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [U-Boot, 2/2] ARM: am33xx: Always inhibit init/refresh during DDR phy init
2016-07-21 11:28 ` [U-Boot] [PATCH 2/2] ARM: am33xx: Always inhibit init/refresh during DDR phy init Russ Dill
2016-07-22 13:42 ` Tom Rini
@ 2016-07-26 2:32 ` Tom Rini
1 sibling, 0 replies; 9+ messages in thread
From: Tom Rini @ 2016-07-26 2:32 UTC (permalink / raw)
To: u-boot
On Thu, Jul 21, 2016 at 04:28:32AM -0700, Russ Dill wrote:
> A couple of commits have modified the am33xx/am437x ddr2/ddr3
> initialization path to fix certain issues, but have had the side effect
> of causing L3 noc errors during initialization. The two commits are:
>
> 69b918 "am33xx,ddr3: fix ddr3 sdram configuration"
> fc46ba "arm: am437x: Enable hardware leveling for EMIF"
>
> The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all
> platforms. This delays initialization and refresh until a later stage.
> The 500us timer can be programmed for platforms that require it
> and for platforms that don't require it. It is currently hardcoded
> for 400MHz systems. For systems with a higher memory frequency
> this needs to be a larger value, and for systems with a lower
> memory frequency this can be a lower value. This can be
> considered a separate issue and corrected in a later commit.
>
> Signed-off-by: Russ Dill <Russ.Dill@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 0/2] am33xx/am437x u-boot DDR init fixes
2016-07-21 11:28 [U-Boot] [PATCH 0/2] am33xx/am437x u-boot DDR init fixes Russ Dill
2016-07-21 11:28 ` [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement Russ Dill
2016-07-21 11:28 ` [U-Boot] [PATCH 2/2] ARM: am33xx: Always inhibit init/refresh during DDR phy init Russ Dill
@ 2016-07-22 13:42 ` Tom Rini
2016-07-23 0:31 ` Russ Dill
2 siblings, 1 reply; 9+ messages in thread
From: Tom Rini @ 2016-07-22 13:42 UTC (permalink / raw)
To: u-boot
On Thu, Jul 21, 2016 at 04:28:30AM -0700, Russ Dill wrote:
> This patch set fixes a small pair of DDR init issues on am33xx and
> am437x platforms. These issue lead an L3 noc error on am437x
> platforms that is reported once the kernel boots.
What is the set of platforms you tested all of these on? Thanks!
--
Tom
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2016-07-21 11:28 [U-Boot] [PATCH 0/2] am33xx/am437x u-boot DDR init fixes Russ Dill
2016-07-21 11:28 ` [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement Russ Dill
2016-07-22 13:42 ` Tom Rini
2016-07-26 2:32 ` [U-Boot] [U-Boot, " Tom Rini
2016-07-21 11:28 ` [U-Boot] [PATCH 2/2] ARM: am33xx: Always inhibit init/refresh during DDR phy init Russ Dill
2016-07-22 13:42 ` Tom Rini
2016-07-26 2:32 ` [U-Boot] [U-Boot, " Tom Rini
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