From: tien.fong.chee@intel.com
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Meng Tingting <tingting.meng@intel.com>,
Yuslaimi Alif Zakuan <alif.zakuan.yuslaimi@intel.com>,
Hea Kok Kiang <kok.kiang.hea@intel.com>,
Tien Fong Chee <tien.fong.chee@intel.com>
Subject: [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot
Date: Fri, 20 Sep 2024 15:02:22 +0800 [thread overview]
Message-ID: <20240920070242.20884-1-tien.fong.chee@intel.com> (raw)
From: Tien Fong Chee <tien.fong.chee@intel.com>
This patch set introduces boot support for the Altera SoCFPGA Agilex 5
platform in U-Boot. The changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot (UBI/UBIFS)
and RAM boot (TFTP & ARM DS debugger).
Alif Zakuan Yuslaimi (1):
configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS
Tien Fong Chee (18):
arm: socfpga: agilex5: Add new system manager base addresses
arm: socfpga: Add support for agilex5 clock manager
linker: Add SPL linker script for SoC64 devices
arm: socfpga: agilex5: Add low level initialization
arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device
arm: dts: agilex5: Add HPS cache coherency unit configuration settings
arm: dts: agilex5: Add firewall configure settings
arm: dts: agilex5: Enable XGMAC
sysreset: Add reset support to SoCFPGA Agilex5 device
arm: socfpga: agilex5: Enable cache flush for system memory cache in
CCU
arm: socfpga: agilex5: Add SMMU initialization
arm: socfpga: agilex5: Update CPU info
arm: socfpga: Export board ID as U-Boot environment variable
configs: agilex5: Add configuration for malloc pool
arm: socfpga: smc: Add memory coherency support to mailbox command
arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA
configs: socfpga: soc64: agilex5: Enable XGMAC
arm: socfpga: soc64: Add support for board_boot_order()
Tingting Meng (1):
ddr: altera: Add DDR driver for Agilex5 series
MAINTAINERS | 2 +
arch/arm/Kconfig | 1 +
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 660 ++++++++++++++++++
arch/arm/dts/socfpga_agilex5.dtsi | 7 +
.../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 33 +
arch/arm/mach-socfpga/Makefile | 6 +
arch/arm/mach-socfpga/ccu_ncore3.c | 64 ++
arch/arm/mach-socfpga/include/mach/firewall.h | 23 +-
.../mach-socfpga/include/mach/handoff_soc64.h | 4 +-
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
.../include/mach/reset_manager_soc64.h | 12 +-
.../include/mach/system_manager_soc64.h | 129 ++--
arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 57 ++
arch/arm/mach-socfpga/misc.c | 24 +-
arch/arm/mach-socfpga/misc_soc64.c | 12 +-
arch/arm/mach-socfpga/smc_api.c | 13 +-
arch/arm/mach-socfpga/spl_agilex5.c | 84 +++
arch/arm/mach-socfpga/spl_soc64.c | 120 +++-
arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 80 +++
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 10 +-
configs/socfpga_agilex5_defconfig | 6 +
drivers/ddr/altera/Makefile | 1 +
drivers/ddr/altera/iossm_mailbox.c | 613 ++++++++++++++++
drivers/ddr/altera/iossm_mailbox.h | 186 +++++
drivers/ddr/altera/sdram_agilex5.c | 377 ++++++++++
drivers/ddr/altera/sdram_soc64.c | 78 ++-
drivers/ddr/altera/sdram_soc64.h | 32 +-
drivers/sysreset/Kconfig | 7 +
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_socfpga_agilex5.c | 47 ++
include/configs/socfpga_soc64_common.h | 5 +
31 files changed, 2605 insertions(+), 90 deletions(-)
create mode 100644 arch/arm/mach-socfpga/ccu_ncore3.c
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S
create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c
create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds
create mode 100644 drivers/ddr/altera/iossm_mailbox.c
create mode 100644 drivers/ddr/altera/iossm_mailbox.h
create mode 100644 drivers/ddr/altera/sdram_agilex5.c
create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c
--
2.25.1
next reply other threads:[~2024-09-20 7:03 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-20 7:02 tien.fong.chee [this message]
2024-09-20 7:02 ` [PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses tien.fong.chee
2024-09-21 13:47 ` Marek Vasut
2024-09-24 4:45 ` Chee, Tien Fong
2024-09-24 18:35 ` Marek Vasut
2024-09-20 7:02 ` [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager tien.fong.chee
2024-09-21 13:47 ` Marek Vasut
2024-09-24 5:58 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices tien.fong.chee
2024-09-21 13:48 ` Marek Vasut
2024-09-24 5:48 ` Chee, Tien Fong
2024-09-24 18:35 ` Marek Vasut
2024-09-25 6:06 ` Chee, Tien Fong
2024-09-25 12:50 ` Marek Vasut
2024-09-20 7:02 ` [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization tien.fong.chee
2024-09-21 13:49 ` Marek Vasut
2024-09-24 3:14 ` Chee, Tien Fong
2024-09-24 18:32 ` Marek Vasut
2024-09-25 5:40 ` Chee, Tien Fong
2024-09-25 12:50 ` Marek Vasut
2024-09-26 6:02 ` Chee, Tien Fong
2024-09-26 22:37 ` Marek Vasut
2024-09-27 4:53 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 05/20] arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 06/20] arm: dts: agilex5: Add HPS cache coherency unit configuration settings tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 07/20] arm: dts: agilex5: Add firewall configure settings tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC tien.fong.chee
2024-09-21 13:50 ` Marek Vasut
2024-09-24 6:02 ` Chee, Tien Fong
2024-09-24 18:36 ` Marek Vasut
2024-09-25 6:13 ` Chee, Tien Fong
2024-09-25 12:51 ` Marek Vasut
2024-09-26 5:43 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device tien.fong.chee
2024-09-21 13:51 ` Marek Vasut
2024-09-24 8:52 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 10/20] arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 11/20] arm: socfpga: agilex5: Add SMMU initialization tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info tien.fong.chee
2024-09-21 13:53 ` Marek Vasut
2024-09-24 6:05 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable tien.fong.chee
2024-09-21 13:53 ` Marek Vasut
2024-09-24 7:30 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 14/20] configs: agilex5: Add configuration for malloc pool tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command tien.fong.chee
2024-09-21 13:58 ` Marek Vasut
2024-09-24 6:03 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 16/20] ddr: altera: Add DDR driver for Agilex5 series tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 17/20] arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 19/20] arm: socfpga: soc64: Add support for board_boot_order() tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 20/20] configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS tien.fong.chee
2024-09-20 7:25 ` [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot Simon Glass
2024-09-20 7:30 ` Chee, Tien Fong
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