From: tien.fong.chee@intel.com
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Meng Tingting <tingting.meng@intel.com>,
Yuslaimi Alif Zakuan <alif.zakuan.yuslaimi@intel.com>,
Hea Kok Kiang <kok.kiang.hea@intel.com>,
Tien Fong Chee <tien.fong.chee@intel.com>
Subject: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices
Date: Fri, 20 Sep 2024 15:02:25 +0800 [thread overview]
Message-ID: <20240920070242.20884-4-tien.fong.chee@intel.com> (raw)
In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com>
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add a new .data section for preserving the original state of the
.data section of SoC64 SPL. This new .data section is required to
make SPL reentrant after warm reset.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 80 ++++++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds
diff --git a/arch/arm/mach-socfpga/u-boot-spl-soc64.lds b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds
new file mode 100644
index 00000000000..91cf8dd3139
--- /dev/null
+++ b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ __image_copy_start = ADDR(.text);
+ .text : {
+ . = ALIGN(8);
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ } >.sram
+
+ .rodata : {
+ . = ALIGN(8);
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } >.sram
+
+ .data : {
+ . = ALIGN(8);
+ /* Run time .data section starting at this location */
+ __data_start = .;
+ *(.data*)
+ /* Run time .data section ending at this location */
+ __data_end = .;
+ } >.sram
+
+ . = ALIGN(8);
+ /* Preserve original .data section starting at this location */
+ __preserve_data_start = .;
+ . = __preserve_data_start + (__data_end - __data_start);
+ /* Preserve original .data section ending at this location */
+ __preserve_data_end = .;
+
+ . = ALIGN(8);
+ __u_boot_list . : {
+ KEEP(*(SORT(__u_boot_list*)));
+ } >.sram
+
+ . = ALIGN(8);
+ __image_copy_end = .;
+
+ _end = .;
+
+ _image_binary_end = .;
+
+ .bss : {
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(8);
+ __bss_end = .;
+ } >.sdram
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
--
2.25.1
next prev parent reply other threads:[~2024-09-20 7:03 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-20 7:02 [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses tien.fong.chee
2024-09-21 13:47 ` Marek Vasut
2024-09-24 4:45 ` Chee, Tien Fong
2024-09-24 18:35 ` Marek Vasut
2024-09-20 7:02 ` [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager tien.fong.chee
2024-09-21 13:47 ` Marek Vasut
2024-09-24 5:58 ` Chee, Tien Fong
2024-09-20 7:02 ` tien.fong.chee [this message]
2024-09-21 13:48 ` [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices Marek Vasut
2024-09-24 5:48 ` Chee, Tien Fong
2024-09-24 18:35 ` Marek Vasut
2024-09-25 6:06 ` Chee, Tien Fong
2024-09-25 12:50 ` Marek Vasut
2024-09-20 7:02 ` [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization tien.fong.chee
2024-09-21 13:49 ` Marek Vasut
2024-09-24 3:14 ` Chee, Tien Fong
2024-09-24 18:32 ` Marek Vasut
2024-09-25 5:40 ` Chee, Tien Fong
2024-09-25 12:50 ` Marek Vasut
2024-09-26 6:02 ` Chee, Tien Fong
2024-09-26 22:37 ` Marek Vasut
2024-09-27 4:53 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 05/20] arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 06/20] arm: dts: agilex5: Add HPS cache coherency unit configuration settings tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 07/20] arm: dts: agilex5: Add firewall configure settings tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC tien.fong.chee
2024-09-21 13:50 ` Marek Vasut
2024-09-24 6:02 ` Chee, Tien Fong
2024-09-24 18:36 ` Marek Vasut
2024-09-25 6:13 ` Chee, Tien Fong
2024-09-25 12:51 ` Marek Vasut
2024-09-26 5:43 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device tien.fong.chee
2024-09-21 13:51 ` Marek Vasut
2024-09-24 8:52 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 10/20] arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 11/20] arm: socfpga: agilex5: Add SMMU initialization tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info tien.fong.chee
2024-09-21 13:53 ` Marek Vasut
2024-09-24 6:05 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable tien.fong.chee
2024-09-21 13:53 ` Marek Vasut
2024-09-24 7:30 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 14/20] configs: agilex5: Add configuration for malloc pool tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command tien.fong.chee
2024-09-21 13:58 ` Marek Vasut
2024-09-24 6:03 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 16/20] ddr: altera: Add DDR driver for Agilex5 series tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 17/20] arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 19/20] arm: socfpga: soc64: Add support for board_boot_order() tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 20/20] configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS tien.fong.chee
2024-09-20 7:25 ` [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot Simon Glass
2024-09-20 7:30 ` Chee, Tien Fong
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