From: tien.fong.chee@intel.com
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Meng Tingting <tingting.meng@intel.com>,
Yuslaimi Alif Zakuan <alif.zakuan.yuslaimi@intel.com>,
Hea Kok Kiang <kok.kiang.hea@intel.com>,
Tien Fong Chee <tien.fong.chee@intel.com>
Subject: [PATCH v1 07/20] arm: dts: agilex5: Add firewall configure settings
Date: Fri, 20 Sep 2024 15:02:29 +0800 [thread overview]
Message-ID: <20240920070242.20884-8-tien.fong.chee@intel.com> (raw)
In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com>
From: Tien Fong Chee <tien.fong.chee@intel.com>
These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 166 +++++++++++++++++++++++
1 file changed, 166 insertions(+)
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index ec42fd01a9c..bf30b3b8858 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -221,6 +221,172 @@
bootph-all;
};
};
+
+ socfpga_firewall_config: socfpga-firewall-config {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* L4 peripherals firewall */
+ noc_fw_l4_per@10d21000 {
+ reg = <0x10d21000 0x0000008c>;
+ intel,offset-settings =
+ /* NAND */
+ <0x00000000 0x01010001 0x01010001>,
+ /* USB0 */
+ <0x0000000c 0x01010001 0x01010001>,
+ /* USB1 */
+ <0x00000010 0x01010001 0x01010001>,
+ /* SPI_MAIN0 */
+ <0x0000001c 0x01010301 0x01010301>,
+ /* SPI_MAIN1 */
+ <0x00000020 0x01010301 0x01010301>,
+ /* SPI_SECONDARY0 */
+ <0x00000024 0x01010301 0x01010301>,
+ /* SPI_SECONDARY1 */
+ <0x00000028 0x01010301 0x01010301>,
+ /* EMAC0 */
+ <0x0000002c 0x01010001 0x01010001>,
+ /* EMAC1 */
+ <0x00000030 0x01010001 0x01010001>,
+ /* EMAC2 */
+ <0x00000034 0x01010001 0x01010001>,
+ /* SDMMC */
+ <0x00000040 0x01010001 0x01010001>,
+ /* GPIO0 */
+ <0x00000044 0x01010301 0x01010301>,
+ /* GPIO1 */
+ <0x00000048 0x01010301 0x01010301>,
+ /* I2C0 */
+ <0x00000050 0x01010301 0x01010301>,
+ /* I2C1 */
+ <0x00000054 0x01010301 0x01010301>,
+ /* I2C2 */
+ <0x00000058 0x01010301 0x01010301>,
+ /* I2C3 */
+ <0x0000005c 0x01010301 0x01010301>,
+ /* I2C4 */
+ <0x00000060 0x01010301 0x01010301>,
+ /* SP_TIMER0 */
+ <0x00000064 0x01010301 0x01010301>,
+ /* SP_TIMER1 */
+ <0x00000068 0x01010301 0x01010301>,
+ /* UART0 */
+ <0x0000006c 0x01010301 0x01010301>,
+ /* UART1 */
+ <0x00000070 0x01010301 0x01010301>,
+ /* I3C0 */
+ <0x00000074 0x01010301 0x01010301>,
+ /* I3C1 */
+ <0x00000078 0x01010301 0x01010301>,
+ /* DMA0 */
+ <0x0000007c 0x01010001 0x01010001>,
+ /* DMA1 */
+ <0x00000080 0x01010001 0x01010001>,
+ /* COMBO_PHY */
+ <0x00000084 0x01010001 0x01010001>,
+ /* NAND_SDMA */
+ <0x00000088 0x01010301 0x01010301>;
+ bootph-all;
+ };
+
+ /* L4 system firewall */
+ noc_fw_l4_sys@10d21100 {
+ reg = <0x10d21100 0x00000098>;
+ intel,offset-settings =
+ /* DMA_ECC */
+ <0x00000008 0x01010001 0x01010001>,
+ /* EMAC0RX_ECC */
+ <0x0000000c 0x01010001 0x01010001>,
+ /* EMAC0TX_ECC */
+ <0x00000010 0x01010001 0x01010001>,
+ /* EMAC1RX_ECC */
+ <0x00000014 0x01010001 0x01010001>,
+ /* EMAC1TX_ECC */
+ <0x00000018 0x01010001 0x01010001>,
+ /* EMAC2RX_ECC */
+ <0x0000001c 0x01010001 0x01010001>,
+ /* EMAC2TX_ECC */
+ <0x00000020 0x01010001 0x01010001>,
+ /* NAND_ECC */
+ <0x0000002c 0x01010001 0x01010001>,
+ /* NAND_READ_ECC */
+ <0x00000030 0x01010001 0x01010001>,
+ /* NAND_WRITE_ECC */
+ <0x00000034 0x01010001 0x01010001>,
+ /* OCRAM_ECC */
+ <0x00000038 0x01010001 0x01010001>,
+ /* SDMMC_ECC */
+ <0x00000040 0x01010001 0x01010001>,
+ /* USB0_ECC */
+ <0x00000044 0x01010001 0x01010001>,
+ /* USB1_CACHEECC */
+ <0x00000048 0x01010001 0x01010001>,
+ /* CLOCK_MANAGER */
+ <0x0000004c 0x01010001 0x01010001>,
+ /* IO_MANAGER */
+ <0x00000054 0x01010001 0x01010001>,
+ /* RESET_MANAGER */
+ <0x00000058 0x01010001 0x01010001>,
+ /* SYSTEM_MANAGER */
+ <0x0000005c 0x01010001 0x01010001>,
+ /* OSC0_TIMER */
+ <0x00000060 0x01010301 0x01010301>,
+ /* OSC1_TIMER0*/
+ <0x00000064 0x01010301 0x01010301>,
+ /* WATCHDOG0 */
+ <0x00000068 0x01010301 0x01010301>,
+ /* WATCHDOG1 */
+ <0x0000006c 0x01010301 0x01010301>,
+ /* WATCHDOG2 */
+ <0x00000070 0x01010301 0x01010301>,
+ /* WATCHDOG3 */
+ <0x00000074 0x01010301 0x01010301>,
+ /* DAP */
+ <0x00000078 0x03010001 0x03010001>,
+ /* WATCHDOG4 */
+ <0x0000007c 0x01010301 0x01010301>,
+ /* POWER_MANAGER */
+ <0x00000080 0x01010001 0x01010001>,
+ /* USB1_RXECC */
+ <0x00000084 0x01010001 0x01010001>,
+ /* USB1_TXECC */
+ <0x00000088 0x01010001 0x01010001>,
+ /* L4_NOC_PROBES */
+ <0x00000090 0x01010001 0x01010001>,
+ /* L4_NOC_QOS */
+ <0x00000094 0x01010001 0x01010001>;
+ bootph-all;
+ };
+
+ /* Light weight SoC2FPGA */
+ noc_fw_lwsoc2fpga@10d21300 {
+ reg = <0x10d21300 0x0000004>;
+ intel,offset-settings =
+ /* LWSOC2FPGA_CSR */
+ <0x00000000 0x0ffe0301 0x0ffe0301>;
+ bootph-all;
+ };
+
+ /* SoC2FPGA */
+ noc_fw_soc2fpga@10d21200 {
+ reg = <0x10d21200 0x0000004>;
+ intel,offset-settings =
+ /* SOC2FPGA_CSR */
+ <0x00000000 0x0ffe0301 0x0ffe0301>;
+ bootph-all;
+ };
+
+ /* TCU */
+ noc_fw_tcu@10d21400 {
+ reg = <0x10d21400 0x0000004>;
+ intel,offset-settings =
+ /* TCU_CSR */
+ <0x00000000 0x01010001 0x01010001>;
+ bootph-all;
+ };
+ };
};
};
--
2.25.1
next prev parent reply other threads:[~2024-09-20 7:04 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-20 7:02 [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses tien.fong.chee
2024-09-21 13:47 ` Marek Vasut
2024-09-24 4:45 ` Chee, Tien Fong
2024-09-24 18:35 ` Marek Vasut
2024-09-20 7:02 ` [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager tien.fong.chee
2024-09-21 13:47 ` Marek Vasut
2024-09-24 5:58 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices tien.fong.chee
2024-09-21 13:48 ` Marek Vasut
2024-09-24 5:48 ` Chee, Tien Fong
2024-09-24 18:35 ` Marek Vasut
2024-09-25 6:06 ` Chee, Tien Fong
2024-09-25 12:50 ` Marek Vasut
2024-09-20 7:02 ` [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization tien.fong.chee
2024-09-21 13:49 ` Marek Vasut
2024-09-24 3:14 ` Chee, Tien Fong
2024-09-24 18:32 ` Marek Vasut
2024-09-25 5:40 ` Chee, Tien Fong
2024-09-25 12:50 ` Marek Vasut
2024-09-26 6:02 ` Chee, Tien Fong
2024-09-26 22:37 ` Marek Vasut
2024-09-27 4:53 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 05/20] arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 06/20] arm: dts: agilex5: Add HPS cache coherency unit configuration settings tien.fong.chee
2024-09-20 7:02 ` tien.fong.chee [this message]
2024-09-20 7:02 ` [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC tien.fong.chee
2024-09-21 13:50 ` Marek Vasut
2024-09-24 6:02 ` Chee, Tien Fong
2024-09-24 18:36 ` Marek Vasut
2024-09-25 6:13 ` Chee, Tien Fong
2024-09-25 12:51 ` Marek Vasut
2024-09-26 5:43 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device tien.fong.chee
2024-09-21 13:51 ` Marek Vasut
2024-09-24 8:52 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 10/20] arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 11/20] arm: socfpga: agilex5: Add SMMU initialization tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info tien.fong.chee
2024-09-21 13:53 ` Marek Vasut
2024-09-24 6:05 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable tien.fong.chee
2024-09-21 13:53 ` Marek Vasut
2024-09-24 7:30 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 14/20] configs: agilex5: Add configuration for malloc pool tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command tien.fong.chee
2024-09-21 13:58 ` Marek Vasut
2024-09-24 6:03 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 16/20] ddr: altera: Add DDR driver for Agilex5 series tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 17/20] arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 19/20] arm: socfpga: soc64: Add support for board_boot_order() tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 20/20] configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS tien.fong.chee
2024-09-20 7:25 ` [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot Simon Glass
2024-09-20 7:30 ` Chee, Tien Fong
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