From: tien.fong.chee@intel.com
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Meng Tingting <tingting.meng@intel.com>,
Yuslaimi Alif Zakuan <alif.zakuan.yuslaimi@intel.com>,
Hea Kok Kiang <kok.kiang.hea@intel.com>,
Tien Fong Chee <tien.fong.chee@intel.com>
Subject: [PATCH v1 06/20] arm: dts: agilex5: Add HPS cache coherency unit configuration settings
Date: Fri, 20 Sep 2024 15:02:28 +0800 [thread overview]
Message-ID: <20240920070242.20884-7-tien.fong.chee@intel.com> (raw)
In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com>
From: Tien Fong Chee <tien.fong.chee@intel.com>
These configuration settings are required to enable cache maintenance and
access between initiators and targets.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 209 +++++++++++++++++++++++
1 file changed, 209 insertions(+)
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index a8167e5c14a..ec42fd01a9c 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -13,6 +13,215 @@
#size-cells = <2>;
bootph-all;
};
+
+ soc {
+ bootph-all;
+
+ socfpga_ccu_config: socfpga-ccu-config {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* DSU */
+ i_ccu_caiu0@1c000000 {
+ reg = <0x1c000000 0x00001000>;
+ intel,offset-settings =
+ /* CAIUMIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DII1_MPFEREGS */
+ <0x00000414 0x00018000 0xffffffff>,
+ <0x00000418 0x00000000 0x000000ff>,
+ <0x00000410 0xc0e00200 0xc1f03e1f>,
+ /* DII2_GICREGS */
+ <0x00000424 0x0001d000 0xffffffff>,
+ <0x00000428 0x00000000 0x000000ff>,
+ <0x00000420 0xc0800400 0xc1f03e1f>,
+ /* NCAIU0_LWSOC2FPGA */
+ <0x00000444 0x00020000 0xffffffff>,
+ <0x00000448 0x00000000 0x000000ff>,
+ <0x00000440 0xc1100006 0xc1f03e1f>,
+ /* NCAIU0_SOC2FPGA_1G */
+ <0x00000454 0x00040000 0xffffffff>,
+ <0x00000458 0x00000000 0x000000ff>,
+ <0x00000450 0xc1200006 0xc1f03e1f>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* NCAIU0_SOC2FPGA_16G */
+ <0x00000474 0x00400000 0xffffffff>,
+ <0x00000478 0x00000000 0x000000ff>,
+ <0x00000470 0xc1600006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* NCAIU0_SOC2FPGA_256G */
+ <0x00000494 0x04000000 0xffffffff>,
+ <0x00000498 0x00000000 0x000000ff>,
+ <0x00000490 0xc1a00006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* FPGA2SOC */
+ i_ccu_ncaiu0@1c001000 {
+ reg = <0x1c001000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU0MIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* PSS */
+ <0x00000404 0x00010000 0xffffffff>,
+ <0x00000408 0x00000000 0x000000ff>,
+ <0x00000400 0xC0F00000 0xc1f03e1f>,
+ /* DII1_MPFEREGS */
+ <0x00000414 0x00018000 0xffffffff>,
+ <0x00000418 0x00000000 0x000000ff>,
+ <0x00000410 0xc0e00200 0xc1f03e1f>,
+ /* NCAIU0_LWSOC2FPGA */
+ <0x00000444 0x00020000 0xffffffff>,
+ <0x00000448 0x00000000 0x000000ff>,
+ <0x00000440 0xc1100006 0xc1f03e1f>,
+ /* NCAIU0_SOC2FPGA_1G */
+ <0x00000454 0x00040000 0xffffffff>,
+ <0x00000458 0x00000000 0x000000ff>,
+ <0x00000450 0xc1200006 0xc1f03e1f>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* NCAIU0_SOC2FPGA_16G */
+ <0x00000474 0x00400000 0xffffffff>,
+ <0x00000478 0x00000000 0x000000ff>,
+ <0x00000470 0xc1600006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* NCAIU0_SOC2FPGA_256G */
+ <0x00000494 0x04000000 0xffffffff>,
+ <0x00000498 0x00000000 0x000000ff>,
+ <0x00000490 0xc1a00006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* GIC_M */
+ i_ccu_ncaiu1@1c002000 {
+ reg = <0x1c002000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU1MIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* SMMU */
+ i_ccu_ncaiu2@1c003000 {
+ reg = <0x1c003000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU2MIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* PSS NOC */
+ i_ccu_ncaiu3@1c004000 {
+ reg = <0x1c004000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU3MIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DII1_MPFEREGS */
+ <0x00000414 0x00018000 0xffffffff>,
+ <0x00000418 0x00000000 0x000000ff>,
+ <0x00000410 0xc0e00200 0xc1f03e1f>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* DCE0 */
+ i_ccu_dce0@1c005000 {
+ reg = <0x1c005000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUMIFSR0 */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* DCE1 */
+ i_ccu_dce1@1c006000 {
+ reg = <0x1c006000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUMIFSR1 */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* DMI0 */
+ i_ccu_dmi0@1c007000 {
+ reg = <0x1c007000 0x00001000>;
+ intel,offset-settings =
+ /* DMIUSMCTCR */
+ <0x00000300 0x00000001 0x00000003>,
+ <0x00000300 0x00000003 0x00000003>;
+ bootph-all;
+ };
+
+ /* DMI1 */
+ i_ccu_dmi0@1c008000 {
+ reg = <0x1c008000 0x00001000>;
+ intel,offset-settings =
+ /* DMIUSMCTCR */
+ <0x00000300 0x00000001 0x00000003>,
+ <0x00000300 0x00000003 0x00000003>;
+ bootph-all;
+ };
+ };
+ };
};
&clkmgr {
--
2.25.1
next prev parent reply other threads:[~2024-09-20 7:05 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-20 7:02 [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses tien.fong.chee
2024-09-21 13:47 ` Marek Vasut
2024-09-24 4:45 ` Chee, Tien Fong
2024-09-24 18:35 ` Marek Vasut
2024-09-20 7:02 ` [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager tien.fong.chee
2024-09-21 13:47 ` Marek Vasut
2024-09-24 5:58 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices tien.fong.chee
2024-09-21 13:48 ` Marek Vasut
2024-09-24 5:48 ` Chee, Tien Fong
2024-09-24 18:35 ` Marek Vasut
2024-09-25 6:06 ` Chee, Tien Fong
2024-09-25 12:50 ` Marek Vasut
2024-09-20 7:02 ` [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization tien.fong.chee
2024-09-21 13:49 ` Marek Vasut
2024-09-24 3:14 ` Chee, Tien Fong
2024-09-24 18:32 ` Marek Vasut
2024-09-25 5:40 ` Chee, Tien Fong
2024-09-25 12:50 ` Marek Vasut
2024-09-26 6:02 ` Chee, Tien Fong
2024-09-26 22:37 ` Marek Vasut
2024-09-27 4:53 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 05/20] arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device tien.fong.chee
2024-09-20 7:02 ` tien.fong.chee [this message]
2024-09-20 7:02 ` [PATCH v1 07/20] arm: dts: agilex5: Add firewall configure settings tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC tien.fong.chee
2024-09-21 13:50 ` Marek Vasut
2024-09-24 6:02 ` Chee, Tien Fong
2024-09-24 18:36 ` Marek Vasut
2024-09-25 6:13 ` Chee, Tien Fong
2024-09-25 12:51 ` Marek Vasut
2024-09-26 5:43 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device tien.fong.chee
2024-09-21 13:51 ` Marek Vasut
2024-09-24 8:52 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 10/20] arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 11/20] arm: socfpga: agilex5: Add SMMU initialization tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info tien.fong.chee
2024-09-21 13:53 ` Marek Vasut
2024-09-24 6:05 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable tien.fong.chee
2024-09-21 13:53 ` Marek Vasut
2024-09-24 7:30 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 14/20] configs: agilex5: Add configuration for malloc pool tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command tien.fong.chee
2024-09-21 13:58 ` Marek Vasut
2024-09-24 6:03 ` Chee, Tien Fong
2024-09-20 7:02 ` [PATCH v1 16/20] ddr: altera: Add DDR driver for Agilex5 series tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 17/20] arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 19/20] arm: socfpga: soc64: Add support for board_boot_order() tien.fong.chee
2024-09-20 7:02 ` [PATCH v1 20/20] configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS tien.fong.chee
2024-09-20 7:25 ` [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot Simon Glass
2024-09-20 7:30 ` Chee, Tien Fong
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