From: Ralf Baechle <ralf@linux-mips.org>
To: Kevin Cernekee <cernekee@gmail.com>
Cc: Shinya Kuribayashi <skuribay@pobox.com>,
linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush
Date: Mon, 18 Oct 2010 23:50:56 +0100 [thread overview]
Message-ID: <20101018225056.GI27377@linux-mips.org> (raw)
In-Reply-To: <AANLkTimmatKpOFATCPDxthN-9pZzzXRAOnLGR1_348=r@mail.gmail.com>
On Mon, Oct 18, 2010 at 12:41:20PM -0700, Kevin Cernekee wrote:
> On Mon, Oct 18, 2010 at 12:19 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> > I'm trying to get a statement from the MIPS architecture guys if the
> > necessity to do anything beyond a cache flush is an architecture violation.
>
> IMO such a requirement would be unnecessarily strict. Larger flushes
> (e.g. page at a time) tend to benefit from some form of pipelining or
> write gathering. Forcing the processor to flush exactly 32 bytes at a
> time, synchronously, could really slow things down and thrash the
> memory controller.
>
> I have not been able to find any official statement from MIPS that
> says that CACHE + SYNC should be used, but that seems like the most
> intuitive way to implement things on the hardware side.
I agree with you but I seem to remember having read something that suggests
otherwise. Oh well, maybe it's just something in the Cambridge water
that makes my halocinate ;)
Ralf
next prev parent reply other threads:[~2010-10-18 22:51 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-16 21:22 [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-17 17:01 ` Florian Fainelli
2010-10-16 21:22 ` [PATCH 3/9] MIPS: Add BMIPS CP0 register definitions Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-20 7:23 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH 4/9] MIPS: Install handlers for software IRQs Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-21 14:44 ` Ralf Baechle
2011-05-19 12:31 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 5/9] MIPS: sync after cacheflush Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-18 13:44 ` Shinya Kuribayashi
2010-10-18 18:34 ` Kevin Cernekee
2010-10-19 0:03 ` Shinya Kuribayashi
2010-10-19 0:51 ` Kevin Cernekee
2010-10-19 13:30 ` Shinya Kuribayashi
2010-10-19 0:57 ` Maciej W. Rozycki
2010-10-19 12:34 ` Ralf Baechle
2010-10-19 20:11 ` Maciej W. Rozycki
2010-10-20 8:05 ` Gleb O. Raiko
2010-10-20 17:26 ` Maciej W. Rozycki
2010-10-21 8:52 ` Gleb O. Raiko
2010-10-24 5:12 ` Maciej W. Rozycki
2010-10-18 19:19 ` Ralf Baechle
2010-10-18 19:41 ` Kevin Cernekee
2010-10-18 22:50 ` Ralf Baechle [this message]
2010-10-19 0:45 ` Maciej W. Rozycki
2010-10-19 8:54 ` Gleb O. Raiko
2010-10-19 9:17 ` Ralf Baechle
2010-10-19 10:15 ` Gleb O. Raiko
2010-10-16 21:22 ` [PATCH resend 6/9] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH v2 resend 7/9] MIPS: Move FIXADDR_TOP into spaces.h Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH resend 8/9] MIPS: Honor L2 bypass bit Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-19 16:16 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 processors Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-21 14:32 ` Ralf Baechle
2010-10-17 16:59 ` [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Florian Fainelli
2010-10-20 7:19 ` Ralf Baechle
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