[PATCH 4/9] MIPS: Install handlers for software IRQs

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From: Kevin Cernekee <cernekee@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 4/9] MIPS: Install handlers for software IRQs
Date: Sat, 16 Oct 2010 14:22:33 -0700	[thread overview]
Message-ID: <953858e54ceec800464756a0521abea1@localhost> (raw)
In-Reply-To: <17ebecce124618ddf83ec6fe8e526f93@localhost>

BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/kernel/irq_cpu.c |   14 ++++++--------
 1 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 55c8a3c..436bb2d 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -106,14 +106,12 @@ void __init mips_cpu_irq_init(void)
 	clear_c0_status(ST0_IM);
 	clear_c0_cause(CAUSEF_IP);
 
-	/*
-	 * Only MT is using the software interrupts currently, so we just
-	 * leave them uninitialized for other processors.
-	 */
-	if (cpu_has_mipsmt)
-		for (i = irq_base; i < irq_base + 2; i++)
-			set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
-						 handle_percpu_irq);
+	/* Software interrupts are used for MT/CMT IPI */
+	for (i = irq_base; i < irq_base + 2; i++)
+		set_irq_chip_and_handler(i, cpu_has_mipsmt ?
+					 &mips_mt_cpu_irq_controller :
+					 &mips_cpu_irq_controller,
+					 handle_percpu_irq);
 
 	for (i = irq_base + 2; i < irq_base + 8; i++)
 		set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
-- 
1.7.0.4

WARNING: multiple messages have this Message-ID (diff)

From: Kevin Cernekee <cernekee@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: [PATCH 4/9] MIPS: Install handlers for software IRQs
Date: Sat, 16 Oct 2010 14:22:33 -0700	[thread overview]
Message-ID: <953858e54ceec800464756a0521abea1@localhost> (raw)
Message-ID: <20101016212233.5V0tsrpXyZIpQJEx--WLlTRlRF4iGotgoKgfwCAh3_c@z> (raw)
In-Reply-To: <17ebecce124618ddf83ec6fe8e526f93@localhost>

BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/kernel/irq_cpu.c |   14 ++++++--------
 1 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 55c8a3c..436bb2d 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -106,14 +106,12 @@ void __init mips_cpu_irq_init(void)
 	clear_c0_status(ST0_IM);
 	clear_c0_cause(CAUSEF_IP);
 
-	/*
-	 * Only MT is using the software interrupts currently, so we just
-	 * leave them uninitialized for other processors.
-	 */
-	if (cpu_has_mipsmt)
-		for (i = irq_base; i < irq_base + 2; i++)
-			set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
-						 handle_percpu_irq);
+	/* Software interrupts are used for MT/CMT IPI */
+	for (i = irq_base; i < irq_base + 2; i++)
+		set_irq_chip_and_handler(i, cpu_has_mipsmt ?
+					 &mips_mt_cpu_irq_controller :
+					 &mips_cpu_irq_controller,
+					 handle_percpu_irq);
 
 	for (i = irq_base + 2; i < irq_base + 8; i++)
 		set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
-- 
1.7.0.4

next prev parent reply	other threads:[~2010-10-16 21:45 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-16 21:22 [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-17 17:01   ` Florian Fainelli
2010-10-16 21:22 ` [PATCH 3/9] MIPS: Add BMIPS CP0 register definitions Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-20  7:23   ` Ralf Baechle
2010-10-16 21:22 ` Kevin Cernekee [this message]
2010-10-16 21:22   ` [PATCH 4/9] MIPS: Install handlers for software IRQs Kevin Cernekee
2010-10-21 14:44   ` Ralf Baechle
2011-05-19 12:31   ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 5/9] MIPS: sync after cacheflush Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-18 13:44   ` Shinya Kuribayashi
2010-10-18 18:34     ` Kevin Cernekee
2010-10-19  0:03       ` Shinya Kuribayashi
2010-10-19  0:51         ` Kevin Cernekee
2010-10-19 13:30           ` Shinya Kuribayashi
2010-10-19  0:57       ` Maciej W. Rozycki
2010-10-19 12:34         ` Ralf Baechle
2010-10-19 20:11           ` Maciej W. Rozycki
2010-10-20  8:05             ` Gleb O. Raiko
2010-10-20 17:26               ` Maciej W. Rozycki
2010-10-21  8:52                 ` Gleb O. Raiko
2010-10-24  5:12                   ` Maciej W. Rozycki
2010-10-18 19:19     ` Ralf Baechle
2010-10-18 19:41       ` Kevin Cernekee
2010-10-18 22:50         ` Ralf Baechle
2010-10-19  0:45           ` Maciej W. Rozycki
2010-10-19  8:54         ` Gleb O. Raiko
2010-10-19  9:17           ` Ralf Baechle
2010-10-19 10:15             ` Gleb O. Raiko
2010-10-16 21:22 ` [PATCH resend 6/9] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH v2 resend 7/9] MIPS: Move FIXADDR_TOP into spaces.h Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH resend 8/9] MIPS: Honor L2 bypass bit Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-19 16:16   ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 processors Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-21 14:32   ` Ralf Baechle
2010-10-17 16:59 ` [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Florian Fainelli
2010-10-20  7:19 ` Ralf Baechle

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:55c8a3c dfblob:436bb2d dfblob:55c8a3c dfblob:436bb2d )
 OR (
bs:"[PATCH 4/9] MIPS: Install handlers for software IRQs" )
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