From: Kevin Cernekee <cernekee@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH resend 8/9] MIPS: Honor L2 bypass bit
Date: Sat, 16 Oct 2010 14:22:37 -0700 [thread overview]
Message-ID: <a87064966b36ed9982d8cf05169c5524@localhost> (raw)
In-Reply-To: <17ebecce124618ddf83ec6fe8e526f93@localhost>
If CP0 CONFIG2 bit 12 (L2B) is set, the L2 cache is disabled and
therefore Linux should not attempt to use it.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/mm/sc-mips.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8..d072b25 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -79,6 +79,11 @@ static inline int __init mips_sc_probe(void)
return 0;
config2 = read_c0_config2();
+
+ /* bypass bit */
+ if (config2 & (1 << 12))
+ return 0;
+
tmp = (config2 >> 4) & 0x0f;
if (0 < tmp && tmp <= 7)
c->scache.linesz = 2 << tmp;
--
1.7.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Kevin Cernekee <cernekee@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: [PATCH resend 8/9] MIPS: Honor L2 bypass bit
Date: Sat, 16 Oct 2010 14:22:37 -0700 [thread overview]
Message-ID: <a87064966b36ed9982d8cf05169c5524@localhost> (raw)
Message-ID: <20101016212237.m9KLyVi0fMXAeOSsYkXMDV6UqRgIl3GGlPlJATS2xtg@z> (raw)
In-Reply-To: <17ebecce124618ddf83ec6fe8e526f93@localhost>
If CP0 CONFIG2 bit 12 (L2B) is set, the L2 cache is disabled and
therefore Linux should not attempt to use it.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/mm/sc-mips.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8..d072b25 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -79,6 +79,11 @@ static inline int __init mips_sc_probe(void)
return 0;
config2 = read_c0_config2();
+
+ /* bypass bit */
+ if (config2 & (1 << 12))
+ return 0;
+
tmp = (config2 >> 4) & 0x0f;
if (0 < tmp && tmp <= 7)
c->scache.linesz = 2 << tmp;
--
1.7.0.4
next prev parent reply other threads:[~2010-10-16 21:46 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-16 21:22 [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-17 17:01 ` Florian Fainelli
2010-10-16 21:22 ` [PATCH 3/9] MIPS: Add BMIPS CP0 register definitions Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-20 7:23 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH 4/9] MIPS: Install handlers for software IRQs Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-21 14:44 ` Ralf Baechle
2011-05-19 12:31 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 5/9] MIPS: sync after cacheflush Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-18 13:44 ` Shinya Kuribayashi
2010-10-18 18:34 ` Kevin Cernekee
2010-10-19 0:03 ` Shinya Kuribayashi
2010-10-19 0:51 ` Kevin Cernekee
2010-10-19 13:30 ` Shinya Kuribayashi
2010-10-19 0:57 ` Maciej W. Rozycki
2010-10-19 12:34 ` Ralf Baechle
2010-10-19 20:11 ` Maciej W. Rozycki
2010-10-20 8:05 ` Gleb O. Raiko
2010-10-20 17:26 ` Maciej W. Rozycki
2010-10-21 8:52 ` Gleb O. Raiko
2010-10-24 5:12 ` Maciej W. Rozycki
2010-10-18 19:19 ` Ralf Baechle
2010-10-18 19:41 ` Kevin Cernekee
2010-10-18 22:50 ` Ralf Baechle
2010-10-19 0:45 ` Maciej W. Rozycki
2010-10-19 8:54 ` Gleb O. Raiko
2010-10-19 9:17 ` Ralf Baechle
2010-10-19 10:15 ` Gleb O. Raiko
2010-10-16 21:22 ` [PATCH resend 6/9] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH v2 resend 7/9] MIPS: Move FIXADDR_TOP into spaces.h Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee [this message]
2010-10-16 21:22 ` [PATCH resend 8/9] MIPS: Honor L2 bypass bit Kevin Cernekee
2010-10-19 16:16 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 processors Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-21 14:32 ` Ralf Baechle
2010-10-17 16:59 ` [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Florian Fainelli
2010-10-20 7:19 ` Ralf Baechle
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