From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Kevin Cernekee <cernekee@gmail.com>,
Shinya Kuribayashi <skuribay@pobox.com>,
linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush
Date: Wed, 20 Oct 2010 12:05:42 +0400 [thread overview]
Message-ID: <4CBEA2D6.6050507@niisi.msk.ru> (raw)
In-Reply-To: <alpine.LFD.2.00.1010192039550.15889@eddie.linux-mips.org>
On 20.10.2010 0:11, Maciej W. Rozycki wrote:
> That said, R4k DECstations seem to perform aggressive write buffering in
> the chipset and to make sure a write has propagated to an MMIO register a
> SYNC and an uncached read operation are necessary.
Just uncached read may be enough. R4k shall pull data from its store
buffer on uncached read.
> I haven't investigated DMA dependencies and I think we currently only
> have one TURBOchannel device/driver only (that is the DEFTA/defxx FDDI
> thingy) making use of the generic DMA API on DECstations. It seemed to
> work correctly the last time I tried; presumably either because the API
> Does The Right Thing, or by pure luck and right timings.
dfx_writel issues sync after store. BTW, it seems no uncached read
issued here (just mb() is used, which seems to do sync only), so either
those uncached read is not needed (unlikely) or data from dfx_writel
wait somewhere in the chipset for being pulled by subsequent reads or
writes.
Gleb.
next prev parent reply other threads:[~2010-10-20 7:50 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-16 21:22 [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-17 17:01 ` Florian Fainelli
2010-10-16 21:22 ` [PATCH 3/9] MIPS: Add BMIPS CP0 register definitions Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-20 7:23 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH 4/9] MIPS: Install handlers for software IRQs Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-21 14:44 ` Ralf Baechle
2011-05-19 12:31 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 5/9] MIPS: sync after cacheflush Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-18 13:44 ` Shinya Kuribayashi
2010-10-18 18:34 ` Kevin Cernekee
2010-10-19 0:03 ` Shinya Kuribayashi
2010-10-19 0:51 ` Kevin Cernekee
2010-10-19 13:30 ` Shinya Kuribayashi
2010-10-19 0:57 ` Maciej W. Rozycki
2010-10-19 12:34 ` Ralf Baechle
2010-10-19 20:11 ` Maciej W. Rozycki
2010-10-20 8:05 ` Gleb O. Raiko [this message]
2010-10-20 17:26 ` Maciej W. Rozycki
2010-10-21 8:52 ` Gleb O. Raiko
2010-10-24 5:12 ` Maciej W. Rozycki
2010-10-18 19:19 ` Ralf Baechle
2010-10-18 19:41 ` Kevin Cernekee
2010-10-18 22:50 ` Ralf Baechle
2010-10-19 0:45 ` Maciej W. Rozycki
2010-10-19 8:54 ` Gleb O. Raiko
2010-10-19 9:17 ` Ralf Baechle
2010-10-19 10:15 ` Gleb O. Raiko
2010-10-16 21:22 ` [PATCH resend 6/9] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH v2 resend 7/9] MIPS: Move FIXADDR_TOP into spaces.h Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH resend 8/9] MIPS: Honor L2 bypass bit Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-19 16:16 ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 processors Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-21 14:32 ` Ralf Baechle
2010-10-17 16:59 ` [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Florian Fainelli
2010-10-20 7:19 ` Ralf Baechle
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