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From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Kevin Cernekee <cernekee@gmail.com>,
	Shinya Kuribayashi <skuribay@pobox.com>,
	linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
	chris@mips.com
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush
Date: Tue, 19 Oct 2010 14:15:57 +0400	[thread overview]
Message-ID: <4CBD6FDD.3020906@niisi.msk.ru> (raw)
In-Reply-To: <20101019091729.GA31405@linux-mips.org>



On 19.10.2010 13:17, Ralf Baechle wrote:
> On Tue, Oct 19, 2010 at 12:54:33PM +0400, Gleb O. Raiko wrote:
> The MIPS32 BIS v2.6 spec says on page 92:
>
>    "The CACHE instruction and the memory transactions which are sourced by
>     the CACHE instruction, such as cache refill or cache writeback, obey
>     the ordering and completion rules of the SYNC instruction."
>
> That's not as clearly spelt out as one would like but it seems to imply
> that only reads/writes preceeding the CACHE instruction are guaranteed
> to have completed that is the last CACHE instruction that was executed
> may still be incomplete.

I meant another piece:

"For implementations which implement multiple level of caches  ... 
<speaking about inclusive caches here> ... The software must place a 
SYNC instruction after the CACHE instruction whenever there are possible 
writebacks from the inner cache to ensure that the writeback data is 
resident in the outer cache before operating on the
outer cache. ... <the rest of statement is a bogeyman story about not 
doing so>

For implementations which implement muliple level of caches without the 
inclusion property, the use of a SYNC instruction after the CACHE 
instruction is still needed whenever writeback data has to be resident 
in the next level of memory hierarchy."

It seems the last sentence shall be also applied for inclusive caches too.

Gleb.

  reply	other threads:[~2010-10-19 10:00 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-16 21:22 [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Kevin Cernekee
2010-10-16 21:22 ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-17 17:01   ` Florian Fainelli
2010-10-16 21:22 ` [PATCH 3/9] MIPS: Add BMIPS CP0 register definitions Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-20  7:23   ` Ralf Baechle
2010-10-16 21:22 ` [PATCH 4/9] MIPS: Install handlers for software IRQs Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-21 14:44   ` Ralf Baechle
2011-05-19 12:31   ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 5/9] MIPS: sync after cacheflush Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-18 13:44   ` Shinya Kuribayashi
2010-10-18 18:34     ` Kevin Cernekee
2010-10-19  0:03       ` Shinya Kuribayashi
2010-10-19  0:51         ` Kevin Cernekee
2010-10-19 13:30           ` Shinya Kuribayashi
2010-10-19  0:57       ` Maciej W. Rozycki
2010-10-19 12:34         ` Ralf Baechle
2010-10-19 20:11           ` Maciej W. Rozycki
2010-10-20  8:05             ` Gleb O. Raiko
2010-10-20 17:26               ` Maciej W. Rozycki
2010-10-21  8:52                 ` Gleb O. Raiko
2010-10-24  5:12                   ` Maciej W. Rozycki
2010-10-18 19:19     ` Ralf Baechle
2010-10-18 19:41       ` Kevin Cernekee
2010-10-18 22:50         ` Ralf Baechle
2010-10-19  0:45           ` Maciej W. Rozycki
2010-10-19  8:54         ` Gleb O. Raiko
2010-10-19  9:17           ` Ralf Baechle
2010-10-19 10:15             ` Gleb O. Raiko [this message]
2010-10-16 21:22 ` [PATCH resend 6/9] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH v2 resend 7/9] MIPS: Move FIXADDR_TOP into spaces.h Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-16 21:22 ` [PATCH resend 8/9] MIPS: Honor L2 bypass bit Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-19 16:16   ` Ralf Baechle
2010-10-16 21:22 ` [PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 processors Kevin Cernekee
2010-10-16 21:22   ` Kevin Cernekee
2010-10-21 14:32   ` Ralf Baechle
2010-10-17 16:59 ` [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code Florian Fainelli
2010-10-20  7:19 ` Ralf Baechle

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