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From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c
Date: Tue, 26 Sep 2023 17:03:10 +0200	[thread overview]
Message-ID: <20230926150316.1129648-2-cleger@rivosinc.com> (raw)
In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com>

Replace macros by the only two function calls that are done from this
file, store_u8() and load_u8().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/kernel/traps_misaligned.c | 46 +++++-----------------------
 1 file changed, 7 insertions(+), 39 deletions(-)

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 378f5b151443..e7bfb33089c1 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -151,51 +151,19 @@
 #define PRECISION_S 0
 #define PRECISION_D 1
 
-#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn)			\
-static inline type load_##type(const type *addr)			\
-{									\
-	type val;							\
-	asm (#insn " %0, %1"						\
-	: "=&r" (val) : "m" (*addr));					\
-	return val;							\
-}
+static inline u8 load_u8(const u8 *addr)
+{
+	u8 val;
 
-#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn)			\
-static inline void store_##type(type *addr, type val)			\
-{									\
-	asm volatile (#insn " %0, %1\n"					\
-	: : "r" (val), "m" (*addr));					\
-}
+	asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr));
 
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw)
-#if defined(CONFIG_64BIT)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
-#else
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
-
-static inline u64 load_u64(const u64 *addr)
-{
-	return load_u32((u32 *)addr)
-		+ ((u64)load_u32((u32 *)addr + 1) << 32);
+	return val;
 }
 
-static inline void store_u64(u64 *addr, u64 val)
+static inline void store_u8(u8 *addr, u8 val)
 {
-	store_u32((u32 *)addr, val);
-	store_u32((u32 *)addr + 1, val >> 32);
+	asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr));
 }
-#endif
 
 static inline ulong get_insn(ulong mepc)
 {
-- 
2.40.1


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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c
Date: Tue, 26 Sep 2023 17:03:10 +0200	[thread overview]
Message-ID: <20230926150316.1129648-2-cleger@rivosinc.com> (raw)
In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com>

Replace macros by the only two function calls that are done from this
file, store_u8() and load_u8().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/kernel/traps_misaligned.c | 46 +++++-----------------------
 1 file changed, 7 insertions(+), 39 deletions(-)

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 378f5b151443..e7bfb33089c1 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -151,51 +151,19 @@
 #define PRECISION_S 0
 #define PRECISION_D 1
 
-#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn)			\
-static inline type load_##type(const type *addr)			\
-{									\
-	type val;							\
-	asm (#insn " %0, %1"						\
-	: "=&r" (val) : "m" (*addr));					\
-	return val;							\
-}
+static inline u8 load_u8(const u8 *addr)
+{
+	u8 val;
 
-#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn)			\
-static inline void store_##type(type *addr, type val)			\
-{									\
-	asm volatile (#insn " %0, %1\n"					\
-	: : "r" (val), "m" (*addr));					\
-}
+	asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr));
 
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw)
-#if defined(CONFIG_64BIT)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
-#else
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
-
-static inline u64 load_u64(const u64 *addr)
-{
-	return load_u32((u32 *)addr)
-		+ ((u64)load_u32((u32 *)addr + 1) << 32);
+	return val;
 }
 
-static inline void store_u64(u64 *addr, u64 val)
+static inline void store_u8(u8 *addr, u8 val)
 {
-	store_u32((u32 *)addr, val);
-	store_u32((u32 *)addr + 1, val >> 32);
+	asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr));
 }
-#endif
 
 static inline ulong get_insn(ulong mepc)
 {
-- 
2.40.1


  reply	other threads:[~2023-09-26 15:04 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-26 15:03 [PATCH 0/7] Add support to handle misaligned accesses in S-mode Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` Clément Léger [this message]
2023-09-26 15:03   ` [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-09-26 15:03 ` [PATCH 2/7] riscv: add support for misaligned handling in S-mode Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 3/7] riscv: report perf event for misaligned fault Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 4/7] riscv: add floating point insn support to misaligned access emulation Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 6/7] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 21:57   ` Evan Green
2023-09-26 21:57     ` Evan Green
2023-09-28  7:46     ` Clément Léger
2023-09-28  7:46       ` Clément Léger
2023-09-28 16:51       ` Evan Green
2023-09-28 16:51         ` Evan Green
2023-10-03  9:50         ` Atish Kumar Patra
2023-10-03  9:50           ` Atish Kumar Patra
2023-09-29  1:02   ` kernel test robot
2023-09-29  1:02     ` kernel test robot
2023-09-26 15:03 ` [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 21:43 ` [PATCH 0/7] Add support to handle misaligned accesses in S-mode Evan Green
2023-09-26 21:43   ` Evan Green
2023-09-28  7:49   ` Clément Léger
2023-09-28  7:49     ` Clément Léger
2023-09-28 16:48     ` Evan Green
2023-09-28 16:48       ` Evan Green
2023-10-03  8:40       ` Atish Kumar Patra
2023-10-03  8:40         ` Atish Kumar Patra
2023-10-03 15:39         ` ron minnich
2023-10-03 15:39           ` ron minnich
2023-09-30  9:23 ` Conor Dooley
2023-09-30  9:23   ` Conor Dooley
2023-10-02  7:40   ` Clément Léger
2023-10-02  7:40     ` Clément Léger
2023-10-02 10:49     ` Conor Dooley
2023-10-02 10:49       ` Conor Dooley
2023-10-02 11:18       ` Clément Léger
2023-10-02 11:18         ` Clément Léger
2023-10-02 15:32         ` ron minnich
2023-10-02 15:32           ` ron minnich
2023-10-02 22:22           ` Jessica Clarke
2023-10-02 22:22             ` Jessica Clarke
2023-10-03 15:37             ` ron minnich
2023-10-03 15:37               ` ron minnich
2023-10-03  8:12           ` Clément Léger
2023-10-03  8:12             ` Clément Léger
2023-10-04  8:26     ` David Laight
2023-10-04  8:26       ` David Laight
2023-10-04 10:03       ` Clément Léger
2023-10-04 10:03         ` Clément Léger
2023-10-04 14:10         ` David Laight
2023-10-04 14:10           ` David Laight

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